1 /***************************************************************************
2 * Copyright (C) 2018 by Square, Inc. *
3 * Steven Stallion <stallion@squareup.com> *
4 * James Zhao <hjz@squareup.com> *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
18 ***************************************************************************/
24 #include <helper/binarybuffer.h>
25 #include <helper/command.h>
26 #include <helper/log.h>
27 #include <helper/time_support.h>
28 #include <helper/types.h>
29 #include <jtag/interface.h>
30 #include <target/breakpoints.h>
31 #include <target/register.h>
32 #include <target/target.h>
33 #include <target/target_type.h>
37 #define RESET_TIMEOUT 5000 /* 5s */
38 #define STEP_TIMEOUT 1000 /* 1s */
41 * eSi-RISC targets support a configurable number of interrupts;
42 * up to 32 interrupts are supported.
44 static const char * const esirisc_exceptions[] = {
45 "Reset", "HardwareFailure", "NMI", "InstBreakpoint", "DataBreakpoint",
46 "Unsupported", "PrivilegeViolation", "InstBusError", "DataBusError",
47 "AlignmentError", "ArithmeticError", "SystemCall", "MemoryManagement",
48 "Unrecoverable", "Reserved",
50 "Interrupt0", "Interrupt1", "Interrupt2", "Interrupt3",
51 "Interrupt4", "Interrupt5", "Interrupt6", "Interrupt7",
52 "Interrupt8", "Interrupt9", "Interrupt10", "Interrupt11",
53 "Interrupt12", "Interrupt13", "Interrupt14", "Interrupt15",
54 "Interrupt16", "Interrupt17", "Interrupt18", "Interrupt19",
55 "Interrupt20", "Interrupt21", "Interrupt22", "Interrupt23",
56 "Interrupt24", "Interrupt25", "Interrupt26", "Interrupt27",
57 "Interrupt28", "Interrupt29", "Interrupt30", "Interrupt31",
61 * eSi-RISC targets support a configurable number of general purpose
62 * registers; 8, 16, and 32 registers are supported.
65 enum esirisc_reg_num number;
70 { ESIRISC_SP, "sp", REG_TYPE_DATA_PTR, "general" },
71 { ESIRISC_RA, "ra", REG_TYPE_INT, "general" },
72 { ESIRISC_R2, "r2", REG_TYPE_INT, "general" },
73 { ESIRISC_R3, "r3", REG_TYPE_INT, "general" },
74 { ESIRISC_R4, "r4", REG_TYPE_INT, "general" },
75 { ESIRISC_R5, "r5", REG_TYPE_INT, "general" },
76 { ESIRISC_R6, "r6", REG_TYPE_INT, "general" },
77 { ESIRISC_R7, "r7", REG_TYPE_INT, "general" },
78 { ESIRISC_R8, "r8", REG_TYPE_INT, "general" },
79 { ESIRISC_R9, "r9", REG_TYPE_INT, "general" },
80 { ESIRISC_R10, "r10", REG_TYPE_INT, "general" },
81 { ESIRISC_R11, "r11", REG_TYPE_INT, "general" },
82 { ESIRISC_R12, "r12", REG_TYPE_INT, "general" },
83 { ESIRISC_R13, "r13", REG_TYPE_INT, "general" },
84 { ESIRISC_R14, "r14", REG_TYPE_INT, "general" },
85 { ESIRISC_R15, "r15", REG_TYPE_INT, "general" },
86 { ESIRISC_R16, "r16", REG_TYPE_INT, "general" },
87 { ESIRISC_R17, "r17", REG_TYPE_INT, "general" },
88 { ESIRISC_R18, "r18", REG_TYPE_INT, "general" },
89 { ESIRISC_R19, "r19", REG_TYPE_INT, "general" },
90 { ESIRISC_R20, "r20", REG_TYPE_INT, "general" },
91 { ESIRISC_R21, "r21", REG_TYPE_INT, "general" },
92 { ESIRISC_R22, "r22", REG_TYPE_INT, "general" },
93 { ESIRISC_R23, "r23", REG_TYPE_INT, "general" },
94 { ESIRISC_R24, "r24", REG_TYPE_INT, "general" },
95 { ESIRISC_R25, "r25", REG_TYPE_INT, "general" },
96 { ESIRISC_R26, "r26", REG_TYPE_INT, "general" },
97 { ESIRISC_R27, "r27", REG_TYPE_INT, "general" },
98 { ESIRISC_R28, "r28", REG_TYPE_INT, "general" },
99 { ESIRISC_R29, "r29", REG_TYPE_INT, "general" },
100 { ESIRISC_R30, "r30", REG_TYPE_INT, "general" },
101 { ESIRISC_R31, "r31", REG_TYPE_INT, "general" },
105 * Control and Status Registers (CSRs) are largely defined as belonging
106 * to the system register group. The exception to this rule are the PC
107 * and CAS registers, which belong to the general group. While debug is
108 * active, EPC, ECAS, and ETC must be used to read and write the PC,
109 * CAS, and TC CSRs, respectively.
111 static const struct {
112 enum esirisc_reg_num number;
119 { ESIRISC_PC, CSR_THREAD, CSR_THREAD_EPC, "PC", REG_TYPE_CODE_PTR, "general" }, /* PC -> EPC */
120 { ESIRISC_CAS, CSR_THREAD, CSR_THREAD_ECAS, "CAS", REG_TYPE_INT, "general" }, /* CAS -> ECAS */
121 { ESIRISC_TC, CSR_THREAD, CSR_THREAD_ETC, "TC", REG_TYPE_INT, "system" }, /* TC -> ETC */
122 { ESIRISC_ETA, CSR_THREAD, CSR_THREAD_ETA, "ETA", REG_TYPE_INT, "system" },
123 { ESIRISC_ETC, CSR_THREAD, CSR_THREAD_ETC, "ETC", REG_TYPE_INT, "system" },
124 { ESIRISC_EPC, CSR_THREAD, CSR_THREAD_EPC, "EPC", REG_TYPE_CODE_PTR, "system" },
125 { ESIRISC_ECAS, CSR_THREAD, CSR_THREAD_ECAS, "ECAS", REG_TYPE_INT, "system" },
126 { ESIRISC_EID, CSR_THREAD, CSR_THREAD_EID, "EID", REG_TYPE_INT, "system" },
127 { ESIRISC_ED, CSR_THREAD, CSR_THREAD_ED, "ED", REG_TYPE_INT, "system" },
128 { ESIRISC_IP, CSR_INTERRUPT, CSR_INTERRUPT_IP, "IP", REG_TYPE_INT, "system"},
129 { ESIRISC_IM, CSR_INTERRUPT, CSR_INTERRUPT_IM, "IM", REG_TYPE_INT, "system"},
130 { ESIRISC_IS, CSR_INTERRUPT, CSR_INTERRUPT_IS, "IS", REG_TYPE_INT, "system"},
131 { ESIRISC_IT, CSR_INTERRUPT, CSR_INTERRUPT_IT, "IT", REG_TYPE_INT, "system"},
134 static int esirisc_disable_interrupts(struct target *target)
136 struct esirisc_common *esirisc = target_to_esirisc(target);
137 struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
143 retval = esirisc_jtag_read_csr(jtag_info, CSR_THREAD, CSR_THREAD_ETC, &etc);
144 if (retval != ERROR_OK) {
145 LOG_ERROR("%s: failed to read CSR: ETC", target_name(target));
149 etc &= ~(1<<0); /* TC.I */
151 retval = esirisc_jtag_write_csr(jtag_info, CSR_THREAD, CSR_THREAD_ETC, etc);
152 if (retval != ERROR_OK) {
153 LOG_ERROR("%s: failed to write CSR: ETC", target_name(target));
161 static int esirisc_enable_interrupts(struct target *target)
163 struct esirisc_common *esirisc = target_to_esirisc(target);
164 struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
170 retval = esirisc_jtag_read_csr(jtag_info, CSR_THREAD, CSR_THREAD_ETC, &etc);
171 if (retval != ERROR_OK) {
172 LOG_ERROR("%s: failed to read CSR: ETC", target_name(target));
176 etc |= (1<<0); /* TC.I */
178 retval = esirisc_jtag_write_csr(jtag_info, CSR_THREAD, CSR_THREAD_ETC, etc);
179 if (retval != ERROR_OK) {
180 LOG_ERROR("%s: failed to write CSR: ETC", target_name(target));
188 static int esirisc_save_interrupts(struct target *target)
190 struct esirisc_common *esirisc = target_to_esirisc(target);
191 struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
195 int retval = esirisc_jtag_read_csr(jtag_info, CSR_THREAD, CSR_THREAD_ETC,
197 if (retval != ERROR_OK) {
198 LOG_ERROR("%s: failed to read CSR: ETC", target_name(target));
205 static int esirisc_restore_interrupts(struct target *target)
207 struct esirisc_common *esirisc = target_to_esirisc(target);
208 struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
212 int retval = esirisc_jtag_write_csr(jtag_info, CSR_THREAD, CSR_THREAD_ETC,
214 if (retval != ERROR_OK) {
215 LOG_ERROR("%s: failed to write CSR: ETC", target_name(target));
223 static int esirisc_save_hwdc(struct target *target)
225 struct esirisc_common *esirisc = target_to_esirisc(target);
226 struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
230 int retval = esirisc_jtag_read_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_HWDC,
231 &esirisc->hwdc_save);
232 if (retval != ERROR_OK) {
233 LOG_ERROR("%s: failed to read CSR: HWDC", target_name(target));
241 static int esirisc_restore_hwdc(struct target *target)
243 struct esirisc_common *esirisc = target_to_esirisc(target);
244 struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
248 int retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_HWDC,
250 if (retval != ERROR_OK) {
251 LOG_ERROR("%s: failed to write CSR: HWDC", target_name(target));
258 static int esirisc_save_context(struct target *target)
260 struct esirisc_common *esirisc = target_to_esirisc(target);
264 for (unsigned i = 0; i < esirisc->reg_cache->num_regs; ++i) {
265 struct reg *reg = esirisc->reg_cache->reg_list + i;
266 struct esirisc_reg *reg_info = reg->arch_info;
268 if (reg->exist && !reg->valid)
275 static int esirisc_restore_context(struct target *target)
277 struct esirisc_common *esirisc = target_to_esirisc(target);
281 for (unsigned i = 0; i < esirisc->reg_cache->num_regs; ++i) {
282 struct reg *reg = esirisc->reg_cache->reg_list + i;
283 struct esirisc_reg *reg_info = reg->arch_info;
285 if (reg->exist && reg->dirty)
286 reg_info->write(reg);
292 static int esirisc_flush_caches(struct target *target)
294 struct esirisc_common *esirisc = target_to_esirisc(target);
295 struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
299 if (target->state != TARGET_HALTED)
300 return ERROR_TARGET_NOT_HALTED;
302 int retval = esirisc_jtag_flush_caches(jtag_info);
303 if (retval != ERROR_OK) {
304 LOG_ERROR("%s: failed to flush caches", target_name(target));
311 static int esirisc_wait_debug_active(struct esirisc_common *esirisc, int ms)
313 struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
320 int retval = esirisc_jtag_enable_debug(jtag_info);
321 if (retval == ERROR_OK && esirisc_jtag_is_debug_active(jtag_info))
324 if ((timeval_ms() - t) > ms)
325 return ERROR_TARGET_TIMEOUT;
331 static int esirisc_read_memory(struct target *target, target_addr_t address,
332 uint32_t size, uint32_t count, uint8_t *buffer)
334 struct esirisc_common *esirisc = target_to_esirisc(target);
335 struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
340 int num_bits = 8 * size;
341 for (uint32_t i = 0; i < count; ++i) {
342 union esirisc_memory value;
346 case sizeof(value.word):
347 value_p = &value.word;
348 retval = esirisc_jtag_read_word(jtag_info, address, value_p);
351 case sizeof(value.hword):
352 value_p = &value.hword;
353 retval = esirisc_jtag_read_hword(jtag_info, address, value_p);
356 case sizeof(value.byte):
357 value_p = &value.byte;
358 retval = esirisc_jtag_read_byte(jtag_info, address, value_p);
362 LOG_ERROR("%s: unsupported size: %" PRIu32, target_name(target), size);
366 if (retval != ERROR_OK) {
367 LOG_ERROR("%s: failed to read address: 0x%" TARGET_PRIxADDR, target_name(target),
372 buf_cpy(value_p, buffer, num_bits);
380 static int esirisc_write_memory(struct target *target, target_addr_t address,
381 uint32_t size, uint32_t count, const uint8_t *buffer)
383 struct esirisc_common *esirisc = target_to_esirisc(target);
384 struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
389 int num_bits = 8 * size;
390 for (uint32_t i = 0; i < count; ++i) {
391 union esirisc_memory value;
394 case sizeof(value.word):
395 value.word = buf_get_u32(buffer, 0, num_bits);
396 retval = esirisc_jtag_write_word(jtag_info, address, value.word);
399 case sizeof(value.hword):
400 value.hword = buf_get_u32(buffer, 0, num_bits);
401 retval = esirisc_jtag_write_hword(jtag_info, address, value.hword);
404 case sizeof(value.byte):
405 value.byte = buf_get_u32(buffer, 0, num_bits);
406 retval = esirisc_jtag_write_byte(jtag_info, address, value.byte);
410 LOG_ERROR("%s: unsupported size: %" PRIu32, target_name(target), size);
414 if (retval != ERROR_OK) {
415 LOG_ERROR("%s: failed to write address: 0x%" TARGET_PRIxADDR, target_name(target),
427 static int esirisc_checksum_memory(struct target *target, target_addr_t address,
428 uint32_t count, uint32_t *checksum)
430 return ERROR_FAIL; /* not supported */
433 static int esirisc_next_breakpoint(struct target *target)
435 struct esirisc_common *esirisc = target_to_esirisc(target);
436 struct breakpoint **breakpoints_p = esirisc->breakpoints_p;
437 struct breakpoint **breakpoints_e = breakpoints_p + esirisc->num_breakpoints;
441 for (int bp_index = 0; breakpoints_p < breakpoints_e; ++breakpoints_p, ++bp_index)
442 if (*breakpoints_p == NULL)
448 static int esirisc_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
450 struct esirisc_common *esirisc = target_to_esirisc(target);
451 struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
459 * The default linker scripts provided by the eSi-RISC toolchain do
460 * not specify attributes on memory regions, which results in
461 * incorrect application of software breakpoints by GDB. Targets
462 * must be configured with `gdb_breakpoint_override hard` as
463 * software breakpoints are not supported.
465 if (breakpoint->type != BKPT_HARD)
466 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
468 bp_index = esirisc_next_breakpoint(target);
470 LOG_ERROR("%s: out of hardware breakpoints", target_name(target));
471 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
474 breakpoint->set = bp_index + 1;
475 esirisc->breakpoints_p[bp_index] = breakpoint;
477 /* specify instruction breakpoint address */
478 retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_IBAn + bp_index,
479 breakpoint->address);
480 if (retval != ERROR_OK) {
481 LOG_ERROR("%s: failed to write CSR: IBA", target_name(target));
485 /* enable instruction breakpoint */
486 retval = esirisc_jtag_read_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_IBC, &ibc);
487 if (retval != ERROR_OK) {
488 LOG_ERROR("%s: failed to read CSR: IBC", target_name(target));
492 ibc |= (1 << bp_index); /* IBC.In */
494 retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_IBC, ibc);
495 if (retval != ERROR_OK) {
496 LOG_ERROR("%s: failed to write CSR: IBC", target_name(target));
503 static int esirisc_add_breakpoints(struct target *target)
505 struct breakpoint *breakpoint = target->breakpoints;
509 while (breakpoint != NULL) {
510 if (breakpoint->set == 0)
511 esirisc_add_breakpoint(target, breakpoint);
513 breakpoint = breakpoint->next;
519 static int esirisc_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
521 struct esirisc_common *esirisc = target_to_esirisc(target);
522 struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
523 int bp_index = breakpoint->set - 1;
529 /* disable instruction breakpoint */
530 retval = esirisc_jtag_read_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_IBC, &ibc);
531 if (retval != ERROR_OK) {
532 LOG_ERROR("%s: failed to read CSR: IBC", target_name(target));
536 ibc &= ~(1 << bp_index); /* IBC.In */
538 retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_IBC, ibc);
539 if (retval != ERROR_OK) {
540 LOG_ERROR("%s: failed to write CSR: IBC", target_name(target));
544 esirisc->breakpoints_p[bp_index] = NULL;
550 static int esirisc_remove_breakpoints(struct target *target)
552 struct esirisc_common *esirisc = target_to_esirisc(target);
553 struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
557 /* clear instruction breakpoints */
558 int retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_IBC, 0);
559 if (retval != ERROR_OK) {
560 LOG_ERROR("%s: failed to write CSR: IBC", target_name(target));
564 memset(esirisc->breakpoints_p, 0, sizeof(esirisc->breakpoints_p));
569 static int esirisc_next_watchpoint(struct target *target)
571 struct esirisc_common *esirisc = target_to_esirisc(target);
572 struct watchpoint **watchpoints_p = esirisc->watchpoints_p;
573 struct watchpoint **watchpoints_e = watchpoints_p + esirisc->num_watchpoints;
577 for (int wp_index = 0; watchpoints_p < watchpoints_e; ++watchpoints_p, ++wp_index)
578 if (*watchpoints_p == NULL)
584 static int esirisc_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
586 struct esirisc_common *esirisc = target_to_esirisc(target);
587 struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
594 wp_index = esirisc_next_watchpoint(target);
596 LOG_ERROR("%s: out of hardware watchpoints", target_name(target));
600 watchpoint->set = wp_index + 1;
601 esirisc->watchpoints_p[wp_index] = watchpoint;
603 /* specify data breakpoint address */
604 retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DBAn + wp_index,
605 watchpoint->address);
606 if (retval != ERROR_OK) {
607 LOG_ERROR("%s: failed to write CSR: DBA", target_name(target));
611 /* specify data breakpoint size */
612 retval = esirisc_jtag_read_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DBS, &dbs);
613 if (retval != ERROR_OK) {
614 LOG_ERROR("%s: failed to read CSR: DBS", target_name(target));
619 switch (watchpoint->length) {
620 case sizeof(uint64_t):
623 case sizeof(uint32_t):
627 case sizeof(uint16_t):
631 case sizeof(uint8_t):
636 LOG_ERROR("%s: unsupported length: %" PRIu32, target_name(target),
641 dbs |= (sn << (2 * wp_index)); /* DBS.Sn */
643 retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DBS, dbs);
644 if (retval != ERROR_OK) {
645 LOG_ERROR("%s: failed to write CSR: DBS", target_name(target));
649 /* enable data breakpoint */
650 retval = esirisc_jtag_read_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DBC, &dbc);
651 if (retval != ERROR_OK) {
652 LOG_ERROR("%s: failed to read CSR: DBC", target_name(target));
657 switch (watchpoint->rw) {
671 LOG_ERROR("%s: unsupported rw: %" PRId32, target_name(target),
676 dbc |= (dn << (2 * wp_index)); /* DBC.Dn */
678 retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DBC, dbc);
679 if (retval != ERROR_OK) {
680 LOG_ERROR("%s: failed to write CSR: DBC", target_name(target));
687 static int esirisc_add_watchpoints(struct target *target)
689 struct watchpoint *watchpoint = target->watchpoints;
693 while (watchpoint != NULL) {
694 if (watchpoint->set == 0)
695 esirisc_add_watchpoint(target, watchpoint);
697 watchpoint = watchpoint->next;
703 static int esirisc_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
705 struct esirisc_common *esirisc = target_to_esirisc(target);
706 struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
707 int wp_index = watchpoint->set - 1;
713 /* disable data breakpoint */
714 retval = esirisc_jtag_read_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DBC, &dbc);
715 if (retval != ERROR_OK) {
716 LOG_ERROR("%s: failed to read CSR: DBC", target_name(target));
720 dbc &= ~(0x3 << (2 * wp_index)); /* DBC.Dn */
722 retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DBC, dbc);
723 if (retval != ERROR_OK) {
724 LOG_ERROR("%s: failed to write CSR: DBC", target_name(target));
728 esirisc->watchpoints_p[wp_index] = NULL;
734 static int esirisc_remove_watchpoints(struct target *target)
736 struct esirisc_common *esirisc = target_to_esirisc(target);
737 struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
741 /* clear data breakpoints */
742 int retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DBC, 0);
743 if (retval != ERROR_OK) {
744 LOG_ERROR("%s: failed to write CSR: DBC", target_name(target));
748 memset(esirisc->watchpoints_p, 0, sizeof(esirisc->watchpoints_p));
753 static int esirisc_halt(struct target *target)
755 struct esirisc_common *esirisc = target_to_esirisc(target);
756 struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
760 if (target->state == TARGET_HALTED)
763 int retval = esirisc_jtag_break(jtag_info);
764 if (retval != ERROR_OK) {
765 LOG_ERROR("%s: failed to halt target", target_name(target));
769 target->debug_reason = DBG_REASON_DBGRQ;
774 static int esirisc_disable_step(struct target *target)
776 struct esirisc_common *esirisc = target_to_esirisc(target);
777 struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
783 retval = esirisc_jtag_read_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DC, &dc);
784 if (retval != ERROR_OK) {
785 LOG_ERROR("%s: failed to read CSR: DC", target_name(target));
789 dc &= ~(1<<0); /* DC.S */
791 retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DC, dc);
792 if (retval != ERROR_OK) {
793 LOG_ERROR("%s: failed to write CSR: DC", target_name(target));
800 static int esirisc_enable_step(struct target *target)
802 struct esirisc_common *esirisc = target_to_esirisc(target);
803 struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
809 retval = esirisc_jtag_read_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DC, &dc);
810 if (retval != ERROR_OK) {
811 LOG_ERROR("%s: failed to read CSR: DC", target_name(target));
815 dc |= (1<<0); /* DC.S */
817 retval = esirisc_jtag_write_csr(jtag_info, CSR_DEBUG, CSR_DEBUG_DC, dc);
818 if (retval != ERROR_OK) {
819 LOG_ERROR("%s: failed to write CSR: DC", target_name(target));
826 static int esirisc_resume_or_step(struct target *target, int current, target_addr_t address,
827 int handle_breakpoints, int debug_execution, bool step)
829 struct esirisc_common *esirisc = target_to_esirisc(target);
830 struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
831 struct breakpoint *breakpoint = NULL;
836 if (target->state != TARGET_HALTED)
837 return ERROR_TARGET_NOT_HALTED;
839 if (!debug_execution) {
840 target_free_all_working_areas(target);
841 esirisc_add_breakpoints(target);
842 esirisc_add_watchpoints(target);
846 address = buf_get_u32(esirisc->epc->value, 0, esirisc->epc->size);
848 buf_set_u32(esirisc->epc->value, 0, esirisc->epc->size, address);
849 esirisc->epc->dirty = true;
850 esirisc->epc->valid = true;
853 esirisc_restore_context(target);
855 if (esirisc_has_cache(esirisc))
856 esirisc_flush_caches(target);
858 if (handle_breakpoints) {
859 breakpoint = breakpoint_find(target, address);
860 if (breakpoint != NULL)
861 esirisc_remove_breakpoint(target, breakpoint);
865 esirisc_disable_interrupts(target);
866 esirisc_enable_step(target);
867 target->debug_reason = DBG_REASON_SINGLESTEP;
869 esirisc_disable_step(target);
870 esirisc_restore_interrupts(target);
871 target->debug_reason = DBG_REASON_NOTHALTED;
874 esirisc_restore_hwdc(target);
876 retval = esirisc_jtag_continue(jtag_info);
877 if (retval != ERROR_OK) {
878 LOG_ERROR("%s: failed to resume target", target_name(target));
882 register_cache_invalidate(esirisc->reg_cache);
884 if (!debug_execution) {
885 target->state = TARGET_RUNNING;
886 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
888 target->state = TARGET_DEBUG_RUNNING;
889 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
895 static int esirisc_resume(struct target *target, int current, target_addr_t address,
896 int handle_breakpoints, int debug_execution)
900 return esirisc_resume_or_step(target, current, address,
901 handle_breakpoints, debug_execution, false);
904 static int esirisc_step(struct target *target, int current, target_addr_t address,
905 int handle_breakpoints)
909 return esirisc_resume_or_step(target, current, address,
910 handle_breakpoints, 0, true);
913 static int esirisc_debug_step(struct target *target)
915 struct esirisc_common *esirisc = target_to_esirisc(target);
916 struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
921 esirisc_disable_interrupts(target);
922 esirisc_enable_step(target);
924 retval = esirisc_jtag_continue(jtag_info);
925 if (retval != ERROR_OK) {
926 LOG_ERROR("%s: failed to resume target", target_name(target));
930 retval = esirisc_wait_debug_active(esirisc, STEP_TIMEOUT);
931 if (retval != ERROR_OK) {
932 LOG_ERROR("%s: step timed out", target_name(target));
936 esirisc_disable_step(target);
937 esirisc_restore_interrupts(target);
942 static int esirisc_debug_reset(struct target *target)
944 struct esirisc_common *esirisc = target_to_esirisc(target);
945 struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
950 retval = esirisc_jtag_assert_reset(jtag_info);
951 if (retval != ERROR_OK) {
952 LOG_ERROR("%s: failed to assert reset", target_name(target));
956 retval = esirisc_jtag_deassert_reset(jtag_info);
957 if (retval != ERROR_OK) {
958 LOG_ERROR("%s: failed to deassert reset", target_name(target));
962 retval = esirisc_wait_debug_active(esirisc, RESET_TIMEOUT);
963 if (retval != ERROR_OK) {
964 LOG_ERROR("%s: reset timed out", target_name(target));
971 static int esirisc_debug_enable(struct target *target)
973 struct esirisc_common *esirisc = target_to_esirisc(target);
974 struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
979 retval = esirisc_jtag_enable_debug(jtag_info);
980 if (retval != ERROR_OK) {
981 LOG_ERROR("%s: failed to enable debug mode", target_name(target));
986 * The debug clock is inactive until the first command is sent.
987 * If the target is stopped, we must first issue a reset before
988 * attempting further communication. This also handles unpowered
989 * targets, which will respond with all ones and appear active.
991 if (esirisc_jtag_is_stopped(jtag_info)) {
992 LOG_INFO("%s: debug clock inactive; attempting debug reset", target_name(target));
993 retval = esirisc_debug_reset(target);
994 if (retval != ERROR_OK)
997 if (esirisc_jtag_is_stopped(jtag_info)) {
998 LOG_ERROR("%s: target unresponsive; giving up", target_name(target));
1006 static int esirisc_debug_entry(struct target *target)
1008 struct esirisc_common *esirisc = target_to_esirisc(target);
1009 struct breakpoint *breakpoint;
1013 esirisc_save_context(target);
1015 if (esirisc_has_cache(esirisc))
1016 esirisc_flush_caches(target);
1018 if (target->debug_reason != DBG_REASON_SINGLESTEP) {
1019 esirisc_save_interrupts(target);
1021 uint32_t eid = buf_get_u32(esirisc->eid->value, 0, esirisc->eid->size);
1024 * InstBreakpoint exceptions are also raised when a core is
1025 * halted for debugging. The following is required to
1026 * determine if a breakpoint was encountered.
1028 case EID_INST_BREAKPOINT:
1029 breakpoint = breakpoint_find(target,
1030 buf_get_u32(esirisc->epc->value, 0, esirisc->epc->size));
1031 target->debug_reason = (breakpoint != NULL) ?
1032 DBG_REASON_BREAKPOINT : DBG_REASON_DBGRQ;
1036 * eSi-RISC treats watchpoints similarly to breakpoints,
1037 * however GDB will not request to step over the current
1038 * instruction when a watchpoint fires. The following is
1039 * required to resume the target.
1041 case EID_DATA_BREAKPOINT:
1042 esirisc_remove_watchpoints(target);
1043 esirisc_debug_step(target);
1044 esirisc_add_watchpoints(target);
1045 target->debug_reason = DBG_REASON_WATCHPOINT;
1049 target->debug_reason = DBG_REASON_DBGRQ;
1056 static int esirisc_poll(struct target *target)
1058 struct esirisc_common *esirisc = target_to_esirisc(target);
1059 struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
1062 retval = esirisc_jtag_enable_debug(jtag_info);
1063 if (retval != ERROR_OK) {
1064 LOG_ERROR("%s: failed to poll target", target_name(target));
1068 if (esirisc_jtag_is_stopped(jtag_info)) {
1069 LOG_ERROR("%s: target has stopped; reset required", target_name(target));
1070 target->state = TARGET_UNKNOWN;
1071 return ERROR_TARGET_FAILURE;
1074 if (esirisc_jtag_is_debug_active(jtag_info)) {
1075 if (target->state == TARGET_RUNNING || target->state == TARGET_RESET) {
1076 target->state = TARGET_HALTED;
1078 retval = esirisc_debug_entry(target);
1079 if (retval != ERROR_OK)
1082 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1085 } else if (target->state == TARGET_HALTED || target->state == TARGET_RESET) {
1086 target->state = TARGET_RUNNING;
1087 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1093 static int esirisc_assert_reset(struct target *target)
1095 struct esirisc_common *esirisc = target_to_esirisc(target);
1096 struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
1101 if (jtag_get_reset_config() & RESET_HAS_SRST) {
1102 jtag_add_reset(1, 1);
1103 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) == 0)
1104 jtag_add_reset(0, 1);
1106 esirisc_remove_breakpoints(target);
1107 esirisc_remove_watchpoints(target);
1109 retval = esirisc_jtag_assert_reset(jtag_info);
1110 if (retval != ERROR_OK) {
1111 LOG_ERROR("%s: failed to assert reset", target_name(target));
1116 target->state = TARGET_RESET;
1118 register_cache_invalidate(esirisc->reg_cache);
1123 static int esirisc_reset_entry(struct target *target)
1125 struct esirisc_common *esirisc = target_to_esirisc(target);
1126 struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
1132 /* read exception table address */
1133 retval = esirisc_jtag_read_csr(jtag_info, CSR_THREAD, CSR_THREAD_ETA, &eta);
1134 if (retval != ERROR_OK) {
1135 LOG_ERROR("%s: failed to read CSR: ETA", target_name(target));
1139 /* read reset entry point */
1140 retval = esirisc_jtag_read_word(jtag_info, eta + ENTRY_RESET, &epc);
1141 if (retval != ERROR_OK) {
1142 LOG_ERROR("%s: failed to read address: 0x%" TARGET_PRIxADDR, target_name(target),
1143 (target_addr_t)epc);
1147 /* write reset entry point */
1148 retval = esirisc_jtag_write_csr(jtag_info, CSR_THREAD, CSR_THREAD_EPC, epc);
1149 if (retval != ERROR_OK) {
1150 LOG_ERROR("%s: failed to write CSR: EPC", target_name(target));
1157 static int esirisc_deassert_reset(struct target *target)
1159 struct esirisc_common *esirisc = target_to_esirisc(target);
1160 struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
1165 if (jtag_get_reset_config() & RESET_HAS_SRST) {
1166 jtag_add_reset(0, 0);
1168 retval = esirisc_debug_enable(target);
1169 if (retval != ERROR_OK)
1172 retval = esirisc_debug_reset(target);
1173 if (retval != ERROR_OK)
1177 retval = esirisc_jtag_deassert_reset(jtag_info);
1178 if (retval != ERROR_OK) {
1179 LOG_ERROR("%s: failed to deassert reset", target_name(target));
1184 retval = esirisc_wait_debug_active(esirisc, RESET_TIMEOUT);
1185 if (retval != ERROR_OK) {
1186 LOG_ERROR("%s: reset timed out", target_name(target));
1190 retval = esirisc_reset_entry(target);
1191 if (retval != ERROR_OK)
1194 esirisc_add_breakpoints(target);
1195 esirisc_add_watchpoints(target);
1197 esirisc_restore_hwdc(target);
1199 if (!target->reset_halt) {
1200 retval = esirisc_jtag_continue(jtag_info);
1201 if (retval != ERROR_OK) {
1202 LOG_ERROR("%s: failed to resume target", target_name(target));
1210 static int esirisc_arch_state(struct target *target)
1212 struct esirisc_common *esirisc = target_to_esirisc(target);
1213 uint32_t epc = buf_get_u32(esirisc->epc->value, 0, esirisc->epc->size);
1214 uint32_t ecas = buf_get_u32(esirisc->ecas->value, 0, esirisc->ecas->size);
1215 uint32_t eid = buf_get_u32(esirisc->eid->value, 0, esirisc->eid->size);
1216 uint32_t ed = buf_get_u32(esirisc->ed->value, 0, esirisc->ed->size);
1220 const char *exception = "Unknown";
1221 if (eid < ARRAY_SIZE(esirisc_exceptions))
1222 exception = esirisc_exceptions[eid];
1224 LOG_USER("target halted due to %s, exception: %s\n"
1225 "EPC: 0x%" PRIx32 " ECAS: 0x%" PRIx32 " EID: 0x%" PRIx32 " ED: 0x%" PRIx32,
1226 debug_reason_name(target), exception, epc, ecas, eid, ed);
1231 static const char *esirisc_get_gdb_arch(struct target *target)
1233 struct esirisc_common *esirisc = target_to_esirisc(target);
1238 * Targets with the UNIFIED_ADDRESS_SPACE option disabled employ a
1239 * Harvard architecture. This option is not exposed in a CSR, which
1240 * requires additional configuration to properly interact with these
1241 * targets in GDB (also see: `esirisc cache_arch`).
1243 if (esirisc->gdb_arch == NULL && target_was_examined(target))
1244 esirisc->gdb_arch = alloc_printf("esirisc:%d_bit_%d_reg_%s",
1245 esirisc->num_bits, esirisc->num_regs, esirisc_cache_arch(esirisc));
1247 return esirisc->gdb_arch;
1250 static int esirisc_get_gdb_reg_list(struct target *target, struct reg **reg_list[],
1251 int *reg_list_size, enum target_register_class reg_class)
1253 struct esirisc_common *esirisc = target_to_esirisc(target);
1257 *reg_list_size = ESIRISC_NUM_REGS;
1259 *reg_list = calloc(*reg_list_size, sizeof(struct reg *));
1260 if (*reg_list == NULL)
1263 if (reg_class == REG_CLASS_ALL)
1264 for (int i = 0; i < *reg_list_size; ++i)
1265 (*reg_list)[i] = esirisc->reg_cache->reg_list + i;
1267 for (int i = 0; i < esirisc->num_regs; ++i)
1268 (*reg_list)[i] = esirisc->reg_cache->reg_list + i;
1270 (*reg_list)[ESIRISC_PC] = esirisc->reg_cache->reg_list + ESIRISC_PC;
1271 (*reg_list)[ESIRISC_CAS] = esirisc->reg_cache->reg_list + ESIRISC_CAS;
1277 static int esirisc_read_reg(struct reg *reg)
1279 struct esirisc_reg *reg_info = reg->arch_info;
1280 struct esirisc_common *esirisc = reg_info->esirisc;
1281 struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
1282 struct target *target = esirisc->target;
1287 int retval = esirisc_jtag_read_reg(jtag_info, reg->number, &data);
1288 if (retval != ERROR_OK) {
1289 LOG_ERROR("%s: failed to read register: %s", target_name(target), reg->name);
1293 buf_set_u32(reg->value, 0, reg->size, data);
1300 static int esirisc_write_reg(struct reg *reg)
1302 struct esirisc_reg *reg_info = reg->arch_info;
1303 struct esirisc_common *esirisc = reg_info->esirisc;
1304 struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
1305 struct target *target = esirisc->target;
1306 uint32_t data = buf_get_u32(reg->value, 0, reg->size);
1310 int retval = esirisc_jtag_write_reg(jtag_info, reg->number, data);
1311 if (retval != ERROR_OK) {
1312 LOG_ERROR("%s: failed to write register: %s", target_name(target), reg->name);
1322 static int esirisc_read_csr(struct reg *reg)
1324 struct esirisc_reg *reg_info = reg->arch_info;
1325 struct esirisc_common *esirisc = reg_info->esirisc;
1326 struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
1327 struct target *target = esirisc->target;
1332 int retval = esirisc_jtag_read_csr(jtag_info, reg_info->bank, reg_info->csr, &data);
1333 if (retval != ERROR_OK) {
1334 LOG_ERROR("%s: failed to read CSR: %s", target_name(target), reg->name);
1338 buf_set_u32(reg->value, 0, reg->size, data);
1345 static int esirisc_write_csr(struct reg *reg)
1347 struct esirisc_reg *reg_info = reg->arch_info;
1348 struct esirisc_common *esirisc = reg_info->esirisc;
1349 struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
1350 struct target *target = esirisc->target;
1351 uint32_t data = buf_get_u32(reg->value, 0, reg->size);
1355 int retval = esirisc_jtag_write_csr(jtag_info, reg_info->bank, reg_info->csr, data);
1356 if (retval != ERROR_OK) {
1357 LOG_ERROR("%s: failed to write CSR: %s", target_name(target), reg->name);
1367 static int esirisc_get_reg(struct reg *reg)
1369 struct esirisc_reg *reg_info = reg->arch_info;
1370 struct esirisc_common *esirisc = reg_info->esirisc;
1371 struct target *target = esirisc->target;
1375 if (target->state != TARGET_HALTED)
1376 return ERROR_TARGET_NOT_HALTED;
1378 return reg_info->read(reg);
1381 static int esirisc_set_reg(struct reg *reg, uint8_t *buf)
1383 struct esirisc_reg *reg_info = reg->arch_info;
1384 struct esirisc_common *esirisc = reg_info->esirisc;
1385 struct target *target = esirisc->target;
1386 uint32_t value = buf_get_u32(buf, 0, reg->size);
1390 if (target->state != TARGET_HALTED)
1391 return ERROR_TARGET_NOT_HALTED;
1393 buf_set_u32(reg->value, 0, reg->size, value);
1400 static const struct reg_arch_type esirisc_reg_type = {
1401 .get = esirisc_get_reg,
1402 .set = esirisc_set_reg,
1405 static struct reg_cache *esirisc_build_reg_cache(struct target *target)
1407 struct esirisc_common *esirisc = target_to_esirisc(target);
1408 struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
1409 struct reg_cache *cache = malloc(sizeof(struct reg_cache));
1410 struct reg *reg_list = calloc(ESIRISC_NUM_REGS, sizeof(struct reg));
1414 cache->name = "eSi-RISC registers";
1416 cache->reg_list = reg_list;
1417 cache->num_regs = ESIRISC_NUM_REGS;
1420 esirisc->reg_cache = cache;
1421 esirisc->epc = reg_list + ESIRISC_EPC;
1422 esirisc->ecas = reg_list + ESIRISC_ECAS;
1423 esirisc->eid = reg_list + ESIRISC_EID;
1424 esirisc->ed = reg_list + ESIRISC_ED;
1426 for (int i = 0; i < esirisc->num_regs; ++i) {
1427 struct reg *reg = reg_list + esirisc_regs[i].number;
1428 struct esirisc_reg *reg_info = calloc(1, sizeof(struct esirisc_reg));
1430 reg->name = esirisc_regs[i].name;
1431 reg->number = esirisc_regs[i].number;
1432 reg->value = calloc(1, DIV_ROUND_UP(esirisc->num_bits, 8));
1433 reg->size = esirisc->num_bits;
1434 reg->reg_data_type = calloc(1, sizeof(struct reg_data_type));
1435 reg->reg_data_type->type = esirisc_regs[i].type;
1436 reg->group = esirisc_regs[i].group;
1437 reg_info->esirisc = esirisc;
1438 reg_info->read = esirisc_read_reg;
1439 reg_info->write = esirisc_write_reg;
1440 reg->arch_info = reg_info;
1441 reg->type = &esirisc_reg_type;
1445 for (size_t i = 0; i < ARRAY_SIZE(esirisc_csrs); ++i) {
1446 struct reg *reg = reg_list + esirisc_csrs[i].number;
1447 struct esirisc_reg *reg_info = calloc(1, sizeof(struct esirisc_reg));
1449 reg->name = esirisc_csrs[i].name;
1450 reg->number = esirisc_csrs[i].number;
1451 reg->value = calloc(1, DIV_ROUND_UP(esirisc->num_bits, 8));
1452 reg->size = esirisc->num_bits;
1453 reg->reg_data_type = calloc(1, sizeof(struct reg_data_type));
1454 reg->reg_data_type->type = esirisc_csrs[i].type;
1455 reg->group = esirisc_csrs[i].group;
1456 reg_info->esirisc = esirisc;
1457 reg_info->bank = esirisc_csrs[i].bank;
1458 reg_info->csr = esirisc_csrs[i].csr;
1459 reg_info->read = esirisc_read_csr;
1460 reg_info->write = esirisc_write_csr;
1461 reg->arch_info = reg_info;
1462 reg->type = &esirisc_reg_type;
1469 static int esirisc_identify(struct target *target)
1471 struct esirisc_common *esirisc = target_to_esirisc(target);
1472 struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
1478 retval = esirisc_jtag_read_csr(jtag_info, CSR_CONFIG, CSR_CONFIG_ARCH0, &csr);
1479 if (retval != ERROR_OK) {
1480 LOG_ERROR("%s: failed to read CSR: ARCH0", target_name(target));
1484 esirisc->num_bits = (csr >> 0) & 0x3f; /* ARCH0.B */
1485 esirisc->num_regs = (csr >> 10) & 0x3f; /* ARCH0.R */
1487 retval = esirisc_jtag_read_csr(jtag_info, CSR_CONFIG, CSR_CONFIG_MEM, &csr);
1488 if (retval != ERROR_OK) {
1489 LOG_ERROR("%s: failed to read CSR: MEM", target_name(target));
1493 target->endianness = (csr & 1<<0) ? /* MEM.E */
1494 TARGET_BIG_ENDIAN : TARGET_LITTLE_ENDIAN;
1496 retval = esirisc_jtag_read_csr(jtag_info, CSR_CONFIG, CSR_CONFIG_IC, &csr);
1497 if (retval != ERROR_OK) {
1498 LOG_ERROR("%s: failed to read CSR: IC", target_name(target));
1502 esirisc->has_icache = !!(csr & 1<<0); /* IC.E */
1504 retval = esirisc_jtag_read_csr(jtag_info, CSR_CONFIG, CSR_CONFIG_DC, &csr);
1505 if (retval != ERROR_OK) {
1506 LOG_ERROR("%s: failed to read CSR: DC", target_name(target));
1510 esirisc->has_dcache = !!(csr & 1<<0); /* DC.E */
1512 retval = esirisc_jtag_read_csr(jtag_info, CSR_CONFIG, CSR_CONFIG_DBG, &csr);
1513 if (retval != ERROR_OK) {
1514 LOG_ERROR("%s: failed to read CSR: DBG", target_name(target));
1518 esirisc->num_breakpoints = (csr >> 7) & 0xf; /* DBG.BP */
1519 esirisc->num_watchpoints = (csr >> 12) & 0xf; /* DBG.WP */
1524 static int esirisc_target_create(struct target *target, Jim_Interp *interp)
1526 struct jtag_tap *tap = target->tap;
1527 struct esirisc_common *esirisc;
1532 if (tap->ir_length != INSTR_LENGTH) {
1533 LOG_ERROR("%s: invalid IR length; expected %d", target_name(target),
1538 esirisc = calloc(1, sizeof(struct esirisc_common));
1539 if (esirisc == NULL)
1542 esirisc->target = target;
1543 esirisc->jtag_info.tap = tap;
1544 target->arch_info = esirisc;
1549 static int esirisc_init_target(struct command_context *cmd_ctx, struct target *target)
1551 struct esirisc_common *esirisc = target_to_esirisc(target);
1553 /* trap reset, error, and debug exceptions */
1554 esirisc->hwdc_save = HWDC_R | HWDC_E | HWDC_D;
1559 static int esirisc_examine(struct target *target)
1561 struct esirisc_common *esirisc = target_to_esirisc(target);
1562 struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
1567 if (!target_was_examined(target)) {
1568 retval = esirisc_debug_enable(target);
1569 if (retval != ERROR_OK)
1573 * In order to identify the target we must first halt the core.
1574 * We quietly resume once identification has completed for those
1575 * targets that were running when target_examine was called.
1577 if (esirisc_jtag_is_debug_active(jtag_info)) {
1578 if (target->state == TARGET_UNKNOWN)
1579 target->debug_reason = DBG_REASON_DBGRQ;
1581 target->state = TARGET_HALTED;
1583 retval = esirisc_jtag_break(jtag_info);
1584 if (retval != ERROR_OK) {
1585 LOG_ERROR("%s: failed to halt target", target_name(target));
1589 target->state = TARGET_RUNNING;
1592 retval = esirisc_identify(target);
1593 if (retval != ERROR_OK) {
1594 LOG_ERROR("%s: failed to identify target", target_name(target));
1598 esirisc_build_reg_cache(target);
1600 esirisc_remove_breakpoints(target);
1601 esirisc_remove_watchpoints(target);
1603 esirisc_disable_step(target);
1604 esirisc_restore_hwdc(target);
1606 if (target->state == TARGET_HALTED)
1607 esirisc_save_interrupts(target);
1609 retval = esirisc_jtag_continue(jtag_info);
1610 if (retval != ERROR_OK) {
1611 LOG_ERROR("%s: failed to resume target", target_name(target));
1616 target_set_examined(target);
1618 LOG_INFO("%s: %d bit, %d registers, %s%s%s", target_name(target),
1619 esirisc->num_bits, esirisc->num_regs,
1620 target_endianness(target),
1621 esirisc->has_icache ? ", icache" : "",
1622 esirisc->has_dcache ? ", dcache" : "");
1624 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints", target_name(target),
1625 esirisc->num_breakpoints, esirisc->num_watchpoints);
1631 COMMAND_HANDLER(handle_esirisc_cache_arch_command)
1633 struct target *target = get_current_target(CMD_CTX);
1634 struct esirisc_common *esirisc = target_to_esirisc(target);
1637 if (strcmp(*CMD_ARGV, "harvard") == 0)
1638 esirisc->cache_arch = ESIRISC_CACHE_HARVARD;
1639 else if (strcmp(*CMD_ARGV, "von_neumann") == 0)
1640 esirisc->cache_arch = ESIRISC_CACHE_VON_NEUMANN;
1642 LOG_ERROR("invalid cache_arch: %s", *CMD_ARGV);
1643 return ERROR_COMMAND_SYNTAX_ERROR;
1647 command_print(CMD_CTX, "esirisc cache_arch %s", esirisc_cache_arch(esirisc));
1652 COMMAND_HANDLER(handle_esirisc_flush_caches_command)
1654 struct target *target = get_current_target(CMD_CTX);
1655 struct esirisc_common *esirisc = target_to_esirisc(target);
1658 if (!esirisc_has_cache(esirisc)) {
1659 LOG_ERROR("target does not support caching");
1663 retval = esirisc_flush_caches(target);
1665 command_print(CMD_CTX, "cache flush %s",
1666 (retval == ERROR_OK) ? "successful" : "failed");
1671 static const struct {
1674 } esirisc_hwdc_masks[] = {
1675 { "reset", HWDC_R },
1676 { "interrupt", HWDC_I },
1677 { "syscall", HWDC_S },
1678 { "error", HWDC_E },
1679 { "debug", HWDC_D },
1682 static int esirisc_find_hwdc_mask(const char *name)
1684 for (size_t i = 0; i < ARRAY_SIZE(esirisc_hwdc_masks); ++i)
1685 if (strcmp(esirisc_hwdc_masks[i].name, name) == 0)
1686 return esirisc_hwdc_masks[i].mask;
1691 COMMAND_HANDLER(handle_esirisc_hwdc_command)
1693 struct target *target = get_current_target(CMD_CTX);
1694 struct esirisc_common *esirisc = target_to_esirisc(target);
1697 if (strcmp(CMD_ARGV[0], "all") == 0)
1698 esirisc->hwdc_save = HWDC_R | HWDC_I | HWDC_S | HWDC_E | HWDC_D;
1700 esirisc->hwdc_save = 0;
1701 if (strcmp(CMD_ARGV[0], "none") != 0) {
1702 while (CMD_ARGC-- > 0) {
1703 int mask = esirisc_find_hwdc_mask(CMD_ARGV[CMD_ARGC]);
1705 LOG_ERROR("invalid mask: %s", CMD_ARGV[CMD_ARGC]);
1706 return ERROR_COMMAND_SYNTAX_ERROR;
1708 esirisc->hwdc_save |= mask;
1714 for (size_t i = 0; i < ARRAY_SIZE(esirisc_hwdc_masks); ++i)
1715 command_print(CMD_CTX, "%9s: %s", esirisc_hwdc_masks[i].name,
1716 (esirisc->hwdc_save & esirisc_hwdc_masks[i].mask) ? "enabled" : "disabled");
1721 static const struct command_registration esirisc_exec_command_handlers[] = {
1723 .name = "cache_arch",
1724 .handler = handle_esirisc_cache_arch_command,
1725 .mode = COMMAND_ANY,
1726 .help = "configure cache architecture",
1727 .usage = "['harvard'|'von_neumann']",
1730 .name = "flush_caches",
1731 .handler = handle_esirisc_flush_caches_command,
1732 .mode = COMMAND_EXEC,
1733 .help = "flush instruction and data caches",
1738 .handler = handle_esirisc_hwdc_command,
1739 .mode = COMMAND_ANY,
1740 .help = "configure hardware debug control",
1741 .usage = "['all'|'none'|mask ...]",
1743 COMMAND_REGISTRATION_DONE
1746 static const struct command_registration esirisc_command_handlers[] = {
1749 .mode = COMMAND_ANY,
1750 .help = "eSi-RISC command group",
1752 .chain = esirisc_exec_command_handlers,
1754 COMMAND_REGISTRATION_DONE
1757 struct target_type esirisc_target = {
1760 .poll = esirisc_poll,
1761 .arch_state = esirisc_arch_state,
1763 .halt = esirisc_halt,
1764 .resume = esirisc_resume,
1765 .step = esirisc_step,
1767 .assert_reset = esirisc_assert_reset,
1768 .deassert_reset = esirisc_deassert_reset,
1770 .get_gdb_arch = esirisc_get_gdb_arch,
1771 .get_gdb_reg_list = esirisc_get_gdb_reg_list,
1773 .read_memory = esirisc_read_memory,
1774 .write_memory = esirisc_write_memory,
1775 .checksum_memory = esirisc_checksum_memory,
1777 .add_breakpoint = esirisc_add_breakpoint,
1778 .remove_breakpoint = esirisc_remove_breakpoint,
1779 .add_watchpoint = esirisc_add_watchpoint,
1780 .remove_watchpoint = esirisc_remove_watchpoint,
1782 .commands = esirisc_command_handlers,
1784 .target_create = esirisc_target_create,
1785 .init_target = esirisc_init_target,
1786 .examine = esirisc_examine,