git.sur5r.net Git - openocd/blob - src/target/etb.c

   1 /***************************************************************************
   2  *   Copyright (C) 2007 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "arm.h"
  25 #include "etm.h"
  26 #include "etb.h"
  27 #include "register.h"
  28
  29
  30 static char* etb_reg_list[] =
  31 {
  32         "ETB_identification",
  33         "ETB_ram_depth",
  34         "ETB_ram_width",
  35         "ETB_status",
  36         "ETB_ram_data",
  37         "ETB_ram_read_pointer",
  38         "ETB_ram_write_pointer",
  39         "ETB_trigger_counter",
  40         "ETB_control",
  41 };
  42
  43 static int etb_get_reg(struct reg *reg);
  44
  45 static int etb_set_instr(struct etb *etb, uint32_t new_instr)
  46 {
  47         struct jtag_tap *tap;
  48
  49         tap = etb->tap;
  50         if (tap == NULL)
  51                 return ERROR_FAIL;
  52
  53         if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr)
  54         {
  55                 struct scan_field field;
  56
  57                 field.num_bits = tap->ir_length;
  58                 void * t = calloc(DIV_ROUND_UP(field.num_bits, 8), 1);
  59                 field.out_value = t;
  60                 buf_set_u32(t, 0, field.num_bits, new_instr);
  61
  62                 field.in_value = NULL;
  63
  64                 jtag_add_ir_scan(tap, &field, TAP_IDLE);
  65
  66                 free(t);
  67         }
  68
  69         return ERROR_OK;
  70 }
  71
  72 static int etb_scann(struct etb *etb, uint32_t new_scan_chain)
  73 {
  74         if (etb->cur_scan_chain != new_scan_chain)
  75         {
  76                 struct scan_field field;
  77
  78                 field.num_bits = 5;
  79                 void * t = calloc(DIV_ROUND_UP(field.num_bits, 8), 1);
  80                 field.out_value = t;
  81                 buf_set_u32(t, 0, field.num_bits, new_scan_chain);
  82
  83                 field.in_value = NULL;
  84
  85                 /* select INTEST instruction */
  86                 etb_set_instr(etb, 0x2);
  87                 jtag_add_dr_scan(etb->tap, 1, &field, TAP_IDLE);
  88
  89                 etb->cur_scan_chain = new_scan_chain;
  90
  91                 free(t);
  92         }
  93
  94         return ERROR_OK;
  95 }
  96
  97 static int etb_read_reg_w_check(struct reg *, uint8_t *, uint8_t *);
  98 static int etb_set_reg_w_exec(struct reg *, uint8_t *);
  99
 100 static int etb_read_reg(struct reg *reg)
 101 {
 102         return etb_read_reg_w_check(reg, NULL, NULL);
 103 }
 104
 105 static int etb_get_reg(struct reg *reg)
 106 {
 107         int retval;
 108
 109         if ((retval = etb_read_reg(reg)) != ERROR_OK)
 110         {
 111                 LOG_ERROR("BUG: error scheduling ETB register read");
 112                 return retval;
 113         }
 114
 115         if ((retval = jtag_execute_queue()) != ERROR_OK)
 116         {
 117                 LOG_ERROR("ETB register read failed");
 118                 return retval;
 119         }
 120
 121         return ERROR_OK;
 122 }
 123
 124 static const struct reg_arch_type etb_reg_type = {
 125         .get = etb_get_reg,
 126         .set = etb_set_reg_w_exec,
 127 };
 128
 129 struct reg_cache* etb_build_reg_cache(struct etb *etb)
 130 {
 131         struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
 132         struct reg *reg_list = NULL;
 133         struct etb_reg *arch_info = NULL;
 134         int num_regs = 9;
 135         int i;
 136
 137         /* the actual registers are kept in two arrays */
 138         reg_list = calloc(num_regs, sizeof(struct reg));
 139         arch_info = calloc(num_regs, sizeof(struct etb_reg));
 140
 141         /* fill in values for the reg cache */
 142         reg_cache->name = "etb registers";
 143         reg_cache->next = NULL;
 144         reg_cache->reg_list = reg_list;
 145         reg_cache->num_regs = num_regs;
 146
 147         /* set up registers */
 148         for (i = 0; i < num_regs; i++)
 149         {
 150                 reg_list[i].name = etb_reg_list[i];
 151                 reg_list[i].size = 32;
 152                 reg_list[i].dirty = 0;
 153                 reg_list[i].valid = 0;
 154                 reg_list[i].value = calloc(1, 4);
 155                 reg_list[i].arch_info = &arch_info[i];
 156                 reg_list[i].type = &etb_reg_type;
 157                 reg_list[i].size = 32;
 158                 arch_info[i].addr = i;
 159                 arch_info[i].etb = etb;
 160         }
 161
 162         return reg_cache;
 163 }
 164
 165 static void etb_getbuf(jtag_callback_data_t arg)
 166 {
 167         uint8_t *in = (uint8_t *)arg;
 168
 169         *((uint32_t *)arg) = buf_get_u32(in, 0, 32);
 170 }
 171
 172
 173 static int etb_read_ram(struct etb *etb, uint32_t *data, int num_frames)
 174 {
 175         struct scan_field fields[3];
 176         int i;
 177
 178         etb_scann(etb, 0x0);
 179         etb_set_instr(etb, 0xc);
 180
 181         fields[0].num_bits = 32;
 182         fields[0].out_value = NULL;
 183         fields[0].in_value = NULL;
 184
 185         fields[1].num_bits = 7;
 186         uint8_t temp1;
 187         fields[1].out_value = &temp1;
 188         buf_set_u32(&temp1, 0, 7, 4);
 189         fields[1].in_value = NULL;
 190
 191         fields[2].num_bits = 1;
 192         uint8_t temp2;
 193         fields[2].out_value = &temp2;
 194         buf_set_u32(&temp2, 0, 1, 0);
 195         fields[2].in_value = NULL;
 196
 197         jtag_add_dr_scan(etb->tap, 3, fields, TAP_IDLE);
 198
 199         for (i = 0; i < num_frames; i++)
 200         {
 201                 /* ensure nR/W reamins set to read */
 202                 buf_set_u32(&temp2, 0, 1, 0);
 203
 204                 /* address remains set to 0x4 (RAM data) until we read the last frame */
 205                 if (i < num_frames - 1)
 206                         buf_set_u32(&temp1, 0, 7, 4);
 207                 else
 208                         buf_set_u32(&temp1, 0, 7, 0);
 209
 210                 fields[0].in_value = (uint8_t *)(data + i);
 211                 jtag_add_dr_scan(etb->tap, 3, fields, TAP_IDLE);
 212
 213                 jtag_add_callback(etb_getbuf, (jtag_callback_data_t)(data + i));
 214         }
 215
 216         jtag_execute_queue();
 217
 218         return ERROR_OK;
 219 }
 220
 221 static int etb_read_reg_w_check(struct reg *reg,
 222                 uint8_t* check_value, uint8_t* check_mask)
 223 {
 224         struct etb_reg *etb_reg = reg->arch_info;
 225         uint8_t reg_addr = etb_reg->addr & 0x7f;
 226         struct scan_field fields[3];
 227
 228         LOG_DEBUG("%i", (int)(etb_reg->addr));
 229
 230         etb_scann(etb_reg->etb, 0x0);
 231         etb_set_instr(etb_reg->etb, 0xc);
 232
 233         fields[0].num_bits = 32;
 234         fields[0].out_value = reg->value;
 235         fields[0].in_value = NULL;
 236         fields[0].check_value = NULL;
 237         fields[0].check_mask = NULL;
 238
 239         fields[1].num_bits = 7;
 240         uint8_t temp1;
 241         fields[1].out_value = &temp1;
 242         buf_set_u32(&temp1, 0, 7, reg_addr);
 243         fields[1].in_value = NULL;
 244         fields[1].check_value = NULL;
 245         fields[1].check_mask = NULL;
 246
 247         fields[2].num_bits = 1;
 248         uint8_t temp2;
 249         fields[2].out_value = &temp2;
 250         buf_set_u32(&temp2, 0, 1, 0);
 251         fields[2].in_value = NULL;
 252         fields[2].check_value = NULL;
 253         fields[2].check_mask = NULL;
 254
 255         jtag_add_dr_scan(etb_reg->etb->tap, 3, fields, TAP_IDLE);
 256
 257         /* read the identification register in the second run, to make sure we
 258          * don't read the ETB data register twice, skipping every second entry
 259          */
 260         buf_set_u32(&temp1, 0, 7, 0x0);
 261         fields[0].in_value = reg->value;
 262         fields[0].check_value = check_value;
 263         fields[0].check_mask = check_mask;
 264
 265         jtag_add_dr_scan_check(etb_reg->etb->tap, 3, fields, TAP_IDLE);
 266
 267         return ERROR_OK;
 268 }
 269
 270 static int etb_write_reg(struct reg *, uint32_t);
 271
 272 static int etb_set_reg(struct reg *reg, uint32_t value)
 273 {
 274         int retval;
 275
 276         if ((retval = etb_write_reg(reg, value)) != ERROR_OK)
 277         {
 278                 LOG_ERROR("BUG: error scheduling ETB register write");
 279                 return retval;
 280         }
 281
 282         buf_set_u32(reg->value, 0, reg->size, value);
 283         reg->valid = 1;
 284         reg->dirty = 0;
 285
 286         return ERROR_OK;
 287 }
 288
 289 static int etb_set_reg_w_exec(struct reg *reg, uint8_t *buf)
 290 {
 291         int retval;
 292
 293         etb_set_reg(reg, buf_get_u32(buf, 0, reg->size));
 294
 295         if ((retval = jtag_execute_queue()) != ERROR_OK)
 296         {
 297                 LOG_ERROR("ETB: register write failed");
 298                 return retval;
 299         }
 300         return ERROR_OK;
 301 }
 302
 303 static int etb_write_reg(struct reg *reg, uint32_t value)
 304 {
 305         struct etb_reg *etb_reg = reg->arch_info;
 306         uint8_t reg_addr = etb_reg->addr & 0x7f;
 307
 308         LOG_DEBUG("%i: 0x%8.8" PRIx32 "", (int)(etb_reg->addr), value);
 309
 310         etb_scann(etb_reg->etb, 0x0);
 311         etb_set_instr(etb_reg->etb, 0xc);
 312
 313         uint8_t temp0[4];
 314         buf_set_u32(&temp0, 0, 32, value);
 315
 316         uint8_t temp1;
 317         buf_set_u32(&temp1, 0, 7, reg_addr);
 318
 319         uint8_t temp2;
 320         buf_set_u32(&temp2, 0, 1, 1);
 321
 322         return ERROR_OK;
 323 }
 324
 325 COMMAND_HANDLER(handle_etb_config_command)
 326 {
 327         struct target *target;
 328         struct jtag_tap *tap;
 329         struct arm *arm;
 330
 331         if (CMD_ARGC != 2)
 332         {
 333                 return ERROR_COMMAND_SYNTAX_ERROR;
 334         }
 335
 336         target = get_target(CMD_ARGV[0]);
 337
 338         if (!target)
 339         {
 340                 LOG_ERROR("ETB: target '%s' not defined", CMD_ARGV[0]);
 341                 return ERROR_FAIL;
 342         }
 343
 344         arm = target_to_arm(target);
 345         if (!is_arm(arm))
 346         {
 347                 command_print(CMD_CTX, "ETB: '%s' isn't an ARM", CMD_ARGV[0]);
 348                 return ERROR_FAIL;
 349         }
 350
 351         tap = jtag_tap_by_string(CMD_ARGV[1]);
 352         if (tap == NULL)
 353         {
 354                 command_print(CMD_CTX, "ETB: TAP %s does not exist", CMD_ARGV[1]);
 355                 return ERROR_FAIL;
 356         }
 357
 358         if (arm->etm)
 359         {
 360                 struct etb *etb = malloc(sizeof(struct etb));
 361
 362                 arm->etm->capture_driver_priv = etb;
 363
 364                 etb->tap  = tap;
 365                 etb->cur_scan_chain = 0xffffffff;
 366                 etb->reg_cache = NULL;
 367                 etb->ram_width = 0;
 368                 etb->ram_depth = 0;
 369         }
 370         else
 371         {
 372                 LOG_ERROR("ETM: target has no ETM defined, ETB left unconfigured");
 373                 return ERROR_FAIL;
 374         }
 375
 376         return ERROR_OK;
 377 }
 378
 379 COMMAND_HANDLER(handle_etb_trigger_percent_command)
 380 {
 381         struct target *target;
 382         struct arm *arm;
 383         struct etm_context *etm;
 384         struct etb *etb;
 385
 386         target = get_current_target(CMD_CTX);
 387         arm = target_to_arm(target);
 388         if (!is_arm(arm))
 389         {
 390                 command_print(CMD_CTX, "ETB: current target isn't an ARM");
 391                 return ERROR_FAIL;
 392         }
 393
 394         etm = arm->etm;
 395         if (!etm) {
 396                 command_print(CMD_CTX, "ETB: target has no ETM configured");
 397                 return ERROR_FAIL;
 398         }
 399         if (etm->capture_driver != &etb_capture_driver) {
 400                 command_print(CMD_CTX, "ETB: target not using ETB");
 401                 return ERROR_FAIL;
 402         }
 403         etb = arm->etm->capture_driver_priv;
 404
 405         if (CMD_ARGC > 0) {
 406                 uint32_t new_value;
 407
 408                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], new_value);
 409                 if ((new_value < 2) || (new_value > 100))
 410                         command_print(CMD_CTX,
 411                                 "valid percentages are 2%% to 100%%");
 412                 else
 413                         etb->trigger_percent = (unsigned) new_value;
 414         }
 415
 416         command_print(CMD_CTX, "%d percent of tracebuffer fills after trigger",
 417                         etb->trigger_percent);
 418
 419         return ERROR_OK;
 420 }
 421
 422 static const struct command_registration etb_config_command_handlers[] = {
 423         {
 424                 /* NOTE:  with ADIv5, ETBs are accessed using DAP operations,
 425                  * possibly over SWD, not through separate TAPs...
 426                  */
 427                 .name = "config",
 428                 .handler = handle_etb_config_command,
 429                 .mode = COMMAND_CONFIG,
 430                 .help = "Associate ETB with target and JTAG TAP.",
 431                 .usage = "target tap",
 432         },
 433         {
 434                 .name = "trigger_percent",
 435                 .handler = handle_etb_trigger_percent_command,
 436                 .mode = COMMAND_EXEC,
 437                 .help = "Set percent of trace buffer to be filled "
 438                         "after the trigger occurs (2..100).",
 439                 .usage = "[percent]",
 440         },
 441         COMMAND_REGISTRATION_DONE
 442 };
 443 static const struct command_registration etb_command_handlers[] = {
 444         {
 445                 .name = "etb",
 446                 .mode = COMMAND_ANY,
 447                 .help = "Emebdded Trace Buffer command group",
 448                 .chain = etb_config_command_handlers,
 449         },
 450         COMMAND_REGISTRATION_DONE
 451 };
 452
 453 static int etb_init(struct etm_context *etm_ctx)
 454 {
 455         struct etb *etb = etm_ctx->capture_driver_priv;
 456
 457         etb->etm_ctx = etm_ctx;
 458
 459         /* identify ETB RAM depth and width */
 460         etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_DEPTH]);
 461         etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_WIDTH]);
 462         jtag_execute_queue();
 463
 464         etb->ram_depth = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_DEPTH].value, 0, 32);
 465         etb->ram_width = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WIDTH].value, 0, 32);
 466
 467         etb->trigger_percent = 50;
 468
 469         return ERROR_OK;
 470 }
 471
 472 static trace_status_t etb_status(struct etm_context *etm_ctx)
 473 {
 474         struct etb *etb = etm_ctx->capture_driver_priv;
 475         struct reg *control = &etb->reg_cache->reg_list[ETB_CTRL];
 476         struct reg *status = &etb->reg_cache->reg_list[ETB_STATUS];
 477         trace_status_t retval = 0;
 478         int etb_timeout = 100;
 479
 480         etb->etm_ctx = etm_ctx;
 481
 482         /* read control and status registers */
 483         etb_read_reg(control);
 484         etb_read_reg(status);
 485         jtag_execute_queue();
 486
 487         /* See if it's (still) active */
 488         retval = buf_get_u32(control->value, 0, 1) ? TRACE_RUNNING : TRACE_IDLE;
 489
 490         /* check Full bit to identify wraparound/overflow */
 491         if (buf_get_u32(status->value, 0, 1) == 1)
 492                 retval |= TRACE_OVERFLOWED;
 493
 494         /* check Triggered bit to identify trigger condition */
 495         if (buf_get_u32(status->value, 1, 1) == 1)
 496                 retval |= TRACE_TRIGGERED;
 497
 498         /* check AcqComp to see if trigger counter dropped to zero */
 499         if (buf_get_u32(status->value, 2, 1) == 1) {
 500                 /* wait for DFEmpty */
 501                 while (etb_timeout-- && buf_get_u32(status->value, 3, 1) == 0)
 502                         etb_get_reg(status);
 503
 504                 if (etb_timeout == 0)
 505                         LOG_ERROR("ETB:  DFEmpty won't go high, status 0x%02x",
 506                                 (unsigned) buf_get_u32(status->value, 0, 4));
 507
 508                 if (!(etm_ctx->capture_status & TRACE_TRIGGERED))
 509                         LOG_WARNING("ETB: trace complete without triggering?");
 510
 511                 retval |= TRACE_COMPLETED;
 512         }
 513
 514         /* NOTE: using a trigger is optional; and at least ETB11 has a mode
 515          * where it can ignore the trigger counter.
 516          */
 517
 518         /* update recorded state */
 519         etm_ctx->capture_status = retval;
 520
 521         return retval;
 522 }
 523
 524 static int etb_read_trace(struct etm_context *etm_ctx)
 525 {
 526         struct etb *etb = etm_ctx->capture_driver_priv;
 527         int first_frame = 0;
 528         int num_frames = etb->ram_depth;
 529         uint32_t *trace_data = NULL;
 530         int i, j;
 531
 532         etb_read_reg(&etb->reg_cache->reg_list[ETB_STATUS]);
 533         etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER]);
 534         jtag_execute_queue();
 535
 536         /* check if we overflowed, and adjust first frame of the trace accordingly
 537          * if we didn't overflow, read only up to the frame that would be written next,
 538          * i.e. don't read invalid entries
 539          */
 540         if (buf_get_u32(etb->reg_cache->reg_list[ETB_STATUS].value, 0, 1))
 541         {
 542                 first_frame = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32);
 543         }
 544         else
 545         {
 546                 num_frames = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32);
 547         }
 548
 549         etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_READ_POINTER], first_frame);
 550
 551         /* read data into temporary array for unpacking */
 552         trace_data = malloc(sizeof(uint32_t) * num_frames);
 553         etb_read_ram(etb, trace_data, num_frames);
 554
 555         if (etm_ctx->trace_depth > 0)
 556         {
 557                 free(etm_ctx->trace_data);
 558         }
 559
 560         if ((etm_ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
 561                 etm_ctx->trace_depth = num_frames * 3;
 562         else if ((etm_ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
 563                 etm_ctx->trace_depth = num_frames * 2;
 564         else
 565                 etm_ctx->trace_depth = num_frames;
 566
 567         etm_ctx->trace_data = malloc(sizeof(struct etmv1_trace_data) * etm_ctx->trace_depth);
 568
 569         for (i = 0, j = 0; i < num_frames; i++)
 570         {
 571                 if ((etm_ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
 572                 {
 573                         /* trace word j */
 574                         etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
 575                         etm_ctx->trace_data[j].packet = (trace_data[i] & 0x78) >> 3;
 576                         etm_ctx->trace_data[j].flags = 0;
 577                         if ((trace_data[i] & 0x80) >> 7)
 578                         {
 579                                 etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
 580                         }
 581                         if (etm_ctx->trace_data[j].pipestat == STAT_TR)
 582                         {
 583                                 etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
 584                                 etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
 585                         }
 586
 587                         /* trace word j + 1 */
 588                         etm_ctx->trace_data[j + 1].pipestat = (trace_data[i] & 0x100) >> 8;
 589                         etm_ctx->trace_data[j + 1].packet = (trace_data[i] & 0x7800) >> 11;
 590                         etm_ctx->trace_data[j + 1].flags = 0;
 591                         if ((trace_data[i] & 0x8000) >> 15)
 592                         {
 593                                 etm_ctx->trace_data[j + 1].flags |= ETMV1_TRACESYNC_CYCLE;
 594                         }
 595                         if (etm_ctx->trace_data[j + 1].pipestat == STAT_TR)
 596                         {
 597                                 etm_ctx->trace_data[j + 1].pipestat = etm_ctx->trace_data[j + 1].packet & 0x7;
 598                                 etm_ctx->trace_data[j + 1].flags |= ETMV1_TRIGGER_CYCLE;
 599                         }
 600
 601                         /* trace word j + 2 */
 602                         etm_ctx->trace_data[j + 2].pipestat = (trace_data[i] & 0x10000) >> 16;
 603                         etm_ctx->trace_data[j + 2].packet = (trace_data[i] & 0x780000) >> 19;
 604                         etm_ctx->trace_data[j + 2].flags = 0;
 605                         if ((trace_data[i] & 0x800000) >> 23)
 606                         {
 607                                 etm_ctx->trace_data[j + 2].flags |= ETMV1_TRACESYNC_CYCLE;
 608                         }
 609                         if (etm_ctx->trace_data[j + 2].pipestat == STAT_TR)
 610                         {
 611                                 etm_ctx->trace_data[j + 2].pipestat = etm_ctx->trace_data[j + 2].packet & 0x7;
 612                                 etm_ctx->trace_data[j + 2].flags |= ETMV1_TRIGGER_CYCLE;
 613                         }
 614
 615                         j += 3;
 616                 }
 617                 else if ((etm_ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
 618                 {
 619                         /* trace word j */
 620                         etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
 621                         etm_ctx->trace_data[j].packet = (trace_data[i] & 0x7f8) >> 3;
 622                         etm_ctx->trace_data[j].flags = 0;
 623                         if ((trace_data[i] & 0x800) >> 11)
 624                         {
 625                                 etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
 626                         }
 627                         if (etm_ctx->trace_data[j].pipestat == STAT_TR)
 628                         {
 629                                 etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
 630                                 etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
 631                         }
 632
 633                         /* trace word j + 1 */
 634                         etm_ctx->trace_data[j + 1].pipestat = (trace_data[i] & 0x7000) >> 12;
 635                         etm_ctx->trace_data[j + 1].packet = (trace_data[i] & 0x7f8000) >> 15;
 636                         etm_ctx->trace_data[j + 1].flags = 0;
 637                         if ((trace_data[i] & 0x800000) >> 23)
 638                         {
 639                                 etm_ctx->trace_data[j + 1].flags |= ETMV1_TRACESYNC_CYCLE;
 640                         }
 641                         if (etm_ctx->trace_data[j + 1].pipestat == STAT_TR)
 642                         {
 643                                 etm_ctx->trace_data[j + 1].pipestat = etm_ctx->trace_data[j + 1].packet & 0x7;
 644                                 etm_ctx->trace_data[j + 1].flags |= ETMV1_TRIGGER_CYCLE;
 645                         }
 646
 647                         j += 2;
 648                 }
 649                 else
 650                 {
 651                         /* trace word j */
 652                         etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
 653                         etm_ctx->trace_data[j].packet = (trace_data[i] & 0x7fff8) >> 3;
 654                         etm_ctx->trace_data[j].flags = 0;
 655                         if ((trace_data[i] & 0x80000) >> 19)
 656                         {
 657                                 etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
 658                         }
 659                         if (etm_ctx->trace_data[j].pipestat == STAT_TR)
 660                         {
 661                                 etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
 662                                 etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
 663                         }
 664
 665                         j += 1;
 666                 }
 667         }
 668
 669         free(trace_data);
 670
 671         return ERROR_OK;
 672 }
 673
 674 static int etb_start_capture(struct etm_context *etm_ctx)
 675 {
 676         struct etb *etb = etm_ctx->capture_driver_priv;
 677         uint32_t etb_ctrl_value = 0x1;
 678         uint32_t trigger_count;
 679
 680         if ((etm_ctx->control & ETM_PORT_MODE_MASK) == ETM_PORT_DEMUXED)
 681         {
 682                 if ((etm_ctx->control & ETM_PORT_WIDTH_MASK) != ETM_PORT_8BIT)
 683                 {
 684                         LOG_ERROR("ETB can't run in demultiplexed mode with a 4 or 16 bit port");
 685                         return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
 686                 }
 687                 etb_ctrl_value |= 0x2;
 688         }
 689
 690         if ((etm_ctx->control & ETM_PORT_MODE_MASK) == ETM_PORT_MUXED) {
 691                 LOG_ERROR("ETB: can't run in multiplexed mode");
 692                 return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
 693         }
 694
 695         trigger_count = (etb->ram_depth * etb->trigger_percent) / 100;
 696
 697         etb_write_reg(&etb->reg_cache->reg_list[ETB_TRIGGER_COUNTER], trigger_count);
 698         etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER], 0x0);
 699         etb_write_reg(&etb->reg_cache->reg_list[ETB_CTRL], etb_ctrl_value);
 700         jtag_execute_queue();
 701
 702         /* we're starting a new trace, initialize capture status */
 703         etm_ctx->capture_status = TRACE_RUNNING;
 704
 705         return ERROR_OK;
 706 }
 707
 708 static int etb_stop_capture(struct etm_context *etm_ctx)
 709 {
 710         struct etb *etb = etm_ctx->capture_driver_priv;
 711         struct reg *etb_ctrl_reg = &etb->reg_cache->reg_list[ETB_CTRL];
 712
 713         etb_write_reg(etb_ctrl_reg, 0x0);
 714         jtag_execute_queue();
 715
 716         /* trace stopped, just clear running flag, but preserve others */
 717         etm_ctx->capture_status &= ~TRACE_RUNNING;
 718
 719         return ERROR_OK;
 720 }
 721
 722 struct etm_capture_driver etb_capture_driver =
 723 {
 724         .name = "etb",
 725         .commands = etb_command_handlers,
 726         .init = etb_init,
 727         .status = etb_status,
 728         .start_capture = etb_start_capture,
 729         .stop_capture = etb_stop_capture,
 730         .read_trace = etb_read_trace,
 731 };