git.sur5r.net Git - openocd/blob - src/target/etb.c

   1 /***************************************************************************
   2  *   Copyright (C) 2007 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "arm.h"
  25 #include "etm.h"
  26 #include "etb.h"
  27 #include "register.h"
  28
  29
  30 static char* etb_reg_list[] =
  31 {
  32         "ETB_identification",
  33         "ETB_ram_depth",
  34         "ETB_ram_width",
  35         "ETB_status",
  36         "ETB_ram_data",
  37         "ETB_ram_read_pointer",
  38         "ETB_ram_write_pointer",
  39         "ETB_trigger_counter",
  40         "ETB_control",
  41 };
  42
  43 static int etb_get_reg(struct reg *reg);
  44
  45 static int etb_set_instr(struct etb *etb, uint32_t new_instr)
  46 {
  47         struct jtag_tap *tap;
  48
  49         tap = etb->tap;
  50         if (tap == NULL)
  51                 return ERROR_FAIL;
  52
  53         if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr)
  54         {
  55                 struct scan_field field;
  56
  57                 field.num_bits = tap->ir_length;
  58                 void * t = calloc(DIV_ROUND_UP(field.num_bits, 8), 1);
  59                 field.out_value = t;
  60                 buf_set_u32(t, 0, field.num_bits, new_instr);
  61
  62                 field.in_value = NULL;
  63
  64                 jtag_add_ir_scan(tap, &field, TAP_IDLE);
  65
  66                 free(t);
  67         }
  68
  69         return ERROR_OK;
  70 }
  71
  72 static int etb_scann(struct etb *etb, uint32_t new_scan_chain)
  73 {
  74         if (etb->cur_scan_chain != new_scan_chain)
  75         {
  76                 struct scan_field field;
  77
  78                 field.num_bits = 5;
  79                 void * t = calloc(DIV_ROUND_UP(field.num_bits, 8), 1);
  80                 field.out_value = t;
  81                 buf_set_u32(t, 0, field.num_bits, new_scan_chain);
  82
  83                 field.in_value = NULL;
  84
  85                 /* select INTEST instruction */
  86                 etb_set_instr(etb, 0x2);
  87                 jtag_add_dr_scan(etb->tap, 1, &field, TAP_IDLE);
  88
  89                 etb->cur_scan_chain = new_scan_chain;
  90
  91                 free(t);
  92         }
  93
  94         return ERROR_OK;
  95 }
  96
  97 static int etb_read_reg_w_check(struct reg *, uint8_t *, uint8_t *);
  98 static int etb_set_reg_w_exec(struct reg *, uint8_t *);
  99
 100 static int etb_read_reg(struct reg *reg)
 101 {
 102         return etb_read_reg_w_check(reg, NULL, NULL);
 103 }
 104
 105 static int etb_get_reg(struct reg *reg)
 106 {
 107         int retval;
 108
 109         if ((retval = etb_read_reg(reg)) != ERROR_OK)
 110         {
 111                 LOG_ERROR("BUG: error scheduling ETB register read");
 112                 return retval;
 113         }
 114
 115         if ((retval = jtag_execute_queue()) != ERROR_OK)
 116         {
 117                 LOG_ERROR("ETB register read failed");
 118                 return retval;
 119         }
 120
 121         return ERROR_OK;
 122 }
 123
 124 static const struct reg_arch_type etb_reg_type = {
 125         .get = etb_get_reg,
 126         .set = etb_set_reg_w_exec,
 127 };
 128
 129 struct reg_cache* etb_build_reg_cache(struct etb *etb)
 130 {
 131         struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
 132         struct reg *reg_list = NULL;
 133         struct etb_reg *arch_info = NULL;
 134         int num_regs = 9;
 135         int i;
 136
 137         /* the actual registers are kept in two arrays */
 138         reg_list = calloc(num_regs, sizeof(struct reg));
 139         arch_info = calloc(num_regs, sizeof(struct etb_reg));
 140
 141         /* fill in values for the reg cache */
 142         reg_cache->name = "etb registers";
 143         reg_cache->next = NULL;
 144         reg_cache->reg_list = reg_list;
 145         reg_cache->num_regs = num_regs;
 146
 147         /* set up registers */
 148         for (i = 0; i < num_regs; i++)
 149         {
 150                 reg_list[i].name = etb_reg_list[i];
 151                 reg_list[i].size = 32;
 152                 reg_list[i].dirty = 0;
 153                 reg_list[i].valid = 0;
 154                 reg_list[i].value = calloc(1, 4);
 155                 reg_list[i].arch_info = &arch_info[i];
 156                 reg_list[i].type = &etb_reg_type;
 157                 reg_list[i].size = 32;
 158                 arch_info[i].addr = i;
 159                 arch_info[i].etb = etb;
 160         }
 161
 162         return reg_cache;
 163 }
 164
 165 static void etb_getbuf(jtag_callback_data_t arg)
 166 {
 167         uint8_t *in = (uint8_t *)arg;
 168
 169         *((uint32_t *)arg) = buf_get_u32(in, 0, 32);
 170 }
 171
 172
 173 static int etb_read_ram(struct etb *etb, uint32_t *data, int num_frames)
 174 {
 175         struct scan_field fields[3];
 176         int i;
 177
 178         etb_scann(etb, 0x0);
 179         etb_set_instr(etb, 0xc);
 180
 181         fields[0].num_bits = 32;
 182         fields[0].out_value = NULL;
 183         fields[0].in_value = NULL;
 184
 185         fields[1].num_bits = 7;
 186         uint8_t temp1;
 187         fields[1].out_value = &temp1;
 188         buf_set_u32(&temp1, 0, 7, 4);
 189         fields[1].in_value = NULL;
 190
 191         fields[2].num_bits = 1;
 192         uint8_t temp2;
 193         fields[2].out_value = &temp2;
 194         buf_set_u32(&temp2, 0, 1, 0);
 195         fields[2].in_value = NULL;
 196
 197         jtag_add_dr_scan(etb->tap, 3, fields, TAP_IDLE);
 198
 199         for (i = 0; i < num_frames; i++)
 200         {
 201                 /* ensure nR/W reamins set to read */
 202                 buf_set_u32(&temp2, 0, 1, 0);
 203
 204                 /* address remains set to 0x4 (RAM data) until we read the last frame */
 205                 if (i < num_frames - 1)
 206                         buf_set_u32(&temp1, 0, 7, 4);
 207                 else
 208                         buf_set_u32(&temp1, 0, 7, 0);
 209
 210                 fields[0].in_value = (uint8_t *)(data + i);
 211                 jtag_add_dr_scan(etb->tap, 3, fields, TAP_IDLE);
 212
 213                 jtag_add_callback(etb_getbuf, (jtag_callback_data_t)(data + i));
 214         }
 215
 216         jtag_execute_queue();
 217
 218         return ERROR_OK;
 219 }
 220
 221 static int etb_read_reg_w_check(struct reg *reg,
 222                 uint8_t* check_value, uint8_t* check_mask)
 223 {
 224         struct etb_reg *etb_reg = reg->arch_info;
 225         uint8_t reg_addr = etb_reg->addr & 0x7f;
 226         struct scan_field fields[3];
 227
 228         LOG_DEBUG("%i", (int)(etb_reg->addr));
 229
 230         etb_scann(etb_reg->etb, 0x0);
 231         etb_set_instr(etb_reg->etb, 0xc);
 232
 233         fields[0].num_bits = 32;
 234         fields[0].out_value = reg->value;
 235         fields[0].in_value = NULL;
 236         fields[0].check_value = NULL;
 237         fields[0].check_mask = NULL;
 238
 239         fields[1].num_bits = 7;
 240         uint8_t temp1;
 241         fields[1].out_value = &temp1;
 242         buf_set_u32(&temp1, 0, 7, reg_addr);
 243         fields[1].in_value = NULL;
 244         fields[1].check_value = NULL;
 245         fields[1].check_mask = NULL;
 246
 247         fields[2].num_bits = 1;
 248         uint8_t temp2;
 249         fields[2].out_value = &temp2;
 250         buf_set_u32(&temp2, 0, 1, 0);
 251         fields[2].in_value = NULL;
 252         fields[2].check_value = NULL;
 253         fields[2].check_mask = NULL;
 254
 255         jtag_add_dr_scan(etb_reg->etb->tap, 3, fields, TAP_IDLE);
 256
 257         /* read the identification register in the second run, to make sure we
 258          * don't read the ETB data register twice, skipping every second entry
 259          */
 260         buf_set_u32(&temp1, 0, 7, 0x0);
 261         fields[0].in_value = reg->value;
 262         fields[0].check_value = check_value;
 263         fields[0].check_mask = check_mask;
 264
 265         jtag_add_dr_scan_check(etb_reg->etb->tap, 3, fields, TAP_IDLE);
 266
 267         return ERROR_OK;
 268 }
 269
 270 static int etb_write_reg(struct reg *, uint32_t);
 271
 272 static int etb_set_reg(struct reg *reg, uint32_t value)
 273 {
 274         int retval;
 275
 276         if ((retval = etb_write_reg(reg, value)) != ERROR_OK)
 277         {
 278                 LOG_ERROR("BUG: error scheduling ETB register write");
 279                 return retval;
 280         }
 281
 282         buf_set_u32(reg->value, 0, reg->size, value);
 283         reg->valid = 1;
 284         reg->dirty = 0;
 285
 286         return ERROR_OK;
 287 }
 288
 289 static int etb_set_reg_w_exec(struct reg *reg, uint8_t *buf)
 290 {
 291         int retval;
 292
 293         etb_set_reg(reg, buf_get_u32(buf, 0, reg->size));
 294
 295         if ((retval = jtag_execute_queue()) != ERROR_OK)
 296         {
 297                 LOG_ERROR("ETB: register write failed");
 298                 return retval;
 299         }
 300         return ERROR_OK;
 301 }
 302
 303 static int etb_write_reg(struct reg *reg, uint32_t value)
 304 {
 305         struct etb_reg *etb_reg = reg->arch_info;
 306         uint8_t reg_addr = etb_reg->addr & 0x7f;
 307         struct scan_field fields[3];
 308
 309         LOG_DEBUG("%i: 0x%8.8" PRIx32 "", (int)(etb_reg->addr), value);
 310
 311         etb_scann(etb_reg->etb, 0x0);
 312         etb_set_instr(etb_reg->etb, 0xc);
 313
 314         fields[0].num_bits = 32;
 315         uint8_t temp0[4];
 316         fields[0].out_value = temp0;
 317         buf_set_u32(&temp0, 0, 32, value);
 318         fields[0].in_value = NULL;
 319
 320         fields[1].num_bits = 7;
 321         uint8_t temp1;
 322         fields[1].out_value = &temp1;
 323         buf_set_u32(&temp1, 0, 7, reg_addr);
 324         fields[1].in_value = NULL;
 325
 326         fields[2].num_bits = 1;
 327         uint8_t temp2;
 328         fields[2].out_value = &temp2;
 329         buf_set_u32(&temp2, 0, 1, 1);
 330         fields[2].in_value = NULL;
 331
 332         jtag_add_dr_scan(etb_reg->etb->tap, 3, fields, TAP_IDLE);
 333
 334         return ERROR_OK;
 335 }
 336
 337 COMMAND_HANDLER(handle_etb_config_command)
 338 {
 339         struct target *target;
 340         struct jtag_tap *tap;
 341         struct arm *arm;
 342
 343         if (CMD_ARGC != 2)
 344         {
 345                 return ERROR_COMMAND_SYNTAX_ERROR;
 346         }
 347
 348         target = get_target(CMD_ARGV[0]);
 349
 350         if (!target)
 351         {
 352                 LOG_ERROR("ETB: target '%s' not defined", CMD_ARGV[0]);
 353                 return ERROR_FAIL;
 354         }
 355
 356         arm = target_to_arm(target);
 357         if (!is_arm(arm))
 358         {
 359                 command_print(CMD_CTX, "ETB: '%s' isn't an ARM", CMD_ARGV[0]);
 360                 return ERROR_FAIL;
 361         }
 362
 363         tap = jtag_tap_by_string(CMD_ARGV[1]);
 364         if (tap == NULL)
 365         {
 366                 command_print(CMD_CTX, "ETB: TAP %s does not exist", CMD_ARGV[1]);
 367                 return ERROR_FAIL;
 368         }
 369
 370         if (arm->etm)
 371         {
 372                 struct etb *etb = malloc(sizeof(struct etb));
 373
 374                 arm->etm->capture_driver_priv = etb;
 375
 376                 etb->tap  = tap;
 377                 etb->cur_scan_chain = 0xffffffff;
 378                 etb->reg_cache = NULL;
 379                 etb->ram_width = 0;
 380                 etb->ram_depth = 0;
 381         }
 382         else
 383         {
 384                 LOG_ERROR("ETM: target has no ETM defined, ETB left unconfigured");
 385                 return ERROR_FAIL;
 386         }
 387
 388         return ERROR_OK;
 389 }
 390
 391 COMMAND_HANDLER(handle_etb_trigger_percent_command)
 392 {
 393         struct target *target;
 394         struct arm *arm;
 395         struct etm_context *etm;
 396         struct etb *etb;
 397
 398         target = get_current_target(CMD_CTX);
 399         arm = target_to_arm(target);
 400         if (!is_arm(arm))
 401         {
 402                 command_print(CMD_CTX, "ETB: current target isn't an ARM");
 403                 return ERROR_FAIL;
 404         }
 405
 406         etm = arm->etm;
 407         if (!etm) {
 408                 command_print(CMD_CTX, "ETB: target has no ETM configured");
 409                 return ERROR_FAIL;
 410         }
 411         if (etm->capture_driver != &etb_capture_driver) {
 412                 command_print(CMD_CTX, "ETB: target not using ETB");
 413                 return ERROR_FAIL;
 414         }
 415         etb = arm->etm->capture_driver_priv;
 416
 417         if (CMD_ARGC > 0) {
 418                 uint32_t new_value;
 419
 420                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], new_value);
 421                 if ((new_value < 2) || (new_value > 100))
 422                         command_print(CMD_CTX,
 423                                 "valid percentages are 2%% to 100%%");
 424                 else
 425                         etb->trigger_percent = (unsigned) new_value;
 426         }
 427
 428         command_print(CMD_CTX, "%d percent of tracebuffer fills after trigger",
 429                         etb->trigger_percent);
 430
 431         return ERROR_OK;
 432 }
 433
 434 static const struct command_registration etb_config_command_handlers[] = {
 435         {
 436                 /* NOTE:  with ADIv5, ETBs are accessed using DAP operations,
 437                  * possibly over SWD, not through separate TAPs...
 438                  */
 439                 .name = "config",
 440                 .handler = handle_etb_config_command,
 441                 .mode = COMMAND_CONFIG,
 442                 .help = "Associate ETB with target and JTAG TAP.",
 443                 .usage = "target tap",
 444         },
 445         {
 446                 .name = "trigger_percent",
 447                 .handler = handle_etb_trigger_percent_command,
 448                 .mode = COMMAND_EXEC,
 449                 .help = "Set percent of trace buffer to be filled "
 450                         "after the trigger occurs (2..100).",
 451                 .usage = "[percent]",
 452         },
 453         COMMAND_REGISTRATION_DONE
 454 };
 455 static const struct command_registration etb_command_handlers[] = {
 456         {
 457                 .name = "etb",
 458                 .mode = COMMAND_ANY,
 459                 .help = "Emebdded Trace Buffer command group",
 460                 .chain = etb_config_command_handlers,
 461         },
 462         COMMAND_REGISTRATION_DONE
 463 };
 464
 465 static int etb_init(struct etm_context *etm_ctx)
 466 {
 467         struct etb *etb = etm_ctx->capture_driver_priv;
 468
 469         etb->etm_ctx = etm_ctx;
 470
 471         /* identify ETB RAM depth and width */
 472         etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_DEPTH]);
 473         etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_WIDTH]);
 474         jtag_execute_queue();
 475
 476         etb->ram_depth = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_DEPTH].value, 0, 32);
 477         etb->ram_width = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WIDTH].value, 0, 32);
 478
 479         etb->trigger_percent = 50;
 480
 481         return ERROR_OK;
 482 }
 483
 484 static trace_status_t etb_status(struct etm_context *etm_ctx)
 485 {
 486         struct etb *etb = etm_ctx->capture_driver_priv;
 487         struct reg *control = &etb->reg_cache->reg_list[ETB_CTRL];
 488         struct reg *status = &etb->reg_cache->reg_list[ETB_STATUS];
 489         trace_status_t retval = 0;
 490         int etb_timeout = 100;
 491
 492         etb->etm_ctx = etm_ctx;
 493
 494         /* read control and status registers */
 495         etb_read_reg(control);
 496         etb_read_reg(status);
 497         jtag_execute_queue();
 498
 499         /* See if it's (still) active */
 500         retval = buf_get_u32(control->value, 0, 1) ? TRACE_RUNNING : TRACE_IDLE;
 501
 502         /* check Full bit to identify wraparound/overflow */
 503         if (buf_get_u32(status->value, 0, 1) == 1)
 504                 retval |= TRACE_OVERFLOWED;
 505
 506         /* check Triggered bit to identify trigger condition */
 507         if (buf_get_u32(status->value, 1, 1) == 1)
 508                 retval |= TRACE_TRIGGERED;
 509
 510         /* check AcqComp to see if trigger counter dropped to zero */
 511         if (buf_get_u32(status->value, 2, 1) == 1) {
 512                 /* wait for DFEmpty */
 513                 while (etb_timeout-- && buf_get_u32(status->value, 3, 1) == 0)
 514                         etb_get_reg(status);
 515
 516                 if (etb_timeout == 0)
 517                         LOG_ERROR("ETB:  DFEmpty won't go high, status 0x%02x",
 518                                 (unsigned) buf_get_u32(status->value, 0, 4));
 519
 520                 if (!(etm_ctx->capture_status & TRACE_TRIGGERED))
 521                         LOG_WARNING("ETB: trace complete without triggering?");
 522
 523                 retval |= TRACE_COMPLETED;
 524         }
 525
 526         /* NOTE: using a trigger is optional; and at least ETB11 has a mode
 527          * where it can ignore the trigger counter.
 528          */
 529
 530         /* update recorded state */
 531         etm_ctx->capture_status = retval;
 532
 533         return retval;
 534 }
 535
 536 static int etb_read_trace(struct etm_context *etm_ctx)
 537 {
 538         struct etb *etb = etm_ctx->capture_driver_priv;
 539         int first_frame = 0;
 540         int num_frames = etb->ram_depth;
 541         uint32_t *trace_data = NULL;
 542         int i, j;
 543
 544         etb_read_reg(&etb->reg_cache->reg_list[ETB_STATUS]);
 545         etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER]);
 546         jtag_execute_queue();
 547
 548         /* check if we overflowed, and adjust first frame of the trace accordingly
 549          * if we didn't overflow, read only up to the frame that would be written next,
 550          * i.e. don't read invalid entries
 551          */
 552         if (buf_get_u32(etb->reg_cache->reg_list[ETB_STATUS].value, 0, 1))
 553         {
 554                 first_frame = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32);
 555         }
 556         else
 557         {
 558                 num_frames = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32);
 559         }
 560
 561         etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_READ_POINTER], first_frame);
 562
 563         /* read data into temporary array for unpacking */
 564         trace_data = malloc(sizeof(uint32_t) * num_frames);
 565         etb_read_ram(etb, trace_data, num_frames);
 566
 567         if (etm_ctx->trace_depth > 0)
 568         {
 569                 free(etm_ctx->trace_data);
 570         }
 571
 572         if ((etm_ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
 573                 etm_ctx->trace_depth = num_frames * 3;
 574         else if ((etm_ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
 575                 etm_ctx->trace_depth = num_frames * 2;
 576         else
 577                 etm_ctx->trace_depth = num_frames;
 578
 579         etm_ctx->trace_data = malloc(sizeof(struct etmv1_trace_data) * etm_ctx->trace_depth);
 580
 581         for (i = 0, j = 0; i < num_frames; i++)
 582         {
 583                 if ((etm_ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
 584                 {
 585                         /* trace word j */
 586                         etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
 587                         etm_ctx->trace_data[j].packet = (trace_data[i] & 0x78) >> 3;
 588                         etm_ctx->trace_data[j].flags = 0;
 589                         if ((trace_data[i] & 0x80) >> 7)
 590                         {
 591                                 etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
 592                         }
 593                         if (etm_ctx->trace_data[j].pipestat == STAT_TR)
 594                         {
 595                                 etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
 596                                 etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
 597                         }
 598
 599                         /* trace word j + 1 */
 600                         etm_ctx->trace_data[j + 1].pipestat = (trace_data[i] & 0x100) >> 8;
 601                         etm_ctx->trace_data[j + 1].packet = (trace_data[i] & 0x7800) >> 11;
 602                         etm_ctx->trace_data[j + 1].flags = 0;
 603                         if ((trace_data[i] & 0x8000) >> 15)
 604                         {
 605                                 etm_ctx->trace_data[j + 1].flags |= ETMV1_TRACESYNC_CYCLE;
 606                         }
 607                         if (etm_ctx->trace_data[j + 1].pipestat == STAT_TR)
 608                         {
 609                                 etm_ctx->trace_data[j + 1].pipestat = etm_ctx->trace_data[j + 1].packet & 0x7;
 610                                 etm_ctx->trace_data[j + 1].flags |= ETMV1_TRIGGER_CYCLE;
 611                         }
 612
 613                         /* trace word j + 2 */
 614                         etm_ctx->trace_data[j + 2].pipestat = (trace_data[i] & 0x10000) >> 16;
 615                         etm_ctx->trace_data[j + 2].packet = (trace_data[i] & 0x780000) >> 19;
 616                         etm_ctx->trace_data[j + 2].flags = 0;
 617                         if ((trace_data[i] & 0x800000) >> 23)
 618                         {
 619                                 etm_ctx->trace_data[j + 2].flags |= ETMV1_TRACESYNC_CYCLE;
 620                         }
 621                         if (etm_ctx->trace_data[j + 2].pipestat == STAT_TR)
 622                         {
 623                                 etm_ctx->trace_data[j + 2].pipestat = etm_ctx->trace_data[j + 2].packet & 0x7;
 624                                 etm_ctx->trace_data[j + 2].flags |= ETMV1_TRIGGER_CYCLE;
 625                         }
 626
 627                         j += 3;
 628                 }
 629                 else if ((etm_ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
 630                 {
 631                         /* trace word j */
 632                         etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
 633                         etm_ctx->trace_data[j].packet = (trace_data[i] & 0x7f8) >> 3;
 634                         etm_ctx->trace_data[j].flags = 0;
 635                         if ((trace_data[i] & 0x800) >> 11)
 636                         {
 637                                 etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
 638                         }
 639                         if (etm_ctx->trace_data[j].pipestat == STAT_TR)
 640                         {
 641                                 etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
 642                                 etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
 643                         }
 644
 645                         /* trace word j + 1 */
 646                         etm_ctx->trace_data[j + 1].pipestat = (trace_data[i] & 0x7000) >> 12;
 647                         etm_ctx->trace_data[j + 1].packet = (trace_data[i] & 0x7f8000) >> 15;
 648                         etm_ctx->trace_data[j + 1].flags = 0;
 649                         if ((trace_data[i] & 0x800000) >> 23)
 650                         {
 651                                 etm_ctx->trace_data[j + 1].flags |= ETMV1_TRACESYNC_CYCLE;
 652                         }
 653                         if (etm_ctx->trace_data[j + 1].pipestat == STAT_TR)
 654                         {
 655                                 etm_ctx->trace_data[j + 1].pipestat = etm_ctx->trace_data[j + 1].packet & 0x7;
 656                                 etm_ctx->trace_data[j + 1].flags |= ETMV1_TRIGGER_CYCLE;
 657                         }
 658
 659                         j += 2;
 660                 }
 661                 else
 662                 {
 663                         /* trace word j */
 664                         etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
 665                         etm_ctx->trace_data[j].packet = (trace_data[i] & 0x7fff8) >> 3;
 666                         etm_ctx->trace_data[j].flags = 0;
 667                         if ((trace_data[i] & 0x80000) >> 19)
 668                         {
 669                                 etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
 670                         }
 671                         if (etm_ctx->trace_data[j].pipestat == STAT_TR)
 672                         {
 673                                 etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
 674                                 etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
 675                         }
 676
 677                         j += 1;
 678                 }
 679         }
 680
 681         free(trace_data);
 682
 683         return ERROR_OK;
 684 }
 685
 686 static int etb_start_capture(struct etm_context *etm_ctx)
 687 {
 688         struct etb *etb = etm_ctx->capture_driver_priv;
 689         uint32_t etb_ctrl_value = 0x1;
 690         uint32_t trigger_count;
 691
 692         if ((etm_ctx->control & ETM_PORT_MODE_MASK) == ETM_PORT_DEMUXED)
 693         {
 694                 if ((etm_ctx->control & ETM_PORT_WIDTH_MASK) != ETM_PORT_8BIT)
 695                 {
 696                         LOG_ERROR("ETB can't run in demultiplexed mode with a 4 or 16 bit port");
 697                         return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
 698                 }
 699                 etb_ctrl_value |= 0x2;
 700         }
 701
 702         if ((etm_ctx->control & ETM_PORT_MODE_MASK) == ETM_PORT_MUXED) {
 703                 LOG_ERROR("ETB: can't run in multiplexed mode");
 704                 return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
 705         }
 706
 707         trigger_count = (etb->ram_depth * etb->trigger_percent) / 100;
 708
 709         etb_write_reg(&etb->reg_cache->reg_list[ETB_TRIGGER_COUNTER], trigger_count);
 710         etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER], 0x0);
 711         etb_write_reg(&etb->reg_cache->reg_list[ETB_CTRL], etb_ctrl_value);
 712         jtag_execute_queue();
 713
 714         /* we're starting a new trace, initialize capture status */
 715         etm_ctx->capture_status = TRACE_RUNNING;
 716
 717         return ERROR_OK;
 718 }
 719
 720 static int etb_stop_capture(struct etm_context *etm_ctx)
 721 {
 722         struct etb *etb = etm_ctx->capture_driver_priv;
 723         struct reg *etb_ctrl_reg = &etb->reg_cache->reg_list[ETB_CTRL];
 724
 725         etb_write_reg(etb_ctrl_reg, 0x0);
 726         jtag_execute_queue();
 727
 728         /* trace stopped, just clear running flag, but preserve others */
 729         etm_ctx->capture_status &= ~TRACE_RUNNING;
 730
 731         return ERROR_OK;
 732 }
 733
 734 struct etm_capture_driver etb_capture_driver =
 735 {
 736         .name = "etb",
 737         .commands = etb_command_handlers,
 738         .init = etb_init,
 739         .status = etb_status,
 740         .start_capture = etb_start_capture,
 741         .stop_capture = etb_stop_capture,
 742         .read_trace = etb_read_trace,
 743 };