git.sur5r.net Git - openocd/blob - src/target/etm.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "etm.h"
  25 #include "etb.h"
  26 #include "image.h"
  27 #include "arm7_9_common.h"
  28 #include "arm_disassembler.h"
  29
  30
  31 /*
  32  * ARM "Embedded Trace Macrocell" (ETM) support -- direct JTAG access.
  33  *
  34  * ETM modules collect instruction and/or data trace information, compress
  35  * it, and transfer it to a debugging host through either a (buffered) trace
  36  * port (often a 38-pin Mictor connector) or an Embedded Trace Buffer (ETB).
  37  *
  38  * There are several generations of these modules.  Original versions have
  39  * JTAG access through a dedicated scan chain.  Recent versions have added
  40  * access via coprocessor instructions, memory addressing, and the ARM Debug
  41  * Interface v5 (ADIv5); and phased out direct JTAG access.
  42  *
  43  * This code supports up to the ETMv1.3 architecture, as seen in ETM9 and
  44  * most common ARM9 systems.  Note: "CoreSight ETM9" implements ETMv3.2,
  45  * implying non-JTAG connectivity options.
  46  *
  47  * Relevant documentation includes:
  48  *  ARM DDI 0157G ... ETM9 (r2p2) Technical Reference Manual
  49  *  ARM DDI 0315B ... CoreSight ETM9 (r0p1) Technical Reference Manual
  50  *  ARM IHI 0014O ... Embedded Trace Macrocell, Architecture Specification
  51  */
  52
  53 #define ARRAY_SIZE(x)   ((int)(sizeof(x)/sizeof((x)[0])))
  54
  55 enum {
  56         RO,                             /* read/only */
  57         WO,                             /* write/only */
  58         RW,                             /* read/write */
  59 };
  60
  61 struct etm_reg_info {
  62         uint8_t         addr;
  63         uint8_t         size;           /* low-N of 32 bits */
  64         uint8_t         mode;           /* RO, WO, RW */
  65         uint8_t         bcd_vers;       /* 1.0, 2.0, etc */
  66         char            *name;
  67 };
  68
  69 /*
  70  * Registers 0..0x7f are JTAG-addressable using scanchain 6.
  71  * (Or on some processors, through coprocessor operations.)
  72  * Newer versions of ETM make some W/O registers R/W, and
  73  * provide definitions for some previously-unused bits.
  74  */
  75
  76 /* basic registers that are always there given the right ETM version */
  77 static const struct etm_reg_info etm_core[] = {
  78         /* NOTE: we "know" ETM_CONFIG is listed first */
  79         { ETM_CONFIG, 32, RO, 0x10, "ETM_config", },
  80
  81         /* ETM Trace Registers */
  82         { ETM_CTRL, 32, RW, 0x10, "ETM_ctrl", },
  83         { ETM_TRIG_EVENT, 17, WO, 0x10, "ETM_trig_event", },
  84         { ETM_ASIC_CTRL,  8, WO, 0x10, "ETM_asic_ctrl", },
  85         { ETM_STATUS,  3, RO, 0x11, "ETM_status", },
  86         { ETM_SYS_CONFIG,  9, RO, 0x12, "ETM_sys_config", },
  87
  88         /* TraceEnable configuration */
  89         { ETM_TRACE_RESOURCE_CTRL, 32, WO, 0x12, "ETM_trace_resource_ctrl", },
  90         { ETM_TRACE_EN_CTRL2, 16, WO, 0x12, "ETM_trace_en_ctrl2", },
  91         { ETM_TRACE_EN_EVENT, 17, WO, 0x10, "ETM_trace_en_event", },
  92         { ETM_TRACE_EN_CTRL1, 26, WO, 0x10, "ETM_trace_en_ctrl1", },
  93
  94         /* ViewData configuration (data trace) */
  95         { ETM_VIEWDATA_EVENT, 17, WO, 0x10, "ETM_viewdata_event", },
  96         { ETM_VIEWDATA_CTRL1, 32, WO, 0x10, "ETM_viewdata_ctrl1", },
  97         { ETM_VIEWDATA_CTRL2, 32, WO, 0x10, "ETM_viewdata_ctrl2", },
  98         { ETM_VIEWDATA_CTRL3, 17, WO, 0x10, "ETM_viewdata_ctrl3", },
  99
 100         /* REVISIT exclude VIEWDATA_CTRL2 when it's not there */
 101
 102         { 0x78, 12, WO, 0x20, "ETM_sync_freq", },
 103         { 0x79, 32, RO, 0x20, "ETM_id", },
 104 };
 105
 106 static const struct etm_reg_info etm_fifofull[] = {
 107         /* FIFOFULL configuration */
 108         { ETM_FIFOFULL_REGION, 25, WO, 0x10, "ETM_fifofull_region", },
 109         { ETM_FIFOFULL_LEVEL,  8, WO, 0x10, "ETM_fifofull_level", },
 110 };
 111
 112 static const struct etm_reg_info etm_addr_comp[] = {
 113         /* Address comparator register pairs */
 114 #define ADDR_COMPARATOR(i) \
 115                 { ETM_ADDR_COMPARATOR_VALUE + (i) - 1, 32, WO, 0x10, \
 116                                 "ETM_addr_" #i "_comparator_value", }, \
 117                 { ETM_ADDR_ACCESS_TYPE + (i) - 1,  7, WO, 0x10, \
 118                                 "ETM_addr_" #i "_access_type", }
 119         ADDR_COMPARATOR(1),
 120         ADDR_COMPARATOR(2),
 121         ADDR_COMPARATOR(3),
 122         ADDR_COMPARATOR(4),
 123         ADDR_COMPARATOR(5),
 124         ADDR_COMPARATOR(6),
 125         ADDR_COMPARATOR(7),
 126         ADDR_COMPARATOR(8),
 127
 128         ADDR_COMPARATOR(9),
 129         ADDR_COMPARATOR(10),
 130         ADDR_COMPARATOR(11),
 131         ADDR_COMPARATOR(12),
 132         ADDR_COMPARATOR(13),
 133         ADDR_COMPARATOR(14),
 134         ADDR_COMPARATOR(15),
 135         ADDR_COMPARATOR(16),
 136 #undef ADDR_COMPARATOR
 137 };
 138
 139 static const struct etm_reg_info etm_data_comp[] = {
 140         /* Data Value Comparators (NOTE: odd addresses are reserved) */
 141 #define DATA_COMPARATOR(i) \
 142                 { ETM_DATA_COMPARATOR_VALUE + 2*(i) - 1, 32, WO, 0x10, \
 143                                 "ETM_data_" #i "_comparator_value", }, \
 144                 { ETM_DATA_COMPARATOR_MASK + 2*(i) - 1, 32, WO, 0x10, \
 145                                 "ETM_data_" #i "_comparator_mask", }
 146         DATA_COMPARATOR(1),
 147         DATA_COMPARATOR(2),
 148         DATA_COMPARATOR(3),
 149         DATA_COMPARATOR(4),
 150         DATA_COMPARATOR(5),
 151         DATA_COMPARATOR(6),
 152         DATA_COMPARATOR(7),
 153         DATA_COMPARATOR(8),
 154 #undef DATA_COMPARATOR
 155 };
 156
 157 static const struct etm_reg_info etm_counters[] = {
 158 #define ETM_COUNTER(i) \
 159                 { ETM_COUNTER_RELOAD_VALUE + (i) - 1, 16, WO, 0x10, \
 160                                 "ETM_counter_" #i "_reload_value", }, \
 161                 { ETM_COUNTER_ENABLE + (i) - 1, 18, WO, 0x10, \
 162                                 "ETM_counter_" #i "_enable", }, \
 163                 { ETM_COUNTER_RELOAD_EVENT + (i) - 1, 17, WO, 0x10, \
 164                                 "ETM_counter_" #i "_reload_event", }, \
 165                 { ETM_COUNTER_VALUE + (i) - 1, 16, RO, 0x10, \
 166                                 "ETM_counter_" #i "_value", }
 167         ETM_COUNTER(1),
 168         ETM_COUNTER(2),
 169         ETM_COUNTER(3),
 170         ETM_COUNTER(4),
 171 #undef ETM_COUNTER
 172 };
 173
 174 static const struct etm_reg_info etm_sequencer[] = {
 175 #define ETM_SEQ(i) \
 176                 { ETM_SEQUENCER_EVENT + (i), 17, WO, 0x10, \
 177                                 "ETM_sequencer_event" #i, }
 178         ETM_SEQ(0),                             /* 1->2 */
 179         ETM_SEQ(1),                             /* 2->1 */
 180         ETM_SEQ(2),                             /* 2->3 */
 181         ETM_SEQ(3),                             /* 3->1 */
 182         ETM_SEQ(4),                             /* 3->2 */
 183         ETM_SEQ(5),                             /* 1->3 */
 184 #undef ETM_SEQ
 185         /* 0x66 reserved */
 186         { ETM_SEQUENCER_STATE,  2, RO, 0x10, "ETM_sequencer_state", },
 187 };
 188
 189 static const struct etm_reg_info etm_outputs[] = {
 190 #define ETM_OUTPUT(i) \
 191                 { ETM_EXTERNAL_OUTPUT + (i) - 1, 17, WO, 0x10, \
 192                                 "ETM_external_output" #i, }
 193
 194         ETM_OUTPUT(1),
 195         ETM_OUTPUT(2),
 196         ETM_OUTPUT(3),
 197         ETM_OUTPUT(4),
 198 #undef ETM_OUTPUT
 199 };
 200
 201 #if 0
 202         /* registers from 0x6c..0x7f were added after ETMv1.3 */
 203
 204         /* Context ID Comparators */
 205         { 0x6c, 32, RO, 0x20, "ETM_contextid_comparator_value1", }
 206         { 0x6d, 32, RO, 0x20, "ETM_contextid_comparator_value2", }
 207         { 0x6e, 32, RO, 0x20, "ETM_contextid_comparator_value3", }
 208         { 0x6f, 32, RO, 0x20, "ETM_contextid_comparator_mask", }
 209 #endif
 210
 211 static int etm_reg_arch_type = -1;
 212
 213 static int etm_get_reg(reg_t *reg);
 214 static int etm_read_reg_w_check(reg_t *reg,
 215                 uint8_t* check_value, uint8_t* check_mask);
 216 static int etm_register_user_commands(struct command_context_s *cmd_ctx);
 217 static int etm_set_reg_w_exec(reg_t *reg, uint8_t *buf);
 218 static int etm_write_reg(reg_t *reg, uint32_t value);
 219
 220 static command_t *etm_cmd;
 221
 222
 223 /* Look up register by ID ... most ETM instances only
 224  * support a subset of the possible registers.
 225  */
 226 static reg_t *etm_reg_lookup(etm_context_t *etm_ctx, unsigned id)
 227 {
 228         reg_cache_t *cache = etm_ctx->reg_cache;
 229         int i;
 230
 231         for (i = 0; i < cache->num_regs; i++) {
 232                 struct etm_reg_s *reg = cache->reg_list[i].arch_info;
 233
 234                 if (reg->reg_info->addr == id)
 235                         return &cache->reg_list[i];
 236         }
 237
 238         /* caller asking for nonexistent register is a bug! */
 239         /* REVISIT say which of the N targets was involved */
 240         LOG_ERROR("ETM: register 0x%02x not available", id);
 241         return NULL;
 242 }
 243
 244 static void etm_reg_add(unsigned bcd_vers, arm_jtag_t *jtag_info,
 245                 reg_cache_t *cache, etm_reg_t *ereg,
 246                 const struct etm_reg_info *r, unsigned nreg)
 247 {
 248         reg_t *reg = cache->reg_list;
 249
 250         reg += cache->num_regs;
 251         ereg += cache->num_regs;
 252
 253         /* add up to "nreg" registers from "r", if supported by this
 254          * version of the ETM, to the specified cache.
 255          */
 256         for (; nreg--; r++) {
 257
 258                 /* this ETM may be too old to have some registers */
 259                 if (r->bcd_vers > bcd_vers)
 260                         continue;
 261
 262                 reg->name = r->name;
 263                 reg->size = r->size;
 264                 reg->value = &ereg->value;
 265                 reg->arch_info = ereg;
 266                 reg->arch_type = etm_reg_arch_type;
 267                 reg++;
 268                 cache->num_regs++;
 269
 270                 ereg->reg_info = r;
 271                 ereg->jtag_info = jtag_info;
 272                 ereg++;
 273         }
 274 }
 275
 276 reg_cache_t *etm_build_reg_cache(target_t *target,
 277                 arm_jtag_t *jtag_info, etm_context_t *etm_ctx)
 278 {
 279         reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
 280         reg_t *reg_list = NULL;
 281         etm_reg_t *arch_info = NULL;
 282         unsigned bcd_vers, config;
 283
 284         /* register a register arch-type for etm registers only once */
 285         if (etm_reg_arch_type == -1)
 286                 etm_reg_arch_type = register_reg_arch_type(etm_get_reg,
 287                                 etm_set_reg_w_exec);
 288
 289         /* the actual registers are kept in two arrays */
 290         reg_list = calloc(128, sizeof(reg_t));
 291         arch_info = calloc(128, sizeof(etm_reg_t));
 292
 293         /* fill in values for the reg cache */
 294         reg_cache->name = "etm registers";
 295         reg_cache->next = NULL;
 296         reg_cache->reg_list = reg_list;
 297         reg_cache->num_regs = 0;
 298
 299         /* add ETM_CONFIG, then parse its values to see
 300          * which other registers exist in this ETM
 301          */
 302         etm_reg_add(0x10, jtag_info, reg_cache, arch_info,
 303                         etm_core, 1);
 304
 305         etm_get_reg(reg_list);
 306         etm_ctx->config = buf_get_u32((void *)&arch_info->value, 0, 32);
 307         config = etm_ctx->config;
 308
 309         /* figure ETM version then add base registers */
 310         if (config & (1 << 31)) {
 311                 bcd_vers = 0x20;
 312                 LOG_WARNING("ETMv2+ support is incomplete");
 313
 314                 /* REVISIT read ID register, distinguish ETMv3.3 etc;
 315                  * don't presume trace start/stop support is present;
 316                  * and include any context ID comparator registers.
 317                  */
 318         } else {
 319                 switch (config >> 28) {
 320                 case 7:
 321                 case 5:
 322                 case 3:
 323                         bcd_vers = 0x13;
 324                         break;
 325                 case 4:
 326                 case 2:
 327                         bcd_vers = 0x12;
 328                         break;
 329                 case 1:
 330                         bcd_vers = 0x11;
 331                         break;
 332                 case 0:
 333                         bcd_vers = 0x10;
 334                         break;
 335                 default:
 336                         LOG_WARNING("Bad ETMv1 protocol %d", config >> 28);
 337                         free(reg_cache);
 338                         free(reg_list);
 339                         free(arch_info);
 340                         return ERROR_OK;
 341                 }
 342         }
 343         etm_ctx->bcd_vers = bcd_vers;
 344         LOG_INFO("ETM v%d.%d", bcd_vers >> 4, bcd_vers & 0xf);
 345
 346         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 347                         etm_core + 1, ARRAY_SIZE(etm_core) - 1);
 348
 349         /* address and data comparators; counters; outputs */
 350         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 351                         etm_addr_comp, 4 * (0x0f & (config >> 0)));
 352         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 353                         etm_data_comp, 2 * (0x0f & (config >> 4)));
 354         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 355                         etm_counters, 4 * (0x07 & (config >> 13)));
 356         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 357                         etm_outputs, (0x07 & (config >> 20)));
 358
 359         /* FIFOFULL presence is optional
 360          * REVISIT for ETMv1.2 and later, don't bother adding this
 361          * unless ETM_SYS_CONFIG says it's also *supported* ...
 362          */
 363         if (config & (1 << 23))
 364                 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 365                                 etm_fifofull, ARRAY_SIZE(etm_fifofull));
 366
 367         /* sequencer is optional (for state-dependant triggering) */
 368         if (config & (1 << 16))
 369                 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 370                                 etm_sequencer, ARRAY_SIZE(etm_sequencer));
 371
 372         /* REVISIT could realloc and likely save half the memory
 373          * in the two chunks we allocated...
 374          */
 375
 376         /* the ETM might have an ETB connected */
 377         if (strcmp(etm_ctx->capture_driver->name, "etb") == 0)
 378         {
 379                 etb_t *etb = etm_ctx->capture_driver_priv;
 380
 381                 if (!etb)
 382                 {
 383                         LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
 384                         free(reg_cache);
 385                         free(reg_list);
 386                         free(arch_info);
 387                         return ERROR_OK;
 388                 }
 389
 390                 reg_cache->next = etb_build_reg_cache(etb);
 391
 392                 etb->reg_cache = reg_cache->next;
 393         }
 394
 395
 396         return reg_cache;
 397 }
 398
 399 static int etm_read_reg(reg_t *reg)
 400 {
 401         return etm_read_reg_w_check(reg, NULL, NULL);
 402 }
 403
 404 static int etm_store_reg(reg_t *reg)
 405 {
 406         return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
 407 }
 408
 409 int etm_setup(target_t *target)
 410 {
 411         int retval;
 412         uint32_t etm_ctrl_value;
 413         struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
 414         etm_context_t *etm_ctx = arm7_9->etm_ctx;
 415         reg_t *etm_ctrl_reg;
 416
 417         etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
 418         if (!etm_ctrl_reg)
 419                 return ERROR_OK;
 420
 421         /* initialize some ETM control register settings */
 422         etm_get_reg(etm_ctrl_reg);
 423         etm_ctrl_value = buf_get_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size);
 424
 425         /* clear the ETM powerdown bit (0) */
 426         etm_ctrl_value &= ~0x1;
 427
 428         /* configure port width (6:4), mode (17:16) and clocking (13) */
 429         etm_ctrl_value = (etm_ctrl_value &
 430                 ~ETM_PORT_WIDTH_MASK & ~ETM_PORT_MODE_MASK & ~ETM_PORT_CLOCK_MASK)
 431                 | etm_ctx->portmode;
 432
 433         buf_set_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size, etm_ctrl_value);
 434         etm_store_reg(etm_ctrl_reg);
 435
 436         if ((retval = jtag_execute_queue()) != ERROR_OK)
 437                 return retval;
 438
 439         if ((retval = etm_ctx->capture_driver->init(etm_ctx)) != ERROR_OK)
 440         {
 441                 LOG_ERROR("ETM capture driver initialization failed");
 442                 return retval;
 443         }
 444         return ERROR_OK;
 445 }
 446
 447 static int etm_get_reg(reg_t *reg)
 448 {
 449         int retval;
 450
 451         if ((retval = etm_read_reg(reg)) != ERROR_OK)
 452         {
 453                 LOG_ERROR("BUG: error scheduling etm register read");
 454                 return retval;
 455         }
 456
 457         if ((retval = jtag_execute_queue()) != ERROR_OK)
 458         {
 459                 LOG_ERROR("register read failed");
 460                 return retval;
 461         }
 462
 463         return ERROR_OK;
 464 }
 465
 466 static int etm_read_reg_w_check(reg_t *reg,
 467                 uint8_t* check_value, uint8_t* check_mask)
 468 {
 469         etm_reg_t *etm_reg = reg->arch_info;
 470         const struct etm_reg_info *r = etm_reg->reg_info;
 471         uint8_t reg_addr = r->addr & 0x7f;
 472         scan_field_t fields[3];
 473
 474         if (etm_reg->reg_info->mode == WO) {
 475                 LOG_ERROR("BUG: can't read write-only register %s", r->name);
 476                 return ERROR_INVALID_ARGUMENTS;
 477         }
 478
 479         LOG_DEBUG("%s (%u)", r->name, reg_addr);
 480
 481         jtag_set_end_state(TAP_IDLE);
 482         arm_jtag_scann(etm_reg->jtag_info, 0x6);
 483         arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
 484
 485         fields[0].tap = etm_reg->jtag_info->tap;
 486         fields[0].num_bits = 32;
 487         fields[0].out_value = reg->value;
 488         fields[0].in_value = NULL;
 489         fields[0].check_value = NULL;
 490         fields[0].check_mask = NULL;
 491
 492         fields[1].tap = etm_reg->jtag_info->tap;
 493         fields[1].num_bits = 7;
 494         fields[1].out_value = malloc(1);
 495         buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
 496         fields[1].in_value = NULL;
 497         fields[1].check_value = NULL;
 498         fields[1].check_mask = NULL;
 499
 500         fields[2].tap = etm_reg->jtag_info->tap;
 501         fields[2].num_bits = 1;
 502         fields[2].out_value = malloc(1);
 503         buf_set_u32(fields[2].out_value, 0, 1, 0);
 504         fields[2].in_value = NULL;
 505         fields[2].check_value = NULL;
 506         fields[2].check_mask = NULL;
 507
 508         jtag_add_dr_scan(3, fields, jtag_get_end_state());
 509
 510         fields[0].in_value = reg->value;
 511         fields[0].check_value = check_value;
 512         fields[0].check_mask = check_mask;
 513
 514         jtag_add_dr_scan_check(3, fields, jtag_get_end_state());
 515
 516         free(fields[1].out_value);
 517         free(fields[2].out_value);
 518
 519         return ERROR_OK;
 520 }
 521
 522 static int etm_set_reg(reg_t *reg, uint32_t value)
 523 {
 524         int retval;
 525
 526         if ((retval = etm_write_reg(reg, value)) != ERROR_OK)
 527         {
 528                 LOG_ERROR("BUG: error scheduling etm register write");
 529                 return retval;
 530         }
 531
 532         buf_set_u32(reg->value, 0, reg->size, value);
 533         reg->valid = 1;
 534         reg->dirty = 0;
 535
 536         return ERROR_OK;
 537 }
 538
 539 static int etm_set_reg_w_exec(reg_t *reg, uint8_t *buf)
 540 {
 541         int retval;
 542
 543         etm_set_reg(reg, buf_get_u32(buf, 0, reg->size));
 544
 545         if ((retval = jtag_execute_queue()) != ERROR_OK)
 546         {
 547                 LOG_ERROR("register write failed");
 548                 return retval;
 549         }
 550         return ERROR_OK;
 551 }
 552
 553 static int etm_write_reg(reg_t *reg, uint32_t value)
 554 {
 555         etm_reg_t *etm_reg = reg->arch_info;
 556         const struct etm_reg_info *r = etm_reg->reg_info;
 557         uint8_t reg_addr = r->addr & 0x7f;
 558         scan_field_t fields[3];
 559
 560         if (etm_reg->reg_info->mode == RO) {
 561                 LOG_ERROR("BUG: can't write read--only register %s", r->name);
 562                 return ERROR_INVALID_ARGUMENTS;
 563         }
 564
 565         LOG_DEBUG("%s (%u): 0x%8.8" PRIx32 "", r->name, reg_addr, value);
 566
 567         jtag_set_end_state(TAP_IDLE);
 568         arm_jtag_scann(etm_reg->jtag_info, 0x6);
 569         arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
 570
 571         fields[0].tap = etm_reg->jtag_info->tap;
 572         fields[0].num_bits = 32;
 573         uint8_t tmp1[4];
 574         fields[0].out_value = tmp1;
 575         buf_set_u32(fields[0].out_value, 0, 32, value);
 576         fields[0].in_value = NULL;
 577
 578         fields[1].tap = etm_reg->jtag_info->tap;
 579         fields[1].num_bits = 7;
 580         uint8_t tmp2;
 581         fields[1].out_value = &tmp2;
 582         buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
 583         fields[1].in_value = NULL;
 584
 585         fields[2].tap = etm_reg->jtag_info->tap;
 586         fields[2].num_bits = 1;
 587         uint8_t tmp3;
 588         fields[2].out_value = &tmp3;
 589         buf_set_u32(fields[2].out_value, 0, 1, 1);
 590         fields[2].in_value = NULL;
 591
 592         jtag_add_dr_scan(3, fields, jtag_get_end_state());
 593
 594         return ERROR_OK;
 595 }
 596
 597
 598 /* ETM trace analysis functionality
 599  *
 600  */
 601 extern etm_capture_driver_t etm_dummy_capture_driver;
 602 #if BUILD_OOCD_TRACE == 1
 603 extern etm_capture_driver_t oocd_trace_capture_driver;
 604 #endif
 605
 606 static etm_capture_driver_t *etm_capture_drivers[] =
 607 {
 608         &etb_capture_driver,
 609         &etm_dummy_capture_driver,
 610 #if BUILD_OOCD_TRACE == 1
 611         &oocd_trace_capture_driver,
 612 #endif
 613         NULL
 614 };
 615
 616 static int etm_read_instruction(etm_context_t *ctx, arm_instruction_t *instruction)
 617 {
 618         int i;
 619         int section = -1;
 620         uint32_t size_read;
 621         uint32_t opcode;
 622         int retval;
 623
 624         if (!ctx->image)
 625                 return ERROR_TRACE_IMAGE_UNAVAILABLE;
 626
 627         /* search for the section the current instruction belongs to */
 628         for (i = 0; i < ctx->image->num_sections; i++)
 629         {
 630                 if ((ctx->image->sections[i].base_address <= ctx->current_pc) &&
 631                         (ctx->image->sections[i].base_address + ctx->image->sections[i].size > ctx->current_pc))
 632                 {
 633                         section = i;
 634                         break;
 635                 }
 636         }
 637
 638         if (section == -1)
 639         {
 640                 /* current instruction couldn't be found in the image */
 641                 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
 642         }
 643
 644         if (ctx->core_state == ARMV4_5_STATE_ARM)
 645         {
 646                 uint8_t buf[4];
 647                 if ((retval = image_read_section(ctx->image, section,
 648                         ctx->current_pc - ctx->image->sections[section].base_address,
 649                         4, buf, &size_read)) != ERROR_OK)
 650                 {
 651                         LOG_ERROR("error while reading instruction: %i", retval);
 652                         return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
 653                 }
 654                 opcode = target_buffer_get_u32(ctx->target, buf);
 655                 arm_evaluate_opcode(opcode, ctx->current_pc, instruction);
 656         }
 657         else if (ctx->core_state == ARMV4_5_STATE_THUMB)
 658         {
 659                 uint8_t buf[2];
 660                 if ((retval = image_read_section(ctx->image, section,
 661                         ctx->current_pc - ctx->image->sections[section].base_address,
 662                         2, buf, &size_read)) != ERROR_OK)
 663                 {
 664                         LOG_ERROR("error while reading instruction: %i", retval);
 665                         return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
 666                 }
 667                 opcode = target_buffer_get_u16(ctx->target, buf);
 668                 thumb_evaluate_opcode(opcode, ctx->current_pc, instruction);
 669         }
 670         else if (ctx->core_state == ARMV4_5_STATE_JAZELLE)
 671         {
 672                 LOG_ERROR("BUG: tracing of jazelle code not supported");
 673                 exit(-1);
 674         }
 675         else
 676         {
 677                 LOG_ERROR("BUG: unknown core state encountered");
 678                 exit(-1);
 679         }
 680
 681         return ERROR_OK;
 682 }
 683
 684 static int etmv1_next_packet(etm_context_t *ctx, uint8_t *packet, int apo)
 685 {
 686         while (ctx->data_index < ctx->trace_depth)
 687         {
 688                 /* if the caller specified an address packet offset, skip until the
 689                  * we reach the n-th cycle marked with tracesync */
 690                 if (apo > 0)
 691                 {
 692                         if (ctx->trace_data[ctx->data_index].flags & ETMV1_TRACESYNC_CYCLE)
 693                                 apo--;
 694
 695                         if (apo > 0)
 696                         {
 697                                 ctx->data_index++;
 698                                 ctx->data_half = 0;
 699                         }
 700                         continue;
 701                 }
 702
 703                 /* no tracedata output during a TD cycle
 704                  * or in a trigger cycle */
 705                 if ((ctx->trace_data[ctx->data_index].pipestat == STAT_TD)
 706                         || (ctx->trace_data[ctx->data_index].flags & ETMV1_TRIGGER_CYCLE))
 707                 {
 708                         ctx->data_index++;
 709                         ctx->data_half = 0;
 710                         continue;
 711                 }
 712
 713                 if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_16BIT)
 714                 {
 715                         if (ctx->data_half == 0)
 716                         {
 717                                 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
 718                                 ctx->data_half = 1;
 719                         }
 720                         else
 721                         {
 722                                 *packet = (ctx->trace_data[ctx->data_index].packet & 0xff00) >> 8;
 723                                 ctx->data_half = 0;
 724                                 ctx->data_index++;
 725                         }
 726                 }
 727                 else if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
 728                 {
 729                         *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
 730                         ctx->data_index++;
 731                 }
 732                 else
 733                 {
 734                         /* on a 4-bit port, a packet will be output during two consecutive cycles */
 735                         if (ctx->data_index > (ctx->trace_depth - 2))
 736                                 return -1;
 737
 738                         *packet = ctx->trace_data[ctx->data_index].packet & 0xf;
 739                         *packet |= (ctx->trace_data[ctx->data_index + 1].packet & 0xf) << 4;
 740                         ctx->data_index += 2;
 741                 }
 742
 743                 return 0;
 744         }
 745
 746         return -1;
 747 }
 748
 749 static int etmv1_branch_address(etm_context_t *ctx)
 750 {
 751         int retval;
 752         uint8_t packet;
 753         int shift = 0;
 754         int apo;
 755         uint32_t i;
 756
 757         /* quit analysis if less than two cycles are left in the trace
 758          * because we can't extract the APO */
 759         if (ctx->data_index > (ctx->trace_depth - 2))
 760                 return -1;
 761
 762         /* a BE could be output during an APO cycle, skip the current
 763          * and continue with the new one */
 764         if (ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x4)
 765                 return 1;
 766         if (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x4)
 767                 return 2;
 768
 769         /* address packet offset encoded in the next two cycles' pipestat bits */
 770         apo = ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x3;
 771         apo |= (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x3) << 2;
 772
 773         /* count number of tracesync cycles between current pipe_index and data_index
 774          * i.e. the number of tracesyncs that data_index already passed by
 775          * to subtract them from the APO */
 776         for (i = ctx->pipe_index; i < ctx->data_index; i++)
 777         {
 778                 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & ETMV1_TRACESYNC_CYCLE)
 779                         apo--;
 780         }
 781
 782         /* extract up to four 7-bit packets */
 783         do {
 784                 if ((retval = etmv1_next_packet(ctx, &packet, (shift == 0) ? apo + 1 : 0)) != 0)
 785                         return -1;
 786                 ctx->last_branch &= ~(0x7f << shift);
 787                 ctx->last_branch |= (packet & 0x7f) << shift;
 788                 shift += 7;
 789         } while ((packet & 0x80) && (shift < 28));
 790
 791         /* one last packet holding 4 bits of the address, plus the branch reason code */
 792         if ((shift == 28) && (packet & 0x80))
 793         {
 794                 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
 795                         return -1;
 796                 ctx->last_branch &= 0x0fffffff;
 797                 ctx->last_branch |= (packet & 0x0f) << 28;
 798                 ctx->last_branch_reason = (packet & 0x70) >> 4;
 799                 shift += 4;
 800         }
 801         else
 802         {
 803                 ctx->last_branch_reason = 0;
 804         }
 805
 806         if (shift == 32)
 807         {
 808                 ctx->pc_ok = 1;
 809         }
 810
 811         /* if a full address was output, we might have branched into Jazelle state */
 812         if ((shift == 32) && (packet & 0x80))
 813         {
 814                 ctx->core_state = ARMV4_5_STATE_JAZELLE;
 815         }
 816         else
 817         {
 818                 /* if we didn't branch into Jazelle state, the current processor state is
 819                  * encoded in bit 0 of the branch target address */
 820                 if (ctx->last_branch & 0x1)
 821                 {
 822                         ctx->core_state = ARMV4_5_STATE_THUMB;
 823                         ctx->last_branch &= ~0x1;
 824                 }
 825                 else
 826                 {
 827                         ctx->core_state = ARMV4_5_STATE_ARM;
 828                         ctx->last_branch &= ~0x3;
 829                 }
 830         }
 831
 832         return 0;
 833 }
 834
 835 static int etmv1_data(etm_context_t *ctx, int size, uint32_t *data)
 836 {
 837         int j;
 838         uint8_t buf[4];
 839         int retval;
 840
 841         for (j = 0; j < size; j++)
 842         {
 843                 if ((retval = etmv1_next_packet(ctx, &buf[j], 0)) != 0)
 844                         return -1;
 845         }
 846
 847         if (size == 8)
 848         {
 849                 LOG_ERROR("TODO: add support for 64-bit values");
 850                 return -1;
 851         }
 852         else if (size == 4)
 853                 *data = target_buffer_get_u32(ctx->target, buf);
 854         else if (size == 2)
 855                 *data = target_buffer_get_u16(ctx->target, buf);
 856         else if (size == 1)
 857                 *data = buf[0];
 858         else
 859                 return -1;
 860
 861         return 0;
 862 }
 863
 864 static int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd_ctx)
 865 {
 866         int retval;
 867         arm_instruction_t instruction;
 868
 869         /* read the trace data if it wasn't read already */
 870         if (ctx->trace_depth == 0)
 871                 ctx->capture_driver->read_trace(ctx);
 872
 873         /* start at the beginning of the captured trace */
 874         ctx->pipe_index = 0;
 875         ctx->data_index = 0;
 876         ctx->data_half = 0;
 877
 878         /* neither the PC nor the data pointer are valid */
 879         ctx->pc_ok = 0;
 880         ctx->ptr_ok = 0;
 881
 882         while (ctx->pipe_index < ctx->trace_depth)
 883         {
 884                 uint8_t pipestat = ctx->trace_data[ctx->pipe_index].pipestat;
 885                 uint32_t next_pc = ctx->current_pc;
 886                 uint32_t old_data_index = ctx->data_index;
 887                 uint32_t old_data_half = ctx->data_half;
 888                 uint32_t old_index = ctx->pipe_index;
 889                 uint32_t last_instruction = ctx->last_instruction;
 890                 uint32_t cycles = 0;
 891                 int current_pc_ok = ctx->pc_ok;
 892
 893                 if (ctx->trace_data[ctx->pipe_index].flags & ETMV1_TRIGGER_CYCLE)
 894                 {
 895                         command_print(cmd_ctx, "--- trigger ---");
 896                 }
 897
 898                 /* instructions execute in IE/D or BE/D cycles */
 899                 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
 900                         ctx->last_instruction = ctx->pipe_index;
 901
 902                 /* if we don't have a valid pc skip until we reach an indirect branch */
 903                 if ((!ctx->pc_ok) && (pipestat != STAT_BE))
 904                 {
 905                         ctx->pipe_index++;
 906                         continue;
 907                 }
 908
 909                 /* any indirect branch could have interrupted instruction flow
 910                  * - the branch reason code could indicate a trace discontinuity
 911                  * - a branch to the exception vectors indicates an exception
 912                  */
 913                 if ((pipestat == STAT_BE) || (pipestat == STAT_BD))
 914                 {
 915                         /* backup current data index, to be able to consume the branch address
 916                          * before examining data address and values
 917                          */
 918                         old_data_index = ctx->data_index;
 919                         old_data_half = ctx->data_half;
 920
 921                         ctx->last_instruction = ctx->pipe_index;
 922
 923                         if ((retval = etmv1_branch_address(ctx)) != 0)
 924                         {
 925                                 /* negative return value from etmv1_branch_address means we ran out of packets,
 926                                  * quit analysing the trace */
 927                                 if (retval < 0)
 928                                         break;
 929
 930                                 /* a positive return values means the current branch was abandoned,
 931                                  * and a new branch was encountered in cycle ctx->pipe_index + retval;
 932                                  */
 933                                 LOG_WARNING("abandoned branch encountered, correctnes of analysis uncertain");
 934                                 ctx->pipe_index += retval;
 935                                 continue;
 936                         }
 937
 938                         /* skip over APO cycles */
 939                         ctx->pipe_index += 2;
 940
 941                         switch (ctx->last_branch_reason)
 942                         {
 943                                 case 0x0:       /* normal PC change */
 944                                         next_pc = ctx->last_branch;
 945                                         break;
 946                                 case 0x1:       /* tracing enabled */
 947                                         command_print(cmd_ctx, "--- tracing enabled at 0x%8.8" PRIx32 " ---", ctx->last_branch);
 948                                         ctx->current_pc = ctx->last_branch;
 949                                         ctx->pipe_index++;
 950                                         continue;
 951                                         break;
 952                                 case 0x2:       /* trace restarted after FIFO overflow */
 953                                         command_print(cmd_ctx, "--- trace restarted after FIFO overflow at 0x%8.8" PRIx32 " ---", ctx->last_branch);
 954                                         ctx->current_pc = ctx->last_branch;
 955                                         ctx->pipe_index++;
 956                                         continue;
 957                                         break;
 958                                 case 0x3:       /* exit from debug state */
 959                                         command_print(cmd_ctx, "--- exit from debug state at 0x%8.8" PRIx32 " ---", ctx->last_branch);
 960                                         ctx->current_pc = ctx->last_branch;
 961                                         ctx->pipe_index++;
 962                                         continue;
 963                                         break;
 964                                 case 0x4:       /* periodic synchronization point */
 965                                         next_pc = ctx->last_branch;
 966                                         /* if we had no valid PC prior to this synchronization point,
 967                                          * we have to move on with the next trace cycle
 968                                          */
 969                                         if (!current_pc_ok)
 970                                         {
 971                                                 command_print(cmd_ctx, "--- periodic synchronization point at 0x%8.8" PRIx32 " ---", next_pc);
 972                                                 ctx->current_pc = next_pc;
 973                                                 ctx->pipe_index++;
 974                                                 continue;
 975                                         }
 976                                         break;
 977                                 default:        /* reserved */
 978                                         LOG_ERROR("BUG: branch reason code 0x%" PRIx32 " is reserved", ctx->last_branch_reason);
 979                                         exit(-1);
 980                                         break;
 981                         }
 982
 983                         /* if we got here the branch was a normal PC change
 984                          * (or a periodic synchronization point, which means the same for that matter)
 985                          * if we didn't accquire a complete PC continue with the next cycle
 986                          */
 987                         if (!ctx->pc_ok)
 988                                 continue;
 989
 990                         /* indirect branch to the exception vector means an exception occured */
 991                         if ((ctx->last_branch <= 0x20)
 992                                 || ((ctx->last_branch >= 0xffff0000) && (ctx->last_branch <= 0xffff0020)))
 993                         {
 994                                 if ((ctx->last_branch & 0xff) == 0x10)
 995                                 {
 996                                         command_print(cmd_ctx, "data abort");
 997                                 }
 998                                 else
 999                                 {
1000                                         command_print(cmd_ctx, "exception vector 0x%2.2" PRIx32 "", ctx->last_branch);
1001                                         ctx->current_pc = ctx->last_branch;
1002                                         ctx->pipe_index++;
1003                                         continue;
1004                                 }
1005                         }
1006                 }
1007
1008                 /* an instruction was executed (or not, depending on the condition flags)
1009                  * retrieve it from the image for displaying */
1010                 if (ctx->pc_ok && (pipestat != STAT_WT) && (pipestat != STAT_TD) &&
1011                         !(((pipestat == STAT_BE) || (pipestat == STAT_BD)) &&
1012                                 ((ctx->last_branch_reason != 0x0) && (ctx->last_branch_reason != 0x4))))
1013                 {
1014                         if ((retval = etm_read_instruction(ctx, &instruction)) != ERROR_OK)
1015                         {
1016                                 /* can't continue tracing with no image available */
1017                                 if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
1018                                 {
1019                                         return retval;
1020                                 }
1021                                 else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE)
1022                                 {
1023                                         /* TODO: handle incomplete images
1024                                          * for now we just quit the analsysis*/
1025                                         return retval;
1026                                 }
1027                         }
1028
1029                         cycles = old_index - last_instruction;
1030                 }
1031
1032                 if ((pipestat == STAT_ID) || (pipestat == STAT_BD))
1033                 {
1034                         uint32_t new_data_index = ctx->data_index;
1035                         uint32_t new_data_half = ctx->data_half;
1036
1037                         /* in case of a branch with data, the branch target address was consumed before
1038                          * we temporarily go back to the saved data index */
1039                         if (pipestat == STAT_BD)
1040                         {
1041                                 ctx->data_index = old_data_index;
1042                                 ctx->data_half = old_data_half;
1043                         }
1044
1045                         if (ctx->tracemode & ETMV1_TRACE_ADDR)
1046                         {
1047                                 uint8_t packet;
1048                                 int shift = 0;
1049
1050                                 do {
1051                                         if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
1052                                                 return ERROR_ETM_ANALYSIS_FAILED;
1053                                         ctx->last_ptr &= ~(0x7f << shift);
1054                                         ctx->last_ptr |= (packet & 0x7f) << shift;
1055                                         shift += 7;
1056                                 } while ((packet & 0x80) && (shift < 32));
1057
1058                                 if (shift >= 32)
1059                                         ctx->ptr_ok = 1;
1060
1061                                 if (ctx->ptr_ok)
1062                                 {
1063                                         command_print(cmd_ctx, "address: 0x%8.8" PRIx32 "", ctx->last_ptr);
1064                                 }
1065                         }
1066
1067                         if (ctx->tracemode & ETMV1_TRACE_DATA)
1068                         {
1069                                 if ((instruction.type == ARM_LDM) || (instruction.type == ARM_STM))
1070                                 {
1071                                         int i;
1072                                         for (i = 0; i < 16; i++)
1073                                         {
1074                                                 if (instruction.info.load_store_multiple.register_list & (1 << i))
1075                                                 {
1076                                                         uint32_t data;
1077                                                         if (etmv1_data(ctx, 4, &data) != 0)
1078                                                                 return ERROR_ETM_ANALYSIS_FAILED;
1079                                                         command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
1080                                                 }
1081                                         }
1082                                 }
1083                                 else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_STRH))
1084                                 {
1085                                         uint32_t data;
1086                                         if (etmv1_data(ctx, arm_access_size(&instruction), &data) != 0)
1087                                                 return ERROR_ETM_ANALYSIS_FAILED;
1088                                         command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
1089                                 }
1090                         }
1091
1092                         /* restore data index after consuming BD address and data */
1093                         if (pipestat == STAT_BD)
1094                         {
1095                                 ctx->data_index = new_data_index;
1096                                 ctx->data_half = new_data_half;
1097                         }
1098                 }
1099
1100                 /* adjust PC */
1101                 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
1102                 {
1103                         if (((instruction.type == ARM_B) ||
1104                              (instruction.type == ARM_BL) ||
1105                              (instruction.type == ARM_BLX)) &&
1106                             (instruction.info.b_bl_bx_blx.target_address != 0xffffffff))
1107                         {
1108                                 next_pc = instruction.info.b_bl_bx_blx.target_address;
1109                         }
1110                         else
1111                         {
1112                                 next_pc += (ctx->core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
1113                         }
1114                 }
1115                 else if (pipestat == STAT_IN)
1116                 {
1117                         next_pc += (ctx->core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
1118                 }
1119
1120                 if ((pipestat != STAT_TD) && (pipestat != STAT_WT))
1121                 {
1122                         char cycles_text[32] = "";
1123
1124                         /* if the trace was captured with cycle accurate tracing enabled,
1125                          * output the number of cycles since the last executed instruction
1126                          */
1127                         if (ctx->tracemode & ETMV1_CYCLE_ACCURATE)
1128                         {
1129                                 snprintf(cycles_text, 32, " (%i %s)",
1130                                          (int)cycles,
1131                                         (cycles == 1) ? "cycle" : "cycles");
1132                         }
1133
1134                         command_print(cmd_ctx, "%s%s%s",
1135                                 instruction.text,
1136                                 (pipestat == STAT_IN) ? " (not executed)" : "",
1137                                 cycles_text);
1138
1139                         ctx->current_pc = next_pc;
1140
1141                         /* packets for an instruction don't start on or before the preceding
1142                          * functional pipestat (i.e. other than WT or TD)
1143                          */
1144                         if (ctx->data_index <= ctx->pipe_index)
1145                         {
1146                                 ctx->data_index = ctx->pipe_index + 1;
1147                                 ctx->data_half = 0;
1148                         }
1149                 }
1150
1151                 ctx->pipe_index += 1;
1152         }
1153
1154         return ERROR_OK;
1155 }
1156
1157 static int handle_etm_tracemode_command_update(
1158                 struct command_context_s *cmd_ctx,
1159                 char **args, etmv1_tracemode_t *mode)
1160 {
1161         etmv1_tracemode_t tracemode;
1162
1163         /* what parts of data access are traced? */
1164         if (strcmp(args[0], "none") == 0)
1165                 tracemode = ETMV1_TRACE_NONE;
1166         else if (strcmp(args[0], "data") == 0)
1167                 tracemode = ETMV1_TRACE_DATA;
1168         else if (strcmp(args[0], "address") == 0)
1169                 tracemode = ETMV1_TRACE_ADDR;
1170         else if (strcmp(args[0], "all") == 0)
1171                 tracemode = ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR;
1172         else
1173         {
1174                 command_print(cmd_ctx, "invalid option '%s'", args[0]);
1175                 return ERROR_OK;
1176         }
1177
1178         uint8_t context_id;
1179         COMMAND_PARSE_NUMBER(u8, args[1], context_id);
1180         switch (context_id)
1181         {
1182         case 0:
1183                 tracemode |= ETMV1_CONTEXTID_NONE;
1184                 break;
1185         case 8:
1186                 tracemode |= ETMV1_CONTEXTID_8;
1187                 break;
1188         case 16:
1189                 tracemode |= ETMV1_CONTEXTID_16;
1190                 break;
1191         case 32:
1192                 tracemode |= ETMV1_CONTEXTID_32;
1193                 break;
1194         default:
1195                 command_print(cmd_ctx, "invalid option '%s'", args[1]);
1196                 return ERROR_OK;
1197         }
1198
1199         if (strcmp(args[2], "enable") == 0)
1200                 tracemode |= ETMV1_CYCLE_ACCURATE;
1201         else if (strcmp(args[2], "disable") == 0)
1202                 tracemode |= 0;
1203         else
1204         {
1205                 command_print(cmd_ctx, "invalid option '%s'", args[2]);
1206                 return ERROR_OK;
1207         }
1208
1209         if (strcmp(args[3], "enable") == 0)
1210                 tracemode |= ETMV1_BRANCH_OUTPUT;
1211         else if (strcmp(args[3], "disable") == 0)
1212                 tracemode |= 0;
1213         else
1214         {
1215                 command_print(cmd_ctx, "invalid option '%s'", args[3]);
1216                 return ERROR_OK;
1217         }
1218
1219         /* IGNORED:
1220          *  - CPRT tracing (coprocessor register transfers)
1221          *  - debug request (causes debug entry on trigger)
1222          *  - stall on FIFOFULL (preventing tracedata lossage)
1223          */
1224         *mode = tracemode;
1225
1226         return ERROR_OK;
1227 }
1228
1229 static int handle_etm_tracemode_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1230 {
1231         target_t *target = get_current_target(cmd_ctx);
1232
1233         armv4_5_common_t *armv4_5;
1234         arm7_9_common_t *arm7_9;
1235         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1236         {
1237                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1238                 return ERROR_OK;
1239         }
1240
1241         if (!arm7_9->etm_ctx)
1242         {
1243                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1244                 return ERROR_OK;
1245         }
1246
1247         etmv1_tracemode_t tracemode = arm7_9->etm_ctx->tracemode;
1248         switch (argc)
1249         {
1250         case 0:
1251                 break;
1252         case 4:
1253                 handle_etm_tracemode_command_update(cmd_ctx, args, &tracemode);
1254                 break;
1255         default:
1256                 command_print(cmd_ctx, "usage: configure trace mode "
1257                                 "<none | data | address | all> "
1258                                 "<context id bits> <cycle accurate> <branch output>");
1259                 return ERROR_OK;
1260         }
1261
1262         command_print(cmd_ctx, "current tracemode configuration:");
1263
1264         switch (tracemode & ETMV1_TRACE_MASK)
1265         {
1266                 case ETMV1_TRACE_NONE:
1267                         command_print(cmd_ctx, "data tracing: none");
1268                         break;
1269                 case ETMV1_TRACE_DATA:
1270                         command_print(cmd_ctx, "data tracing: data only");
1271                         break;
1272                 case ETMV1_TRACE_ADDR:
1273                         command_print(cmd_ctx, "data tracing: address only");
1274                         break;
1275                 case ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR:
1276                         command_print(cmd_ctx, "data tracing: address and data");
1277                         break;
1278         }
1279
1280         switch (tracemode & ETMV1_CONTEXTID_MASK)
1281         {
1282                 case ETMV1_CONTEXTID_NONE:
1283                         command_print(cmd_ctx, "contextid tracing: none");
1284                         break;
1285                 case ETMV1_CONTEXTID_8:
1286                         command_print(cmd_ctx, "contextid tracing: 8 bit");
1287                         break;
1288                 case ETMV1_CONTEXTID_16:
1289                         command_print(cmd_ctx, "contextid tracing: 16 bit");
1290                         break;
1291                 case ETMV1_CONTEXTID_32:
1292                         command_print(cmd_ctx, "contextid tracing: 32 bit");
1293                         break;
1294         }
1295
1296         if (tracemode & ETMV1_CYCLE_ACCURATE)
1297         {
1298                 command_print(cmd_ctx, "cycle-accurate tracing enabled");
1299         }
1300         else
1301         {
1302                 command_print(cmd_ctx, "cycle-accurate tracing disabled");
1303         }
1304
1305         if (tracemode & ETMV1_BRANCH_OUTPUT)
1306         {
1307                 command_print(cmd_ctx, "full branch address output enabled");
1308         }
1309         else
1310         {
1311                 command_print(cmd_ctx, "full branch address output disabled");
1312         }
1313
1314         /* only update ETM_CTRL register if tracemode changed */
1315         if (arm7_9->etm_ctx->tracemode != tracemode)
1316         {
1317                 reg_t *etm_ctrl_reg;
1318
1319                 etm_ctrl_reg = etm_reg_lookup(arm7_9->etm_ctx, ETM_CTRL);
1320                 if (!etm_ctrl_reg)
1321                         return ERROR_OK;
1322
1323                 etm_get_reg(etm_ctrl_reg);
1324
1325                 buf_set_u32(etm_ctrl_reg->value, 2, 2, tracemode & ETMV1_TRACE_MASK);
1326                 buf_set_u32(etm_ctrl_reg->value, 14, 2, (tracemode & ETMV1_CONTEXTID_MASK) >> 4);
1327                 buf_set_u32(etm_ctrl_reg->value, 12, 1, (tracemode & ETMV1_CYCLE_ACCURATE) >> 8);
1328                 buf_set_u32(etm_ctrl_reg->value, 8, 1, (tracemode & ETMV1_BRANCH_OUTPUT) >> 9);
1329                 etm_store_reg(etm_ctrl_reg);
1330
1331                 arm7_9->etm_ctx->tracemode = tracemode;
1332
1333                 /* invalidate old trace data */
1334                 arm7_9->etm_ctx->capture_status = TRACE_IDLE;
1335                 if (arm7_9->etm_ctx->trace_depth > 0)
1336                 {
1337                         free(arm7_9->etm_ctx->trace_data);
1338                         arm7_9->etm_ctx->trace_data = NULL;
1339                 }
1340                 arm7_9->etm_ctx->trace_depth = 0;
1341         }
1342
1343         return ERROR_OK;
1344 }
1345
1346 static int handle_etm_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1347 {
1348         target_t *target;
1349         armv4_5_common_t *armv4_5;
1350         arm7_9_common_t *arm7_9;
1351         etm_portmode_t portmode = 0x0;
1352         etm_context_t *etm_ctx = malloc(sizeof(etm_context_t));
1353         int i;
1354
1355         if (argc != 5)
1356         {
1357                 free(etm_ctx);
1358                 return ERROR_COMMAND_SYNTAX_ERROR;
1359         }
1360
1361         target = get_target(args[0]);
1362         if (!target)
1363         {
1364                 LOG_ERROR("target '%s' not defined", args[0]);
1365                 free(etm_ctx);
1366                 return ERROR_FAIL;
1367         }
1368
1369         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1370         {
1371                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1372                 free(etm_ctx);
1373                 return ERROR_FAIL;
1374         }
1375
1376         uint8_t port_width;
1377         COMMAND_PARSE_NUMBER(u8, args[1], port_width);
1378         switch (port_width)
1379         {
1380                 case 4:
1381                         portmode |= ETM_PORT_4BIT;
1382                         break;
1383                 case 8:
1384                         portmode |= ETM_PORT_8BIT;
1385                         break;
1386                 case 16:
1387                         portmode |= ETM_PORT_16BIT;
1388                         break;
1389                 default:
1390                         command_print(cmd_ctx, "unsupported ETM port width '%s', must be 4, 8 or 16", args[1]);
1391                         free(etm_ctx);
1392                         return ERROR_FAIL;
1393         }
1394
1395         if (strcmp("normal", args[2]) == 0)
1396         {
1397                 portmode |= ETM_PORT_NORMAL;
1398         }
1399         else if (strcmp("multiplexed", args[2]) == 0)
1400         {
1401                 portmode |= ETM_PORT_MUXED;
1402         }
1403         else if (strcmp("demultiplexed", args[2]) == 0)
1404         {
1405                 portmode |= ETM_PORT_DEMUXED;
1406         }
1407         else
1408         {
1409                 command_print(cmd_ctx, "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", args[2]);
1410                 free(etm_ctx);
1411                 return ERROR_FAIL;
1412         }
1413
1414         if (strcmp("half", args[3]) == 0)
1415         {
1416                 portmode |= ETM_PORT_HALF_CLOCK;
1417         }
1418         else if (strcmp("full", args[3]) == 0)
1419         {
1420                 portmode |= ETM_PORT_FULL_CLOCK;
1421         }
1422         else
1423         {
1424                 command_print(cmd_ctx, "unsupported ETM port clocking '%s', must be 'full' or 'half'", args[3]);
1425                 free(etm_ctx);
1426                 return ERROR_FAIL;
1427         }
1428
1429         for (i = 0; etm_capture_drivers[i]; i++)
1430         {
1431                 if (strcmp(args[4], etm_capture_drivers[i]->name) == 0)
1432                 {
1433                         int retval;
1434                         if ((retval = etm_capture_drivers[i]->register_commands(cmd_ctx)) != ERROR_OK)
1435                         {
1436                                 free(etm_ctx);
1437                                 return retval;
1438                         }
1439
1440                         etm_ctx->capture_driver = etm_capture_drivers[i];
1441
1442                         break;
1443                 }
1444         }
1445
1446         if (!etm_capture_drivers[i])
1447         {
1448                 /* no supported capture driver found, don't register an ETM */
1449                 free(etm_ctx);
1450                 LOG_ERROR("trace capture driver '%s' not found", args[4]);
1451                 return ERROR_FAIL;
1452         }
1453
1454         etm_ctx->target = target;
1455         etm_ctx->trigger_percent = 50;
1456         etm_ctx->trace_data = NULL;
1457         etm_ctx->trace_depth = 0;
1458         etm_ctx->portmode = portmode;
1459         etm_ctx->tracemode = 0x0;
1460         etm_ctx->core_state = ARMV4_5_STATE_ARM;
1461         etm_ctx->image = NULL;
1462         etm_ctx->pipe_index = 0;
1463         etm_ctx->data_index = 0;
1464         etm_ctx->current_pc = 0x0;
1465         etm_ctx->pc_ok = 0;
1466         etm_ctx->last_branch = 0x0;
1467         etm_ctx->last_branch_reason = 0x0;
1468         etm_ctx->last_ptr = 0x0;
1469         etm_ctx->ptr_ok = 0x0;
1470         etm_ctx->last_instruction = 0;
1471
1472         arm7_9->etm_ctx = etm_ctx;
1473
1474         return etm_register_user_commands(cmd_ctx);
1475 }
1476
1477 static int handle_etm_info_command(struct command_context_s *cmd_ctx,
1478                 char *cmd, char **args, int argc)
1479 {
1480         target_t *target;
1481         armv4_5_common_t *armv4_5;
1482         arm7_9_common_t *arm7_9;
1483         etm_context_t *etm;
1484         reg_t *etm_sys_config_reg;
1485
1486         int max_port_size;
1487
1488         target = get_current_target(cmd_ctx);
1489
1490         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1491         {
1492                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1493                 return ERROR_OK;
1494         }
1495
1496         etm = arm7_9->etm_ctx;
1497         if (!etm)
1498         {
1499                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1500                 return ERROR_OK;
1501         }
1502
1503         command_print(cmd_ctx, "ETM v%d.%d",
1504                         etm->bcd_vers >> 4, etm->bcd_vers & 0xf);
1505         command_print(cmd_ctx, "pairs of address comparators: %i",
1506                         (int) (etm->config >> 0) & 0x0f);
1507         command_print(cmd_ctx, "data comparators: %i",
1508                         (int) (etm->config >> 4) & 0x0f);
1509         command_print(cmd_ctx, "memory map decoders: %i",
1510                         (int) (etm->config >> 8) & 0x1f);
1511         command_print(cmd_ctx, "number of counters: %i",
1512                         (int) (etm->config >> 13) & 0x07);
1513         command_print(cmd_ctx, "sequencer %spresent",
1514                         (int) (etm->config & (1 << 16)) ? "" : "not ");
1515         command_print(cmd_ctx, "number of ext. inputs: %i",
1516                         (int) (etm->config >> 17) & 0x07);
1517         command_print(cmd_ctx, "number of ext. outputs: %i",
1518                         (int) (etm->config >> 20) & 0x07);
1519         command_print(cmd_ctx, "FIFO full %spresent",
1520                         (int) (etm->config & (1 << 23)) ? "" : "not ");
1521         if (etm->bcd_vers < 0x20)
1522                 command_print(cmd_ctx, "protocol version: %i",
1523                                 (int) (etm->config >> 28) & 0x07);
1524         else {
1525                 command_print(cmd_ctx, "trace start/stop %spresent",
1526                                 (etm->config & (1 << 26)) ? "" : "not ");
1527                 command_print(cmd_ctx, "number of context comparators: %i",
1528                                 (int) (etm->config >> 24) & 0x03);
1529         }
1530
1531         /* SYS_CONFIG isn't present before ETMv1.2 */
1532         etm_sys_config_reg = etm_reg_lookup(etm, ETM_SYS_CONFIG);
1533         if (!etm_sys_config_reg)
1534                 return ERROR_OK;
1535
1536         etm_get_reg(etm_sys_config_reg);
1537
1538         switch (buf_get_u32(etm_sys_config_reg->value, 0, 3))
1539         {
1540                 case 0:
1541                         max_port_size = 4;
1542                         break;
1543                 case 1:
1544                         max_port_size = 8;
1545                         break;
1546                 case 2:
1547                         max_port_size = 16;
1548                         break;
1549                 default:
1550                         LOG_ERROR("Illegal max_port_size");
1551                         exit(-1);
1552         }
1553         command_print(cmd_ctx, "max. port size: %i", max_port_size);
1554
1555         command_print(cmd_ctx, "half-rate clocking %ssupported",
1556                         (buf_get_u32(etm_sys_config_reg->value, 3, 1) == 1) ? "" : "not ");
1557         command_print(cmd_ctx, "full-rate clocking %ssupported",
1558                         (buf_get_u32(etm_sys_config_reg->value, 4, 1) == 1) ? "" : "not ");
1559         command_print(cmd_ctx, "normal trace format %ssupported",
1560                         (buf_get_u32(etm_sys_config_reg->value, 5, 1) == 1) ? "" : "not ");
1561         command_print(cmd_ctx, "multiplex trace format %ssupported",
1562                         (buf_get_u32(etm_sys_config_reg->value, 6, 1) == 1) ? "" : "not ");
1563         command_print(cmd_ctx, "demultiplex trace format %ssupported",
1564                         (buf_get_u32(etm_sys_config_reg->value, 7, 1) == 1) ? "" : "not ");
1565         command_print(cmd_ctx, "FIFO full %ssupported",
1566                         (buf_get_u32(etm_sys_config_reg->value, 8, 1) == 1) ? "" : "not ");
1567
1568         return ERROR_OK;
1569 }
1570
1571 static int handle_etm_status_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1572 {
1573         target_t *target;
1574         armv4_5_common_t *armv4_5;
1575         arm7_9_common_t *arm7_9;
1576         etm_context_t *etm;
1577         trace_status_t trace_status;
1578
1579         target = get_current_target(cmd_ctx);
1580
1581         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1582         {
1583                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1584                 return ERROR_OK;
1585         }
1586
1587         if (!arm7_9->etm_ctx)
1588         {
1589                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1590                 return ERROR_OK;
1591         }
1592         etm = arm7_9->etm_ctx;
1593
1594         /* ETM status */
1595         if (etm->bcd_vers >= 0x11) {
1596                 reg_t *reg;
1597
1598                 reg = etm_reg_lookup(etm, ETM_STATUS);
1599                 if (!reg)
1600                         return ERROR_OK;
1601                 if (etm_get_reg(reg) == ERROR_OK) {
1602                         unsigned s = buf_get_u32(reg->value, 0, reg->size);
1603
1604                         command_print(cmd_ctx, "etm: %s%s%s%s",
1605                                 /* bit(1) == progbit */
1606                                 (etm->bcd_vers >= 0x12)
1607                                         ? ((s & (1 << 1))
1608                                                 ? "disabled" : "enabled")
1609                                         : "?",
1610                                 ((s & (1 << 3)) && etm->bcd_vers >= 0x31)
1611                                         ? " triggered" : "",
1612                                 ((s & (1 << 2)) && etm->bcd_vers >= 0x12)
1613                                         ? " start/stop" : "",
1614                                 ((s & (1 << 0)) && etm->bcd_vers >= 0x11)
1615                                         ? " untraced-overflow" : "");
1616                 } /* else ignore and try showing trace port status */
1617         }
1618
1619         /* Trace Port Driver status */
1620         trace_status = etm->capture_driver->status(etm);
1621         if (trace_status == TRACE_IDLE)
1622         {
1623                 command_print(cmd_ctx, "%s: idle", etm->capture_driver->name);
1624         }
1625         else
1626         {
1627                 static char *completed = " completed";
1628                 static char *running = " is running";
1629                 static char *overflowed = ", overflowed";
1630                 static char *triggered = ", triggered";
1631
1632                 command_print(cmd_ctx, "%s: trace collection%s%s%s",
1633                         etm->capture_driver->name,
1634                         (trace_status & TRACE_RUNNING) ? running : completed,
1635                         (trace_status & TRACE_OVERFLOWED) ? overflowed : "",
1636                         (trace_status & TRACE_TRIGGERED) ? triggered : "");
1637
1638                 if (etm->trace_depth > 0)
1639                 {
1640                         command_print(cmd_ctx, "%i frames of trace data read",
1641                                         (int)(etm->trace_depth));
1642                 }
1643         }
1644
1645         return ERROR_OK;
1646 }
1647
1648 static int handle_etm_image_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1649 {
1650         target_t *target;
1651         armv4_5_common_t *armv4_5;
1652         arm7_9_common_t *arm7_9;
1653         etm_context_t *etm_ctx;
1654
1655         if (argc < 1)
1656         {
1657                 command_print(cmd_ctx, "usage: etm image <file> [base address] [type]");
1658                 return ERROR_OK;
1659         }
1660
1661         target = get_current_target(cmd_ctx);
1662
1663         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1664         {
1665                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1666                 return ERROR_OK;
1667         }
1668
1669         if (!(etm_ctx = arm7_9->etm_ctx))
1670         {
1671                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1672                 return ERROR_OK;
1673         }
1674
1675         if (etm_ctx->image)
1676         {
1677                 image_close(etm_ctx->image);
1678                 free(etm_ctx->image);
1679                 command_print(cmd_ctx, "previously loaded image found and closed");
1680         }
1681
1682         etm_ctx->image = malloc(sizeof(image_t));
1683         etm_ctx->image->base_address_set = 0;
1684         etm_ctx->image->start_address_set = 0;
1685
1686         /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1687         if (argc >= 2)
1688         {
1689                 etm_ctx->image->base_address_set = 1;
1690                 COMMAND_PARSE_NUMBER(int, args[1], etm_ctx->image->base_address);
1691         }
1692         else
1693         {
1694                 etm_ctx->image->base_address_set = 0;
1695         }
1696
1697         if (image_open(etm_ctx->image, args[0], (argc >= 3) ? args[2] : NULL) != ERROR_OK)
1698         {
1699                 free(etm_ctx->image);
1700                 etm_ctx->image = NULL;
1701                 return ERROR_OK;
1702         }
1703
1704         return ERROR_OK;
1705 }
1706
1707 static int handle_etm_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1708 {
1709         fileio_t file;
1710         target_t *target;
1711         armv4_5_common_t *armv4_5;
1712         arm7_9_common_t *arm7_9;
1713         etm_context_t *etm_ctx;
1714         uint32_t i;
1715
1716         if (argc != 1)
1717         {
1718                 command_print(cmd_ctx, "usage: etm dump <file>");
1719                 return ERROR_OK;
1720         }
1721
1722         target = get_current_target(cmd_ctx);
1723
1724         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1725         {
1726                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1727                 return ERROR_OK;
1728         }
1729
1730         if (!(etm_ctx = arm7_9->etm_ctx))
1731         {
1732                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1733                 return ERROR_OK;
1734         }
1735
1736         if (etm_ctx->capture_driver->status == TRACE_IDLE)
1737         {
1738                 command_print(cmd_ctx, "trace capture wasn't enabled, no trace data captured");
1739                 return ERROR_OK;
1740         }
1741
1742         if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1743         {
1744                 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1745                 command_print(cmd_ctx, "trace capture not completed");
1746                 return ERROR_OK;
1747         }
1748
1749         /* read the trace data if it wasn't read already */
1750         if (etm_ctx->trace_depth == 0)
1751                 etm_ctx->capture_driver->read_trace(etm_ctx);
1752
1753         if (fileio_open(&file, args[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1754         {
1755                 return ERROR_OK;
1756         }
1757
1758         fileio_write_u32(&file, etm_ctx->capture_status);
1759         fileio_write_u32(&file, etm_ctx->portmode);
1760         fileio_write_u32(&file, etm_ctx->tracemode);
1761         fileio_write_u32(&file, etm_ctx->trace_depth);
1762
1763         for (i = 0; i < etm_ctx->trace_depth; i++)
1764         {
1765                 fileio_write_u32(&file, etm_ctx->trace_data[i].pipestat);
1766                 fileio_write_u32(&file, etm_ctx->trace_data[i].packet);
1767                 fileio_write_u32(&file, etm_ctx->trace_data[i].flags);
1768         }
1769
1770         fileio_close(&file);
1771
1772         return ERROR_OK;
1773 }
1774
1775 static int handle_etm_load_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1776 {
1777         fileio_t file;
1778         target_t *target;
1779         armv4_5_common_t *armv4_5;
1780         arm7_9_common_t *arm7_9;
1781         etm_context_t *etm_ctx;
1782         uint32_t i;
1783
1784         if (argc != 1)
1785         {
1786                 command_print(cmd_ctx, "usage: etm load <file>");
1787                 return ERROR_OK;
1788         }
1789
1790         target = get_current_target(cmd_ctx);
1791
1792         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1793         {
1794                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1795                 return ERROR_OK;
1796         }
1797
1798         if (!(etm_ctx = arm7_9->etm_ctx))
1799         {
1800                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1801                 return ERROR_OK;
1802         }
1803
1804         if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1805         {
1806                 command_print(cmd_ctx, "trace capture running, stop first");
1807                 return ERROR_OK;
1808         }
1809
1810         if (fileio_open(&file, args[0], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1811         {
1812                 return ERROR_OK;
1813         }
1814
1815         if (file.size % 4)
1816         {
1817                 command_print(cmd_ctx, "size isn't a multiple of 4, no valid trace data");
1818                 fileio_close(&file);
1819                 return ERROR_OK;
1820         }
1821
1822         if (etm_ctx->trace_depth > 0)
1823         {
1824                 free(etm_ctx->trace_data);
1825                 etm_ctx->trace_data = NULL;
1826         }
1827
1828         {
1829           uint32_t tmp;
1830           fileio_read_u32(&file, &tmp); etm_ctx->capture_status = tmp;
1831           fileio_read_u32(&file, &tmp); etm_ctx->portmode = tmp;
1832           fileio_read_u32(&file, &tmp); etm_ctx->tracemode = tmp;
1833           fileio_read_u32(&file, &etm_ctx->trace_depth);
1834         }
1835         etm_ctx->trace_data = malloc(sizeof(etmv1_trace_data_t) * etm_ctx->trace_depth);
1836         if (etm_ctx->trace_data == NULL)
1837         {
1838                 command_print(cmd_ctx, "not enough memory to perform operation");
1839                 fileio_close(&file);
1840                 return ERROR_OK;
1841         }
1842
1843         for (i = 0; i < etm_ctx->trace_depth; i++)
1844         {
1845                 uint32_t pipestat, packet, flags;
1846                 fileio_read_u32(&file, &pipestat);
1847                 fileio_read_u32(&file, &packet);
1848                 fileio_read_u32(&file, &flags);
1849                 etm_ctx->trace_data[i].pipestat = pipestat & 0xff;
1850                 etm_ctx->trace_data[i].packet = packet & 0xffff;
1851                 etm_ctx->trace_data[i].flags = flags;
1852         }
1853
1854         fileio_close(&file);
1855
1856         return ERROR_OK;
1857 }
1858
1859 static int handle_etm_trigger_percent_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1860 {
1861         target_t *target;
1862         armv4_5_common_t *armv4_5;
1863         arm7_9_common_t *arm7_9;
1864         etm_context_t *etm_ctx;
1865
1866         target = get_current_target(cmd_ctx);
1867
1868         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1869         {
1870                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1871                 return ERROR_OK;
1872         }
1873
1874         if (!(etm_ctx = arm7_9->etm_ctx))
1875         {
1876                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1877                 return ERROR_OK;
1878         }
1879
1880         if (argc > 0)
1881         {
1882                 uint32_t new_value;
1883                 COMMAND_PARSE_NUMBER(u32, args[0], new_value);
1884
1885                 if ((new_value < 2) || (new_value > 100))
1886                 {
1887                         command_print(cmd_ctx, "valid settings are 2%% to 100%%");
1888                 }
1889                 else
1890                 {
1891                         etm_ctx->trigger_percent = new_value;
1892                 }
1893         }
1894
1895         command_print(cmd_ctx, "%i percent of the tracebuffer reserved for after the trigger", ((int)(etm_ctx->trigger_percent)));
1896
1897         return ERROR_OK;
1898 }
1899
1900 static int handle_etm_start_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1901 {
1902         target_t *target;
1903         armv4_5_common_t *armv4_5;
1904         arm7_9_common_t *arm7_9;
1905         etm_context_t *etm_ctx;
1906         reg_t *etm_ctrl_reg;
1907
1908         target = get_current_target(cmd_ctx);
1909
1910         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1911         {
1912                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1913                 return ERROR_OK;
1914         }
1915
1916         if (!(etm_ctx = arm7_9->etm_ctx))
1917         {
1918                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1919                 return ERROR_OK;
1920         }
1921
1922         /* invalidate old tracing data */
1923         arm7_9->etm_ctx->capture_status = TRACE_IDLE;
1924         if (arm7_9->etm_ctx->trace_depth > 0)
1925         {
1926                 free(arm7_9->etm_ctx->trace_data);
1927                 arm7_9->etm_ctx->trace_data = NULL;
1928         }
1929         arm7_9->etm_ctx->trace_depth = 0;
1930
1931         etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
1932         if (!etm_ctrl_reg)
1933                 return ERROR_OK;
1934
1935         etm_get_reg(etm_ctrl_reg);
1936
1937         /* Clear programming bit (10), set port selection bit (11) */
1938         buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x2);
1939
1940         etm_store_reg(etm_ctrl_reg);
1941         jtag_execute_queue();
1942
1943         etm_ctx->capture_driver->start_capture(etm_ctx);
1944
1945         return ERROR_OK;
1946 }
1947
1948 static int handle_etm_stop_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1949 {
1950         target_t *target;
1951         armv4_5_common_t *armv4_5;
1952         arm7_9_common_t *arm7_9;
1953         etm_context_t *etm_ctx;
1954         reg_t *etm_ctrl_reg;
1955
1956         target = get_current_target(cmd_ctx);
1957
1958         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1959         {
1960                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1961                 return ERROR_OK;
1962         }
1963
1964         if (!(etm_ctx = arm7_9->etm_ctx))
1965         {
1966                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1967                 return ERROR_OK;
1968         }
1969
1970         etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
1971         if (!etm_ctrl_reg)
1972                 return ERROR_OK;
1973
1974         etm_get_reg(etm_ctrl_reg);
1975
1976         /* Set programming bit (10), clear port selection bit (11) */
1977         buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x1);
1978
1979         etm_store_reg(etm_ctrl_reg);
1980         jtag_execute_queue();
1981
1982         etm_ctx->capture_driver->stop_capture(etm_ctx);
1983
1984         return ERROR_OK;
1985 }
1986
1987 static int handle_etm_analyze_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1988 {
1989         target_t *target;
1990         armv4_5_common_t *armv4_5;
1991         arm7_9_common_t *arm7_9;
1992         etm_context_t *etm_ctx;
1993         int retval;
1994
1995         target = get_current_target(cmd_ctx);
1996
1997         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1998         {
1999                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2000                 return ERROR_OK;
2001         }
2002
2003         if (!(etm_ctx = arm7_9->etm_ctx))
2004         {
2005                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
2006                 return ERROR_OK;
2007         }
2008
2009         if ((retval = etmv1_analyze_trace(etm_ctx, cmd_ctx)) != ERROR_OK)
2010         {
2011                 switch (retval)
2012                 {
2013                         case ERROR_ETM_ANALYSIS_FAILED:
2014                                 command_print(cmd_ctx, "further analysis failed (corrupted trace data or just end of data");
2015                                 break;
2016                         case ERROR_TRACE_INSTRUCTION_UNAVAILABLE:
2017                                 command_print(cmd_ctx, "no instruction for current address available, analysis aborted");
2018                                 break;
2019                         case ERROR_TRACE_IMAGE_UNAVAILABLE:
2020                                 command_print(cmd_ctx, "no image available for trace analysis");
2021                                 break;
2022                         default:
2023                                 command_print(cmd_ctx, "unknown error: %i", retval);
2024                 }
2025         }
2026
2027         return ERROR_OK;
2028 }
2029
2030 int etm_register_commands(struct command_context_s *cmd_ctx)
2031 {
2032         etm_cmd = register_command(cmd_ctx, NULL, "etm", NULL, COMMAND_ANY, "Embedded Trace Macrocell");
2033
2034         register_command(cmd_ctx, etm_cmd, "config", handle_etm_config_command,
2035                 COMMAND_CONFIG, "etm config <target> <port_width> <port_mode> <clocking> <capture_driver>");
2036
2037         return ERROR_OK;
2038 }
2039
2040 static int etm_register_user_commands(struct command_context_s *cmd_ctx)
2041 {
2042         register_command(cmd_ctx, etm_cmd, "tracemode", handle_etm_tracemode_command,
2043                 COMMAND_EXEC, "configure/display trace mode: "
2044                         "<none | data | address | all> "
2045                         "<context_id_bits> <cycle_accurate> <branch_output>");
2046
2047         register_command(cmd_ctx, etm_cmd, "info", handle_etm_info_command,
2048                 COMMAND_EXEC, "display info about the current target's ETM");
2049
2050         register_command(cmd_ctx, etm_cmd, "trigger_percent", handle_etm_trigger_percent_command,
2051                 COMMAND_EXEC, "amount (<percent>) of trace buffer to be filled after the trigger occured");
2052         register_command(cmd_ctx, etm_cmd, "status", handle_etm_status_command,
2053                 COMMAND_EXEC, "display current target's ETM status");
2054         register_command(cmd_ctx, etm_cmd, "start", handle_etm_start_command,
2055                 COMMAND_EXEC, "start ETM trace collection");
2056         register_command(cmd_ctx, etm_cmd, "stop", handle_etm_stop_command,
2057                 COMMAND_EXEC, "stop ETM trace collection");
2058
2059         register_command(cmd_ctx, etm_cmd, "analyze", handle_etm_analyze_command,
2060                 COMMAND_EXEC, "anaylze collected ETM trace");
2061
2062         register_command(cmd_ctx, etm_cmd, "image", handle_etm_image_command,
2063                 COMMAND_EXEC, "load image from <file> [base address]");
2064
2065         register_command(cmd_ctx, etm_cmd, "dump", handle_etm_dump_command,
2066                 COMMAND_EXEC, "dump captured trace data <file>");
2067         register_command(cmd_ctx, etm_cmd, "load", handle_etm_load_command,
2068                 COMMAND_EXEC, "load trace data for analysis <file>");
2069
2070         return ERROR_OK;
2071 }