1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
28 #include "arm_disassembler.h"
33 * ARM "Embedded Trace Macrocell" (ETM) support -- direct JTAG access.
35 * ETM modules collect instruction and/or data trace information, compress
36 * it, and transfer it to a debugging host through either a (buffered) trace
37 * port (often a 38-pin Mictor connector) or an Embedded Trace Buffer (ETB).
39 * There are several generations of these modules. Original versions have
40 * JTAG access through a dedicated scan chain. Recent versions have added
41 * access via coprocessor instructions, memory addressing, and the ARM Debug
42 * Interface v5 (ADIv5); and phased out direct JTAG access.
44 * This code supports up to the ETMv1.3 architecture, as seen in ETM9 and
45 * most common ARM9 systems. Note: "CoreSight ETM9" implements ETMv3.2,
46 * implying non-JTAG connectivity options.
48 * Relevant documentation includes:
49 * ARM DDI 0157G ... ETM9 (r2p2) Technical Reference Manual
50 * ARM DDI 0315B ... CoreSight ETM9 (r0p1) Technical Reference Manual
51 * ARM IHI 0014O ... Embedded Trace Macrocell, Architecture Specification
62 uint8_t size; /* low-N of 32 bits */
63 uint8_t mode; /* RO, WO, RW */
64 uint8_t bcd_vers; /* 1.0, 2.0, etc */
69 * Registers 0..0x7f are JTAG-addressable using scanchain 6.
70 * (Or on some processors, through coprocessor operations.)
71 * Newer versions of ETM make some W/O registers R/W, and
72 * provide definitions for some previously-unused bits.
75 /* core registers used to version/configure the ETM */
76 static const struct etm_reg_info etm_core[] = {
77 /* NOTE: we "know" the order here ... */
78 { ETM_CONFIG, 32, RO, 0x10, "ETM_config", },
79 { ETM_ID, 32, RO, 0x20, "ETM_id", },
82 /* basic registers that are always there given the right ETM version */
83 static const struct etm_reg_info etm_basic[] = {
84 /* ETM Trace Registers */
85 { ETM_CTRL, 32, RW, 0x10, "ETM_ctrl", },
86 { ETM_TRIG_EVENT, 17, WO, 0x10, "ETM_trig_event", },
87 { ETM_ASIC_CTRL, 8, WO, 0x10, "ETM_asic_ctrl", },
88 { ETM_STATUS, 3, RO, 0x11, "ETM_status", },
89 { ETM_SYS_CONFIG, 9, RO, 0x12, "ETM_sys_config", },
91 /* TraceEnable configuration */
92 { ETM_TRACE_RESOURCE_CTRL, 32, WO, 0x12, "ETM_trace_resource_ctrl", },
93 { ETM_TRACE_EN_CTRL2, 16, WO, 0x12, "ETM_trace_en_ctrl2", },
94 { ETM_TRACE_EN_EVENT, 17, WO, 0x10, "ETM_trace_en_event", },
95 { ETM_TRACE_EN_CTRL1, 26, WO, 0x10, "ETM_trace_en_ctrl1", },
97 /* ViewData configuration (data trace) */
98 { ETM_VIEWDATA_EVENT, 17, WO, 0x10, "ETM_viewdata_event", },
99 { ETM_VIEWDATA_CTRL1, 32, WO, 0x10, "ETM_viewdata_ctrl1", },
100 { ETM_VIEWDATA_CTRL2, 32, WO, 0x10, "ETM_viewdata_ctrl2", },
101 { ETM_VIEWDATA_CTRL3, 17, WO, 0x10, "ETM_viewdata_ctrl3", },
103 /* REVISIT exclude VIEWDATA_CTRL2 when it's not there */
105 { 0x78, 12, WO, 0x20, "ETM_sync_freq", },
106 { 0x7a, 22, RO, 0x31, "ETM_config_code_ext", },
107 { 0x7b, 32, WO, 0x31, "ETM_ext_input_select", },
108 { 0x7c, 32, WO, 0x34, "ETM_trace_start_stop", },
109 { 0x7d, 8, WO, 0x34, "ETM_behavior_control", },
112 static const struct etm_reg_info etm_fifofull[] = {
113 /* FIFOFULL configuration */
114 { ETM_FIFOFULL_REGION, 25, WO, 0x10, "ETM_fifofull_region", },
115 { ETM_FIFOFULL_LEVEL, 8, WO, 0x10, "ETM_fifofull_level", },
118 static const struct etm_reg_info etm_addr_comp[] = {
119 /* Address comparator register pairs */
120 #define ADDR_COMPARATOR(i) \
121 { ETM_ADDR_COMPARATOR_VALUE + (i) - 1, 32, WO, 0x10, \
122 "ETM_addr_" #i "_comparator_value", }, \
123 { ETM_ADDR_ACCESS_TYPE + (i) - 1, 7, WO, 0x10, \
124 "ETM_addr_" #i "_access_type", }
142 #undef ADDR_COMPARATOR
145 static const struct etm_reg_info etm_data_comp[] = {
146 /* Data Value Comparators (NOTE: odd addresses are reserved) */
147 #define DATA_COMPARATOR(i) \
148 { ETM_DATA_COMPARATOR_VALUE + 2*(i) - 1, 32, WO, 0x10, \
149 "ETM_data_" #i "_comparator_value", }, \
150 { ETM_DATA_COMPARATOR_MASK + 2*(i) - 1, 32, WO, 0x10, \
151 "ETM_data_" #i "_comparator_mask", }
160 #undef DATA_COMPARATOR
163 static const struct etm_reg_info etm_counters[] = {
164 #define ETM_COUNTER(i) \
165 { ETM_COUNTER_RELOAD_VALUE + (i) - 1, 16, WO, 0x10, \
166 "ETM_counter_" #i "_reload_value", }, \
167 { ETM_COUNTER_ENABLE + (i) - 1, 18, WO, 0x10, \
168 "ETM_counter_" #i "_enable", }, \
169 { ETM_COUNTER_RELOAD_EVENT + (i) - 1, 17, WO, 0x10, \
170 "ETM_counter_" #i "_reload_event", }, \
171 { ETM_COUNTER_VALUE + (i) - 1, 16, RO, 0x10, \
172 "ETM_counter_" #i "_value", }
180 static const struct etm_reg_info etm_sequencer[] = {
182 { ETM_SEQUENCER_EVENT + (i), 17, WO, 0x10, \
183 "ETM_sequencer_event" #i, }
184 ETM_SEQ(0), /* 1->2 */
185 ETM_SEQ(1), /* 2->1 */
186 ETM_SEQ(2), /* 2->3 */
187 ETM_SEQ(3), /* 3->1 */
188 ETM_SEQ(4), /* 3->2 */
189 ETM_SEQ(5), /* 1->3 */
192 { ETM_SEQUENCER_STATE, 2, RO, 0x10, "ETM_sequencer_state", },
195 static const struct etm_reg_info etm_outputs[] = {
196 #define ETM_OUTPUT(i) \
197 { ETM_EXTERNAL_OUTPUT + (i) - 1, 17, WO, 0x10, \
198 "ETM_external_output" #i, }
208 /* registers from 0x6c..0x7f were added after ETMv1.3 */
210 /* Context ID Comparators */
211 { 0x6c, 32, RO, 0x20, "ETM_contextid_comparator_value1", }
212 { 0x6d, 32, RO, 0x20, "ETM_contextid_comparator_value2", }
213 { 0x6e, 32, RO, 0x20, "ETM_contextid_comparator_value3", }
214 { 0x6f, 32, RO, 0x20, "ETM_contextid_comparator_mask", }
217 static int etm_get_reg(struct reg *reg);
218 static int etm_read_reg_w_check(struct reg *reg,
219 uint8_t* check_value, uint8_t* check_mask);
220 static int etm_register_user_commands(struct command_context *cmd_ctx);
221 static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf);
222 static int etm_write_reg(struct reg *reg, uint32_t value);
224 static const struct reg_arch_type etm_scan6_type = {
226 .set = etm_set_reg_w_exec,
229 /* Look up register by ID ... most ETM instances only
230 * support a subset of the possible registers.
232 static struct reg *etm_reg_lookup(struct etm_context *etm_ctx, unsigned id)
234 struct reg_cache *cache = etm_ctx->reg_cache;
237 for (i = 0; i < cache->num_regs; i++) {
238 struct etm_reg *reg = cache->reg_list[i].arch_info;
240 if (reg->reg_info->addr == id)
241 return &cache->reg_list[i];
244 /* caller asking for nonexistent register is a bug! */
245 /* REVISIT say which of the N targets was involved */
246 LOG_ERROR("ETM: register 0x%02x not available", id);
250 static void etm_reg_add(unsigned bcd_vers, struct arm_jtag *jtag_info,
251 struct reg_cache *cache, struct etm_reg *ereg,
252 const struct etm_reg_info *r, unsigned nreg)
254 struct reg *reg = cache->reg_list;
256 reg += cache->num_regs;
257 ereg += cache->num_regs;
259 /* add up to "nreg" registers from "r", if supported by this
260 * version of the ETM, to the specified cache.
262 for (; nreg--; r++) {
264 /* this ETM may be too old to have some registers */
265 if (r->bcd_vers > bcd_vers)
270 reg->value = &ereg->value;
271 reg->arch_info = ereg;
272 reg->type = &etm_scan6_type;
277 ereg->jtag_info = jtag_info;
282 struct reg_cache *etm_build_reg_cache(struct target *target,
283 struct arm_jtag *jtag_info, struct etm_context *etm_ctx)
285 struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
286 struct reg *reg_list = NULL;
287 struct etm_reg *arch_info = NULL;
288 unsigned bcd_vers, config;
290 /* the actual registers are kept in two arrays */
291 reg_list = calloc(128, sizeof(struct reg));
292 arch_info = calloc(128, sizeof(struct etm_reg));
294 /* fill in values for the reg cache */
295 reg_cache->name = "etm registers";
296 reg_cache->next = NULL;
297 reg_cache->reg_list = reg_list;
298 reg_cache->num_regs = 0;
300 /* add ETM_CONFIG, then parse its values to see
301 * which other registers exist in this ETM
303 etm_reg_add(0x10, jtag_info, reg_cache, arch_info,
306 etm_get_reg(reg_list);
307 etm_ctx->config = buf_get_u32((void *)&arch_info->value, 0, 32);
308 config = etm_ctx->config;
310 /* figure ETM version then add base registers */
311 if (config & (1 << 31)) {
313 LOG_WARNING("ETMv2+ support is incomplete");
315 /* REVISIT more registers may exist; they may now be
316 * readable; more register bits have defined meanings;
317 * don't presume trace start/stop support is present;
318 * and include any context ID comparator registers.
320 etm_reg_add(0x20, jtag_info, reg_cache, arch_info,
322 etm_get_reg(reg_list + 1);
323 etm_ctx->id = buf_get_u32(
324 (void *)&arch_info[1].value, 0, 32);
325 LOG_DEBUG("ETM ID: %08x", (unsigned) etm_ctx->id);
326 bcd_vers = 0x10 + (((etm_ctx->id) >> 4) & 0xff);
329 switch (config >> 28) {
346 LOG_WARNING("Bad ETMv1 protocol %d", config >> 28);
350 etm_ctx->bcd_vers = bcd_vers;
351 LOG_INFO("ETM v%d.%d", bcd_vers >> 4, bcd_vers & 0xf);
353 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
354 etm_basic, ARRAY_SIZE(etm_basic));
356 /* address and data comparators; counters; outputs */
357 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
358 etm_addr_comp, 4 * (0x0f & (config >> 0)));
359 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
360 etm_data_comp, 2 * (0x0f & (config >> 4)));
361 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
362 etm_counters, 4 * (0x07 & (config >> 13)));
363 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
364 etm_outputs, (0x07 & (config >> 20)));
366 /* FIFOFULL presence is optional
367 * REVISIT for ETMv1.2 and later, don't bother adding this
368 * unless ETM_SYS_CONFIG says it's also *supported* ...
370 if (config & (1 << 23))
371 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
372 etm_fifofull, ARRAY_SIZE(etm_fifofull));
374 /* sequencer is optional (for state-dependant triggering) */
375 if (config & (1 << 16))
376 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
377 etm_sequencer, ARRAY_SIZE(etm_sequencer));
379 /* REVISIT could realloc and likely save half the memory
380 * in the two chunks we allocated...
383 /* the ETM might have an ETB connected */
384 if (strcmp(etm_ctx->capture_driver->name, "etb") == 0)
386 struct etb *etb = etm_ctx->capture_driver_priv;
390 LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
394 reg_cache->next = etb_build_reg_cache(etb);
396 etb->reg_cache = reg_cache->next;
399 etm_ctx->reg_cache = reg_cache;
409 static int etm_read_reg(struct reg *reg)
411 return etm_read_reg_w_check(reg, NULL, NULL);
414 static int etm_store_reg(struct reg *reg)
416 return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
419 int etm_setup(struct target *target)
422 uint32_t etm_ctrl_value;
423 struct arm *arm = target_to_arm(target);
424 struct etm_context *etm_ctx = arm->etm;
425 struct reg *etm_ctrl_reg;
427 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
431 /* initialize some ETM control register settings */
432 etm_get_reg(etm_ctrl_reg);
433 etm_ctrl_value = buf_get_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size);
435 /* clear the ETM powerdown bit (0) */
436 etm_ctrl_value &= ~0x1;
438 /* configure port width (21,6:4), mode (13,17:16) and
439 * for older modules clocking (13)
441 etm_ctrl_value = (etm_ctrl_value
442 & ~ETM_PORT_WIDTH_MASK
443 & ~ETM_PORT_MODE_MASK
444 & ~ETM_PORT_CLOCK_MASK)
447 buf_set_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size, etm_ctrl_value);
448 etm_store_reg(etm_ctrl_reg);
450 if ((retval = jtag_execute_queue()) != ERROR_OK)
453 /* REVISIT for ETMv3.0 and later, read ETM_sys_config to
454 * verify that those width and mode settings are OK ...
457 if ((retval = etm_ctx->capture_driver->init(etm_ctx)) != ERROR_OK)
459 LOG_ERROR("ETM capture driver initialization failed");
465 static int etm_get_reg(struct reg *reg)
469 if ((retval = etm_read_reg(reg)) != ERROR_OK)
471 LOG_ERROR("BUG: error scheduling etm register read");
475 if ((retval = jtag_execute_queue()) != ERROR_OK)
477 LOG_ERROR("register read failed");
484 static int etm_read_reg_w_check(struct reg *reg,
485 uint8_t* check_value, uint8_t* check_mask)
487 struct etm_reg *etm_reg = reg->arch_info;
488 const struct etm_reg_info *r = etm_reg->reg_info;
489 uint8_t reg_addr = r->addr & 0x7f;
490 struct scan_field fields[3];
492 if (etm_reg->reg_info->mode == WO) {
493 LOG_ERROR("BUG: can't read write-only register %s", r->name);
494 return ERROR_INVALID_ARGUMENTS;
497 LOG_DEBUG("%s (%u)", r->name, reg_addr);
499 jtag_set_end_state(TAP_IDLE);
500 arm_jtag_scann(etm_reg->jtag_info, 0x6);
501 arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
503 fields[0].tap = etm_reg->jtag_info->tap;
504 fields[0].num_bits = 32;
505 fields[0].out_value = reg->value;
506 fields[0].in_value = NULL;
507 fields[0].check_value = NULL;
508 fields[0].check_mask = NULL;
510 fields[1].tap = etm_reg->jtag_info->tap;
511 fields[1].num_bits = 7;
512 fields[1].out_value = malloc(1);
513 buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
514 fields[1].in_value = NULL;
515 fields[1].check_value = NULL;
516 fields[1].check_mask = NULL;
518 fields[2].tap = etm_reg->jtag_info->tap;
519 fields[2].num_bits = 1;
520 fields[2].out_value = malloc(1);
521 buf_set_u32(fields[2].out_value, 0, 1, 0);
522 fields[2].in_value = NULL;
523 fields[2].check_value = NULL;
524 fields[2].check_mask = NULL;
526 jtag_add_dr_scan(3, fields, jtag_get_end_state());
528 fields[0].in_value = reg->value;
529 fields[0].check_value = check_value;
530 fields[0].check_mask = check_mask;
532 jtag_add_dr_scan_check(3, fields, jtag_get_end_state());
534 free(fields[1].out_value);
535 free(fields[2].out_value);
540 static int etm_set_reg(struct reg *reg, uint32_t value)
544 if ((retval = etm_write_reg(reg, value)) != ERROR_OK)
546 LOG_ERROR("BUG: error scheduling etm register write");
550 buf_set_u32(reg->value, 0, reg->size, value);
557 static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf)
561 etm_set_reg(reg, buf_get_u32(buf, 0, reg->size));
563 if ((retval = jtag_execute_queue()) != ERROR_OK)
565 LOG_ERROR("register write failed");
571 static int etm_write_reg(struct reg *reg, uint32_t value)
573 struct etm_reg *etm_reg = reg->arch_info;
574 const struct etm_reg_info *r = etm_reg->reg_info;
575 uint8_t reg_addr = r->addr & 0x7f;
576 struct scan_field fields[3];
578 if (etm_reg->reg_info->mode == RO) {
579 LOG_ERROR("BUG: can't write read--only register %s", r->name);
580 return ERROR_INVALID_ARGUMENTS;
583 LOG_DEBUG("%s (%u): 0x%8.8" PRIx32 "", r->name, reg_addr, value);
585 jtag_set_end_state(TAP_IDLE);
586 arm_jtag_scann(etm_reg->jtag_info, 0x6);
587 arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
589 fields[0].tap = etm_reg->jtag_info->tap;
590 fields[0].num_bits = 32;
592 fields[0].out_value = tmp1;
593 buf_set_u32(fields[0].out_value, 0, 32, value);
594 fields[0].in_value = NULL;
596 fields[1].tap = etm_reg->jtag_info->tap;
597 fields[1].num_bits = 7;
599 fields[1].out_value = &tmp2;
600 buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
601 fields[1].in_value = NULL;
603 fields[2].tap = etm_reg->jtag_info->tap;
604 fields[2].num_bits = 1;
606 fields[2].out_value = &tmp3;
607 buf_set_u32(fields[2].out_value, 0, 1, 1);
608 fields[2].in_value = NULL;
610 jtag_add_dr_scan(3, fields, jtag_get_end_state());
616 /* ETM trace analysis functionality
619 extern struct etm_capture_driver etm_dummy_capture_driver;
620 #if BUILD_OOCD_TRACE == 1
621 extern struct etm_capture_driver oocd_trace_capture_driver;
624 static struct etm_capture_driver *etm_capture_drivers[] =
627 &etm_dummy_capture_driver,
628 #if BUILD_OOCD_TRACE == 1
629 &oocd_trace_capture_driver,
634 static int etm_read_instruction(struct etm_context *ctx, struct arm_instruction *instruction)
643 return ERROR_TRACE_IMAGE_UNAVAILABLE;
645 /* search for the section the current instruction belongs to */
646 for (i = 0; i < ctx->image->num_sections; i++)
648 if ((ctx->image->sections[i].base_address <= ctx->current_pc) &&
649 (ctx->image->sections[i].base_address + ctx->image->sections[i].size > ctx->current_pc))
658 /* current instruction couldn't be found in the image */
659 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
662 if (ctx->core_state == ARMV4_5_STATE_ARM)
665 if ((retval = image_read_section(ctx->image, section,
666 ctx->current_pc - ctx->image->sections[section].base_address,
667 4, buf, &size_read)) != ERROR_OK)
669 LOG_ERROR("error while reading instruction: %i", retval);
670 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
672 opcode = target_buffer_get_u32(ctx->target, buf);
673 arm_evaluate_opcode(opcode, ctx->current_pc, instruction);
675 else if (ctx->core_state == ARMV4_5_STATE_THUMB)
678 if ((retval = image_read_section(ctx->image, section,
679 ctx->current_pc - ctx->image->sections[section].base_address,
680 2, buf, &size_read)) != ERROR_OK)
682 LOG_ERROR("error while reading instruction: %i", retval);
683 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
685 opcode = target_buffer_get_u16(ctx->target, buf);
686 thumb_evaluate_opcode(opcode, ctx->current_pc, instruction);
688 else if (ctx->core_state == ARMV4_5_STATE_JAZELLE)
690 LOG_ERROR("BUG: tracing of jazelle code not supported");
695 LOG_ERROR("BUG: unknown core state encountered");
702 static int etmv1_next_packet(struct etm_context *ctx, uint8_t *packet, int apo)
704 while (ctx->data_index < ctx->trace_depth)
706 /* if the caller specified an address packet offset, skip until the
707 * we reach the n-th cycle marked with tracesync */
710 if (ctx->trace_data[ctx->data_index].flags & ETMV1_TRACESYNC_CYCLE)
721 /* no tracedata output during a TD cycle
722 * or in a trigger cycle */
723 if ((ctx->trace_data[ctx->data_index].pipestat == STAT_TD)
724 || (ctx->trace_data[ctx->data_index].flags & ETMV1_TRIGGER_CYCLE))
731 if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_16BIT)
733 if (ctx->data_half == 0)
735 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
740 *packet = (ctx->trace_data[ctx->data_index].packet & 0xff00) >> 8;
745 else if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
747 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
752 /* on a 4-bit port, a packet will be output during two consecutive cycles */
753 if (ctx->data_index > (ctx->trace_depth - 2))
756 *packet = ctx->trace_data[ctx->data_index].packet & 0xf;
757 *packet |= (ctx->trace_data[ctx->data_index + 1].packet & 0xf) << 4;
758 ctx->data_index += 2;
767 static int etmv1_branch_address(struct etm_context *ctx)
775 /* quit analysis if less than two cycles are left in the trace
776 * because we can't extract the APO */
777 if (ctx->data_index > (ctx->trace_depth - 2))
780 /* a BE could be output during an APO cycle, skip the current
781 * and continue with the new one */
782 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x4)
784 if (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x4)
787 /* address packet offset encoded in the next two cycles' pipestat bits */
788 apo = ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x3;
789 apo |= (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x3) << 2;
791 /* count number of tracesync cycles between current pipe_index and data_index
792 * i.e. the number of tracesyncs that data_index already passed by
793 * to subtract them from the APO */
794 for (i = ctx->pipe_index; i < ctx->data_index; i++)
796 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & ETMV1_TRACESYNC_CYCLE)
800 /* extract up to four 7-bit packets */
802 if ((retval = etmv1_next_packet(ctx, &packet, (shift == 0) ? apo + 1 : 0)) != 0)
804 ctx->last_branch &= ~(0x7f << shift);
805 ctx->last_branch |= (packet & 0x7f) << shift;
807 } while ((packet & 0x80) && (shift < 28));
809 /* one last packet holding 4 bits of the address, plus the branch reason code */
810 if ((shift == 28) && (packet & 0x80))
812 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
814 ctx->last_branch &= 0x0fffffff;
815 ctx->last_branch |= (packet & 0x0f) << 28;
816 ctx->last_branch_reason = (packet & 0x70) >> 4;
821 ctx->last_branch_reason = 0;
829 /* if a full address was output, we might have branched into Jazelle state */
830 if ((shift == 32) && (packet & 0x80))
832 ctx->core_state = ARMV4_5_STATE_JAZELLE;
836 /* if we didn't branch into Jazelle state, the current processor state is
837 * encoded in bit 0 of the branch target address */
838 if (ctx->last_branch & 0x1)
840 ctx->core_state = ARMV4_5_STATE_THUMB;
841 ctx->last_branch &= ~0x1;
845 ctx->core_state = ARMV4_5_STATE_ARM;
846 ctx->last_branch &= ~0x3;
853 static int etmv1_data(struct etm_context *ctx, int size, uint32_t *data)
859 for (j = 0; j < size; j++)
861 if ((retval = etmv1_next_packet(ctx, &buf[j], 0)) != 0)
867 LOG_ERROR("TODO: add support for 64-bit values");
871 *data = target_buffer_get_u32(ctx->target, buf);
873 *data = target_buffer_get_u16(ctx->target, buf);
882 static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context *cmd_ctx)
885 struct arm_instruction instruction;
887 /* read the trace data if it wasn't read already */
888 if (ctx->trace_depth == 0)
889 ctx->capture_driver->read_trace(ctx);
891 /* start at the beginning of the captured trace */
896 /* neither the PC nor the data pointer are valid */
900 while (ctx->pipe_index < ctx->trace_depth)
902 uint8_t pipestat = ctx->trace_data[ctx->pipe_index].pipestat;
903 uint32_t next_pc = ctx->current_pc;
904 uint32_t old_data_index = ctx->data_index;
905 uint32_t old_data_half = ctx->data_half;
906 uint32_t old_index = ctx->pipe_index;
907 uint32_t last_instruction = ctx->last_instruction;
909 int current_pc_ok = ctx->pc_ok;
911 if (ctx->trace_data[ctx->pipe_index].flags & ETMV1_TRIGGER_CYCLE)
913 command_print(cmd_ctx, "--- trigger ---");
916 /* instructions execute in IE/D or BE/D cycles */
917 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
918 ctx->last_instruction = ctx->pipe_index;
920 /* if we don't have a valid pc skip until we reach an indirect branch */
921 if ((!ctx->pc_ok) && (pipestat != STAT_BE))
927 /* any indirect branch could have interrupted instruction flow
928 * - the branch reason code could indicate a trace discontinuity
929 * - a branch to the exception vectors indicates an exception
931 if ((pipestat == STAT_BE) || (pipestat == STAT_BD))
933 /* backup current data index, to be able to consume the branch address
934 * before examining data address and values
936 old_data_index = ctx->data_index;
937 old_data_half = ctx->data_half;
939 ctx->last_instruction = ctx->pipe_index;
941 if ((retval = etmv1_branch_address(ctx)) != 0)
943 /* negative return value from etmv1_branch_address means we ran out of packets,
944 * quit analysing the trace */
948 /* a positive return values means the current branch was abandoned,
949 * and a new branch was encountered in cycle ctx->pipe_index + retval;
951 LOG_WARNING("abandoned branch encountered, correctnes of analysis uncertain");
952 ctx->pipe_index += retval;
956 /* skip over APO cycles */
957 ctx->pipe_index += 2;
959 switch (ctx->last_branch_reason)
961 case 0x0: /* normal PC change */
962 next_pc = ctx->last_branch;
964 case 0x1: /* tracing enabled */
965 command_print(cmd_ctx, "--- tracing enabled at 0x%8.8" PRIx32 " ---", ctx->last_branch);
966 ctx->current_pc = ctx->last_branch;
970 case 0x2: /* trace restarted after FIFO overflow */
971 command_print(cmd_ctx, "--- trace restarted after FIFO overflow at 0x%8.8" PRIx32 " ---", ctx->last_branch);
972 ctx->current_pc = ctx->last_branch;
976 case 0x3: /* exit from debug state */
977 command_print(cmd_ctx, "--- exit from debug state at 0x%8.8" PRIx32 " ---", ctx->last_branch);
978 ctx->current_pc = ctx->last_branch;
982 case 0x4: /* periodic synchronization point */
983 next_pc = ctx->last_branch;
984 /* if we had no valid PC prior to this synchronization point,
985 * we have to move on with the next trace cycle
989 command_print(cmd_ctx, "--- periodic synchronization point at 0x%8.8" PRIx32 " ---", next_pc);
990 ctx->current_pc = next_pc;
995 default: /* reserved */
996 LOG_ERROR("BUG: branch reason code 0x%" PRIx32 " is reserved", ctx->last_branch_reason);
1000 /* if we got here the branch was a normal PC change
1001 * (or a periodic synchronization point, which means the same for that matter)
1002 * if we didn't accquire a complete PC continue with the next cycle
1007 /* indirect branch to the exception vector means an exception occured */
1008 if ((ctx->last_branch <= 0x20)
1009 || ((ctx->last_branch >= 0xffff0000) && (ctx->last_branch <= 0xffff0020)))
1011 if ((ctx->last_branch & 0xff) == 0x10)
1013 command_print(cmd_ctx, "data abort");
1017 command_print(cmd_ctx, "exception vector 0x%2.2" PRIx32 "", ctx->last_branch);
1018 ctx->current_pc = ctx->last_branch;
1025 /* an instruction was executed (or not, depending on the condition flags)
1026 * retrieve it from the image for displaying */
1027 if (ctx->pc_ok && (pipestat != STAT_WT) && (pipestat != STAT_TD) &&
1028 !(((pipestat == STAT_BE) || (pipestat == STAT_BD)) &&
1029 ((ctx->last_branch_reason != 0x0) && (ctx->last_branch_reason != 0x4))))
1031 if ((retval = etm_read_instruction(ctx, &instruction)) != ERROR_OK)
1033 /* can't continue tracing with no image available */
1034 if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
1038 else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE)
1040 /* TODO: handle incomplete images
1041 * for now we just quit the analsysis*/
1046 cycles = old_index - last_instruction;
1049 if ((pipestat == STAT_ID) || (pipestat == STAT_BD))
1051 uint32_t new_data_index = ctx->data_index;
1052 uint32_t new_data_half = ctx->data_half;
1054 /* in case of a branch with data, the branch target address was consumed before
1055 * we temporarily go back to the saved data index */
1056 if (pipestat == STAT_BD)
1058 ctx->data_index = old_data_index;
1059 ctx->data_half = old_data_half;
1062 if (ctx->tracemode & ETMV1_TRACE_ADDR)
1068 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
1069 return ERROR_ETM_ANALYSIS_FAILED;
1070 ctx->last_ptr &= ~(0x7f << shift);
1071 ctx->last_ptr |= (packet & 0x7f) << shift;
1073 } while ((packet & 0x80) && (shift < 32));
1080 command_print(cmd_ctx, "address: 0x%8.8" PRIx32 "", ctx->last_ptr);
1084 if (ctx->tracemode & ETMV1_TRACE_DATA)
1086 if ((instruction.type == ARM_LDM) || (instruction.type == ARM_STM))
1089 for (i = 0; i < 16; i++)
1091 if (instruction.info.load_store_multiple.register_list & (1 << i))
1094 if (etmv1_data(ctx, 4, &data) != 0)
1095 return ERROR_ETM_ANALYSIS_FAILED;
1096 command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
1100 else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_STRH))
1103 if (etmv1_data(ctx, arm_access_size(&instruction), &data) != 0)
1104 return ERROR_ETM_ANALYSIS_FAILED;
1105 command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
1109 /* restore data index after consuming BD address and data */
1110 if (pipestat == STAT_BD)
1112 ctx->data_index = new_data_index;
1113 ctx->data_half = new_data_half;
1118 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
1120 if (((instruction.type == ARM_B) ||
1121 (instruction.type == ARM_BL) ||
1122 (instruction.type == ARM_BLX)) &&
1123 (instruction.info.b_bl_bx_blx.target_address != 0xffffffff))
1125 next_pc = instruction.info.b_bl_bx_blx.target_address;
1129 next_pc += (ctx->core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
1132 else if (pipestat == STAT_IN)
1134 next_pc += (ctx->core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
1137 if ((pipestat != STAT_TD) && (pipestat != STAT_WT))
1139 char cycles_text[32] = "";
1141 /* if the trace was captured with cycle accurate tracing enabled,
1142 * output the number of cycles since the last executed instruction
1144 if (ctx->tracemode & ETMV1_CYCLE_ACCURATE)
1146 snprintf(cycles_text, 32, " (%i %s)",
1148 (cycles == 1) ? "cycle" : "cycles");
1151 command_print(cmd_ctx, "%s%s%s",
1153 (pipestat == STAT_IN) ? " (not executed)" : "",
1156 ctx->current_pc = next_pc;
1158 /* packets for an instruction don't start on or before the preceding
1159 * functional pipestat (i.e. other than WT or TD)
1161 if (ctx->data_index <= ctx->pipe_index)
1163 ctx->data_index = ctx->pipe_index + 1;
1168 ctx->pipe_index += 1;
1174 static COMMAND_HELPER(handle_etm_tracemode_command_update,
1175 etmv1_tracemode_t *mode)
1177 etmv1_tracemode_t tracemode;
1179 /* what parts of data access are traced? */
1180 if (strcmp(CMD_ARGV[0], "none") == 0)
1181 tracemode = ETMV1_TRACE_NONE;
1182 else if (strcmp(CMD_ARGV[0], "data") == 0)
1183 tracemode = ETMV1_TRACE_DATA;
1184 else if (strcmp(CMD_ARGV[0], "address") == 0)
1185 tracemode = ETMV1_TRACE_ADDR;
1186 else if (strcmp(CMD_ARGV[0], "all") == 0)
1187 tracemode = ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR;
1190 command_print(CMD_CTX, "invalid option '%s'", CMD_ARGV[0]);
1191 return ERROR_INVALID_ARGUMENTS;
1195 COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], context_id);
1199 tracemode |= ETMV1_CONTEXTID_NONE;
1202 tracemode |= ETMV1_CONTEXTID_8;
1205 tracemode |= ETMV1_CONTEXTID_16;
1208 tracemode |= ETMV1_CONTEXTID_32;
1211 command_print(CMD_CTX, "invalid option '%s'", CMD_ARGV[1]);
1212 return ERROR_INVALID_ARGUMENTS;
1215 bool etmv1_cycle_accurate;
1216 COMMAND_PARSE_ENABLE(CMD_ARGV[2], etmv1_cycle_accurate);
1217 if (etmv1_cycle_accurate)
1218 tracemode |= ETMV1_CYCLE_ACCURATE;
1220 bool etmv1_branch_output;
1221 COMMAND_PARSE_ENABLE(CMD_ARGV[3], etmv1_branch_output);
1222 tracemode |= ETMV1_BRANCH_OUTPUT;
1225 * - CPRT tracing (coprocessor register transfers)
1226 * - debug request (causes debug entry on trigger)
1227 * - stall on FIFOFULL (preventing tracedata lossage)
1234 COMMAND_HANDLER(handle_etm_tracemode_command)
1236 struct target *target = get_current_target(CMD_CTX);
1237 struct arm *arm = target_to_arm(target);
1238 struct etm_context *etm;
1241 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1247 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1251 etmv1_tracemode_t tracemode = etm->tracemode;
1258 CALL_COMMAND_HANDLER(handle_etm_tracemode_command_update, &tracemode);
1261 command_print(CMD_CTX, "usage: configure trace mode "
1262 "<none | data | address | all> "
1263 "<context id bits> <cycle accurate> <branch output>");
1268 * todo: fail if parameters were invalid for this hardware,
1269 * or couldn't be written; display actual hardware state...
1272 command_print(CMD_CTX, "current tracemode configuration:");
1274 switch (tracemode & ETMV1_TRACE_MASK)
1276 case ETMV1_TRACE_NONE:
1277 command_print(CMD_CTX, "data tracing: none");
1279 case ETMV1_TRACE_DATA:
1280 command_print(CMD_CTX, "data tracing: data only");
1282 case ETMV1_TRACE_ADDR:
1283 command_print(CMD_CTX, "data tracing: address only");
1285 case ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR:
1286 command_print(CMD_CTX, "data tracing: address and data");
1290 switch (tracemode & ETMV1_CONTEXTID_MASK)
1292 case ETMV1_CONTEXTID_NONE:
1293 command_print(CMD_CTX, "contextid tracing: none");
1295 case ETMV1_CONTEXTID_8:
1296 command_print(CMD_CTX, "contextid tracing: 8 bit");
1298 case ETMV1_CONTEXTID_16:
1299 command_print(CMD_CTX, "contextid tracing: 16 bit");
1301 case ETMV1_CONTEXTID_32:
1302 command_print(CMD_CTX, "contextid tracing: 32 bit");
1306 if (tracemode & ETMV1_CYCLE_ACCURATE)
1308 command_print(CMD_CTX, "cycle-accurate tracing enabled");
1312 command_print(CMD_CTX, "cycle-accurate tracing disabled");
1315 if (tracemode & ETMV1_BRANCH_OUTPUT)
1317 command_print(CMD_CTX, "full branch address output enabled");
1321 command_print(CMD_CTX, "full branch address output disabled");
1324 /* only update ETM_CTRL register if tracemode changed */
1325 if (etm->tracemode != tracemode)
1327 struct reg *etm_ctrl_reg;
1329 etm_ctrl_reg = etm_reg_lookup(etm, ETM_CTRL);
1333 etm_get_reg(etm_ctrl_reg);
1335 buf_set_u32(etm_ctrl_reg->value, 2, 2, tracemode & ETMV1_TRACE_MASK);
1336 buf_set_u32(etm_ctrl_reg->value, 14, 2, (tracemode & ETMV1_CONTEXTID_MASK) >> 4);
1337 buf_set_u32(etm_ctrl_reg->value, 12, 1, (tracemode & ETMV1_CYCLE_ACCURATE) >> 8);
1338 buf_set_u32(etm_ctrl_reg->value, 8, 1, (tracemode & ETMV1_BRANCH_OUTPUT) >> 9);
1339 etm_store_reg(etm_ctrl_reg);
1341 etm->tracemode = tracemode;
1343 /* invalidate old trace data */
1344 etm->capture_status = TRACE_IDLE;
1345 if (etm->trace_depth > 0)
1347 free(etm->trace_data);
1348 etm->trace_data = NULL;
1350 etm->trace_depth = 0;
1356 COMMAND_HANDLER(handle_etm_config_command)
1358 struct target *target;
1360 etm_portmode_t portmode = 0x0;
1361 struct etm_context *etm_ctx;
1365 return ERROR_COMMAND_SYNTAX_ERROR;
1367 target = get_target(CMD_ARGV[0]);
1370 LOG_ERROR("target '%s' not defined", CMD_ARGV[0]);
1374 arm = target_to_arm(target);
1376 command_print(CMD_CTX, "target '%s' is '%s'; not an ARM",
1377 target->cmd_name, target_get_name(target));
1381 /* FIXME for ETMv3.0 and above -- and we don't yet know what ETM
1382 * version we'll be using!! -- so we can't know how to validate
1383 * params yet. "etm config" should likely be *AFTER* hookup...
1385 * - Many more widths might be supported ... and we can easily
1386 * check whether our setting "took".
1388 * - The "clock" and "mode" bits are interpreted differently.
1389 * See ARM IHI 0014O table 2-17 for the old behavior, and
1390 * table 2-18 for the new. With ETB it's best to specify
1394 COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], port_width);
1397 /* before ETMv3.0 */
1399 portmode |= ETM_PORT_4BIT;
1402 portmode |= ETM_PORT_8BIT;
1405 portmode |= ETM_PORT_16BIT;
1407 /* ETMv3.0 and later*/
1409 portmode |= ETM_PORT_24BIT;
1412 portmode |= ETM_PORT_32BIT;
1415 portmode |= ETM_PORT_48BIT;
1418 portmode |= ETM_PORT_64BIT;
1421 portmode |= ETM_PORT_1BIT;
1424 portmode |= ETM_PORT_2BIT;
1427 command_print(CMD_CTX,
1428 "unsupported ETM port width '%s'", CMD_ARGV[1]);
1432 if (strcmp("normal", CMD_ARGV[2]) == 0)
1434 portmode |= ETM_PORT_NORMAL;
1436 else if (strcmp("multiplexed", CMD_ARGV[2]) == 0)
1438 portmode |= ETM_PORT_MUXED;
1440 else if (strcmp("demultiplexed", CMD_ARGV[2]) == 0)
1442 portmode |= ETM_PORT_DEMUXED;
1446 command_print(CMD_CTX, "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", CMD_ARGV[2]);
1450 if (strcmp("half", CMD_ARGV[3]) == 0)
1452 portmode |= ETM_PORT_HALF_CLOCK;
1454 else if (strcmp("full", CMD_ARGV[3]) == 0)
1456 portmode |= ETM_PORT_FULL_CLOCK;
1460 command_print(CMD_CTX, "unsupported ETM port clocking '%s', must be 'full' or 'half'", CMD_ARGV[3]);
1464 etm_ctx = calloc(1, sizeof(struct etm_context));
1466 LOG_DEBUG("out of memory");
1470 for (i = 0; etm_capture_drivers[i]; i++)
1472 if (strcmp(CMD_ARGV[4], etm_capture_drivers[i]->name) == 0)
1475 if ((retval = etm_capture_drivers[i]->register_commands(CMD_CTX)) != ERROR_OK)
1481 etm_ctx->capture_driver = etm_capture_drivers[i];
1487 if (!etm_capture_drivers[i])
1489 /* no supported capture driver found, don't register an ETM */
1491 LOG_ERROR("trace capture driver '%s' not found", CMD_ARGV[4]);
1495 etm_ctx->target = target;
1496 etm_ctx->trigger_percent = 50;
1497 etm_ctx->trace_data = NULL;
1498 etm_ctx->portmode = portmode;
1499 etm_ctx->core_state = ARMV4_5_STATE_ARM;
1503 return etm_register_user_commands(CMD_CTX);
1506 COMMAND_HANDLER(handle_etm_info_command)
1508 struct target *target;
1510 struct etm_context *etm;
1511 struct reg *etm_sys_config_reg;
1515 target = get_current_target(CMD_CTX);
1516 arm = target_to_arm(target);
1519 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1526 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1530 command_print(CMD_CTX, "ETM v%d.%d",
1531 etm->bcd_vers >> 4, etm->bcd_vers & 0xf);
1532 command_print(CMD_CTX, "pairs of address comparators: %i",
1533 (int) (etm->config >> 0) & 0x0f);
1534 command_print(CMD_CTX, "data comparators: %i",
1535 (int) (etm->config >> 4) & 0x0f);
1536 command_print(CMD_CTX, "memory map decoders: %i",
1537 (int) (etm->config >> 8) & 0x1f);
1538 command_print(CMD_CTX, "number of counters: %i",
1539 (int) (etm->config >> 13) & 0x07);
1540 command_print(CMD_CTX, "sequencer %spresent",
1541 (int) (etm->config & (1 << 16)) ? "" : "not ");
1542 command_print(CMD_CTX, "number of ext. inputs: %i",
1543 (int) (etm->config >> 17) & 0x07);
1544 command_print(CMD_CTX, "number of ext. outputs: %i",
1545 (int) (etm->config >> 20) & 0x07);
1546 command_print(CMD_CTX, "FIFO full %spresent",
1547 (int) (etm->config & (1 << 23)) ? "" : "not ");
1548 if (etm->bcd_vers < 0x20)
1549 command_print(CMD_CTX, "protocol version: %i",
1550 (int) (etm->config >> 28) & 0x07);
1552 command_print(CMD_CTX,
1553 "coprocessor and memory access %ssupported",
1554 (etm->config & (1 << 26)) ? "" : "not ");
1555 command_print(CMD_CTX, "trace start/stop %spresent",
1556 (etm->config & (1 << 26)) ? "" : "not ");
1557 command_print(CMD_CTX, "number of context comparators: %i",
1558 (int) (etm->config >> 24) & 0x03);
1561 /* SYS_CONFIG isn't present before ETMv1.2 */
1562 etm_sys_config_reg = etm_reg_lookup(etm, ETM_SYS_CONFIG);
1563 if (!etm_sys_config_reg)
1566 etm_get_reg(etm_sys_config_reg);
1567 config = buf_get_u32(etm_sys_config_reg->value, 0, 32);
1569 LOG_DEBUG("ETM SYS CONFIG %08x", (unsigned) config);
1571 max_port_size = config & 0x7;
1572 if (etm->bcd_vers >= 0x30)
1573 max_port_size |= (config >> 6) & 0x08;
1574 switch (max_port_size)
1576 /* before ETMv3.0 */
1586 /* ETMv3.0 and later*/
1606 LOG_ERROR("Illegal max_port_size");
1609 command_print(CMD_CTX, "max. port size: %i", max_port_size);
1611 if (etm->bcd_vers < 0x30) {
1612 command_print(CMD_CTX, "half-rate clocking %ssupported",
1613 (config & (1 << 3)) ? "" : "not ");
1614 command_print(CMD_CTX, "full-rate clocking %ssupported",
1615 (config & (1 << 4)) ? "" : "not ");
1616 command_print(CMD_CTX, "normal trace format %ssupported",
1617 (config & (1 << 5)) ? "" : "not ");
1618 command_print(CMD_CTX, "multiplex trace format %ssupported",
1619 (config & (1 << 6)) ? "" : "not ");
1620 command_print(CMD_CTX, "demultiplex trace format %ssupported",
1621 (config & (1 << 7)) ? "" : "not ");
1623 /* REVISIT show which size and format are selected ... */
1624 command_print(CMD_CTX, "current port size %ssupported",
1625 (config & (1 << 10)) ? "" : "not ");
1626 command_print(CMD_CTX, "current trace format %ssupported",
1627 (config & (1 << 11)) ? "" : "not ");
1629 if (etm->bcd_vers >= 0x21)
1630 command_print(CMD_CTX, "fetch comparisons %ssupported",
1631 (config & (1 << 17)) ? "not " : "");
1632 command_print(CMD_CTX, "FIFO full %ssupported",
1633 (config & (1 << 8)) ? "" : "not ");
1638 COMMAND_HANDLER(handle_etm_status_command)
1640 struct target *target;
1642 struct etm_context *etm;
1643 trace_status_t trace_status;
1645 target = get_current_target(CMD_CTX);
1646 arm = target_to_arm(target);
1649 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1656 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1661 if (etm->bcd_vers >= 0x11) {
1664 reg = etm_reg_lookup(etm, ETM_STATUS);
1667 if (etm_get_reg(reg) == ERROR_OK) {
1668 unsigned s = buf_get_u32(reg->value, 0, reg->size);
1670 command_print(CMD_CTX, "etm: %s%s%s%s",
1671 /* bit(1) == progbit */
1672 (etm->bcd_vers >= 0x12)
1674 ? "disabled" : "enabled")
1676 ((s & (1 << 3)) && etm->bcd_vers >= 0x31)
1677 ? " triggered" : "",
1678 ((s & (1 << 2)) && etm->bcd_vers >= 0x12)
1679 ? " start/stop" : "",
1680 ((s & (1 << 0)) && etm->bcd_vers >= 0x11)
1681 ? " untraced-overflow" : "");
1682 } /* else ignore and try showing trace port status */
1685 /* Trace Port Driver status */
1686 trace_status = etm->capture_driver->status(etm);
1687 if (trace_status == TRACE_IDLE)
1689 command_print(CMD_CTX, "%s: idle", etm->capture_driver->name);
1693 static char *completed = " completed";
1694 static char *running = " is running";
1695 static char *overflowed = ", overflowed";
1696 static char *triggered = ", triggered";
1698 command_print(CMD_CTX, "%s: trace collection%s%s%s",
1699 etm->capture_driver->name,
1700 (trace_status & TRACE_RUNNING) ? running : completed,
1701 (trace_status & TRACE_OVERFLOWED) ? overflowed : "",
1702 (trace_status & TRACE_TRIGGERED) ? triggered : "");
1704 if (etm->trace_depth > 0)
1706 command_print(CMD_CTX, "%i frames of trace data read",
1707 (int)(etm->trace_depth));
1714 COMMAND_HANDLER(handle_etm_image_command)
1716 struct target *target;
1718 struct etm_context *etm_ctx;
1722 command_print(CMD_CTX, "usage: etm image <file> [base address] [type]");
1726 target = get_current_target(CMD_CTX);
1727 arm = target_to_arm(target);
1730 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1737 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1743 image_close(etm_ctx->image);
1744 free(etm_ctx->image);
1745 command_print(CMD_CTX, "previously loaded image found and closed");
1748 etm_ctx->image = malloc(sizeof(struct image));
1749 etm_ctx->image->base_address_set = 0;
1750 etm_ctx->image->start_address_set = 0;
1752 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1755 etm_ctx->image->base_address_set = 1;
1756 COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], etm_ctx->image->base_address);
1760 etm_ctx->image->base_address_set = 0;
1763 if (image_open(etm_ctx->image, CMD_ARGV[0], (CMD_ARGC >= 3) ? CMD_ARGV[2] : NULL) != ERROR_OK)
1765 free(etm_ctx->image);
1766 etm_ctx->image = NULL;
1773 COMMAND_HANDLER(handle_etm_dump_command)
1776 struct target *target;
1778 struct etm_context *etm_ctx;
1783 command_print(CMD_CTX, "usage: etm dump <file>");
1787 target = get_current_target(CMD_CTX);
1788 arm = target_to_arm(target);
1791 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1798 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1802 if (etm_ctx->capture_driver->status == TRACE_IDLE)
1804 command_print(CMD_CTX, "trace capture wasn't enabled, no trace data captured");
1808 if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1810 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1811 command_print(CMD_CTX, "trace capture not completed");
1815 /* read the trace data if it wasn't read already */
1816 if (etm_ctx->trace_depth == 0)
1817 etm_ctx->capture_driver->read_trace(etm_ctx);
1819 if (fileio_open(&file, CMD_ARGV[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1824 fileio_write_u32(&file, etm_ctx->capture_status);
1825 fileio_write_u32(&file, etm_ctx->portmode);
1826 fileio_write_u32(&file, etm_ctx->tracemode);
1827 fileio_write_u32(&file, etm_ctx->trace_depth);
1829 for (i = 0; i < etm_ctx->trace_depth; i++)
1831 fileio_write_u32(&file, etm_ctx->trace_data[i].pipestat);
1832 fileio_write_u32(&file, etm_ctx->trace_data[i].packet);
1833 fileio_write_u32(&file, etm_ctx->trace_data[i].flags);
1836 fileio_close(&file);
1841 COMMAND_HANDLER(handle_etm_load_command)
1844 struct target *target;
1846 struct etm_context *etm_ctx;
1851 command_print(CMD_CTX, "usage: etm load <file>");
1855 target = get_current_target(CMD_CTX);
1856 arm = target_to_arm(target);
1859 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1866 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1870 if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1872 command_print(CMD_CTX, "trace capture running, stop first");
1876 if (fileio_open(&file, CMD_ARGV[0], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1883 command_print(CMD_CTX, "size isn't a multiple of 4, no valid trace data");
1884 fileio_close(&file);
1888 if (etm_ctx->trace_depth > 0)
1890 free(etm_ctx->trace_data);
1891 etm_ctx->trace_data = NULL;
1896 fileio_read_u32(&file, &tmp); etm_ctx->capture_status = tmp;
1897 fileio_read_u32(&file, &tmp); etm_ctx->portmode = tmp;
1898 fileio_read_u32(&file, &tmp); etm_ctx->tracemode = tmp;
1899 fileio_read_u32(&file, &etm_ctx->trace_depth);
1901 etm_ctx->trace_data = malloc(sizeof(struct etmv1_trace_data) * etm_ctx->trace_depth);
1902 if (etm_ctx->trace_data == NULL)
1904 command_print(CMD_CTX, "not enough memory to perform operation");
1905 fileio_close(&file);
1909 for (i = 0; i < etm_ctx->trace_depth; i++)
1911 uint32_t pipestat, packet, flags;
1912 fileio_read_u32(&file, &pipestat);
1913 fileio_read_u32(&file, &packet);
1914 fileio_read_u32(&file, &flags);
1915 etm_ctx->trace_data[i].pipestat = pipestat & 0xff;
1916 etm_ctx->trace_data[i].packet = packet & 0xffff;
1917 etm_ctx->trace_data[i].flags = flags;
1920 fileio_close(&file);
1925 COMMAND_HANDLER(handle_etm_trigger_percent_command)
1927 struct target *target;
1929 struct etm_context *etm_ctx;
1931 target = get_current_target(CMD_CTX);
1932 arm = target_to_arm(target);
1935 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1942 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1949 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], new_value);
1951 if ((new_value < 2) || (new_value > 100))
1953 command_print(CMD_CTX, "valid settings are 2%% to 100%%");
1957 etm_ctx->trigger_percent = new_value;
1961 command_print(CMD_CTX, "%i percent of the tracebuffer reserved for after the trigger", ((int)(etm_ctx->trigger_percent)));
1966 COMMAND_HANDLER(handle_etm_start_command)
1968 struct target *target;
1970 struct etm_context *etm_ctx;
1971 struct reg *etm_ctrl_reg;
1973 target = get_current_target(CMD_CTX);
1974 arm = target_to_arm(target);
1977 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1984 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1988 /* invalidate old tracing data */
1989 etm_ctx->capture_status = TRACE_IDLE;
1990 if (etm_ctx->trace_depth > 0)
1992 free(etm_ctx->trace_data);
1993 etm_ctx->trace_data = NULL;
1995 etm_ctx->trace_depth = 0;
1997 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
2001 etm_get_reg(etm_ctrl_reg);
2003 /* Clear programming bit (10), set port selection bit (11) */
2004 buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x2);
2006 etm_store_reg(etm_ctrl_reg);
2007 jtag_execute_queue();
2009 etm_ctx->capture_driver->start_capture(etm_ctx);
2014 COMMAND_HANDLER(handle_etm_stop_command)
2016 struct target *target;
2018 struct etm_context *etm_ctx;
2019 struct reg *etm_ctrl_reg;
2021 target = get_current_target(CMD_CTX);
2022 arm = target_to_arm(target);
2025 command_print(CMD_CTX, "ETM: current target isn't an ARM");
2032 command_print(CMD_CTX, "current target doesn't have an ETM configured");
2036 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
2040 etm_get_reg(etm_ctrl_reg);
2042 /* Set programming bit (10), clear port selection bit (11) */
2043 buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x1);
2045 etm_store_reg(etm_ctrl_reg);
2046 jtag_execute_queue();
2048 etm_ctx->capture_driver->stop_capture(etm_ctx);
2053 COMMAND_HANDLER(handle_etm_analyze_command)
2055 struct target *target;
2057 struct etm_context *etm_ctx;
2060 target = get_current_target(CMD_CTX);
2061 arm = target_to_arm(target);
2064 command_print(CMD_CTX, "ETM: current target isn't an ARM");
2071 command_print(CMD_CTX, "current target doesn't have an ETM configured");
2075 if ((retval = etmv1_analyze_trace(etm_ctx, CMD_CTX)) != ERROR_OK)
2079 case ERROR_ETM_ANALYSIS_FAILED:
2080 command_print(CMD_CTX, "further analysis failed (corrupted trace data or just end of data");
2082 case ERROR_TRACE_INSTRUCTION_UNAVAILABLE:
2083 command_print(CMD_CTX, "no instruction for current address available, analysis aborted");
2085 case ERROR_TRACE_IMAGE_UNAVAILABLE:
2086 command_print(CMD_CTX, "no image available for trace analysis");
2089 command_print(CMD_CTX, "unknown error: %i", retval);
2096 static const struct command_registration etm_config_command_handlers[] = {
2099 .handler = &handle_etm_config_command,
2100 .mode = COMMAND_CONFIG,
2101 .usage = "<target> <port_width> <port_mode> "
2102 "<clocking> <capture_driver>",
2104 COMMAND_REGISTRATION_DONE
2106 const struct command_registration etm_command_handlers[] = {
2109 .mode = COMMAND_ANY,
2110 .help = "Emebdded Trace Macrocell command group",
2111 .chain = etm_config_command_handlers,
2113 COMMAND_REGISTRATION_DONE
2116 static const struct command_registration etm_exec_command_handlers[] = {
2118 .name = "tracemode", handle_etm_tracemode_command,
2119 .mode = COMMAND_EXEC,
2120 .help = "configure/display trace mode",
2121 .usage = "<none | data | address | all> "
2122 "<context_id_bits> <cycle_accurate> <branch_output>",
2126 .handler = &handle_etm_info_command,
2127 .mode = COMMAND_EXEC,
2128 .help = "display info about the current target's ETM",
2131 .name = "trigger_percent",
2132 .handler = &handle_etm_trigger_percent_command,
2133 .mode = COMMAND_EXEC,
2134 .help = "amount (<percent>) of trace buffer "
2135 "to be filled after the trigger occured",
2139 .handler = &handle_etm_status_command,
2140 .mode = COMMAND_EXEC,
2141 .help = "display current target's ETM status",
2145 .handler = &handle_etm_start_command,
2146 .mode = COMMAND_EXEC,
2147 .help = "start ETM trace collection",
2151 .handler = &handle_etm_stop_command,
2152 .mode = COMMAND_EXEC,
2153 .help = "stop ETM trace collection",
2157 .handler = &handle_etm_analyze_command,
2158 .mode = COMMAND_EXEC,
2159 .help = "anaylze collected ETM trace",
2163 .handler = &handle_etm_image_command,
2164 .mode = COMMAND_EXEC,
2165 .help = "load image from <file> [base address]",
2169 .handler = &handle_etm_dump_command,
2170 .mode = COMMAND_EXEC,
2171 .help = "dump captured trace data <file>",
2175 .handler = &handle_etm_load_command,
2176 .mode = COMMAND_EXEC,
2177 .help = "load trace data for analysis <file>",
2179 COMMAND_REGISTRATION_DONE
2182 static int etm_register_user_commands(struct command_context *cmd_ctx)
2184 struct command *etm_cmd = command_find_in_context(cmd_ctx, "etm");
2185 return register_commands(cmd_ctx, etm_cmd, etm_exec_command_handlers);