1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
28 #include "arm_disassembler.h"
30 #include "etm_dummy.h"
32 #if BUILD_OOCD_TRACE == 1
33 #include "oocd_trace.h"
38 * ARM "Embedded Trace Macrocell" (ETM) support -- direct JTAG access.
40 * ETM modules collect instruction and/or data trace information, compress
41 * it, and transfer it to a debugging host through either a (buffered) trace
42 * port (often a 38-pin Mictor connector) or an Embedded Trace Buffer (ETB).
44 * There are several generations of these modules. Original versions have
45 * JTAG access through a dedicated scan chain. Recent versions have added
46 * access via coprocessor instructions, memory addressing, and the ARM Debug
47 * Interface v5 (ADIv5); and phased out direct JTAG access.
49 * This code supports up to the ETMv1.3 architecture, as seen in ETM9 and
50 * most common ARM9 systems. Note: "CoreSight ETM9" implements ETMv3.2,
51 * implying non-JTAG connectivity options.
53 * Relevant documentation includes:
54 * ARM DDI 0157G ... ETM9 (r2p2) Technical Reference Manual
55 * ARM DDI 0315B ... CoreSight ETM9 (r0p1) Technical Reference Manual
56 * ARM IHI 0014O ... Embedded Trace Macrocell, Architecture Specification
67 uint8_t size; /* low-N of 32 bits */
68 uint8_t mode; /* RO, WO, RW */
69 uint8_t bcd_vers; /* 1.0, 2.0, etc */
74 * Registers 0..0x7f are JTAG-addressable using scanchain 6.
75 * (Or on some processors, through coprocessor operations.)
76 * Newer versions of ETM make some W/O registers R/W, and
77 * provide definitions for some previously-unused bits.
80 /* core registers used to version/configure the ETM */
81 static const struct etm_reg_info etm_core[] = {
82 /* NOTE: we "know" the order here ... */
83 { ETM_CONFIG, 32, RO, 0x10, "ETM_config", },
84 { ETM_ID, 32, RO, 0x20, "ETM_id", },
87 /* basic registers that are always there given the right ETM version */
88 static const struct etm_reg_info etm_basic[] = {
89 /* ETM Trace Registers */
90 { ETM_CTRL, 32, RW, 0x10, "ETM_ctrl", },
91 { ETM_TRIG_EVENT, 17, WO, 0x10, "ETM_trig_event", },
92 { ETM_ASIC_CTRL, 8, WO, 0x10, "ETM_asic_ctrl", },
93 { ETM_STATUS, 3, RO, 0x11, "ETM_status", },
94 { ETM_SYS_CONFIG, 9, RO, 0x12, "ETM_sys_config", },
96 /* TraceEnable configuration */
97 { ETM_TRACE_RESOURCE_CTRL, 32, WO, 0x12, "ETM_trace_resource_ctrl", },
98 { ETM_TRACE_EN_CTRL2, 16, WO, 0x12, "ETM_trace_en_ctrl2", },
99 { ETM_TRACE_EN_EVENT, 17, WO, 0x10, "ETM_trace_en_event", },
100 { ETM_TRACE_EN_CTRL1, 26, WO, 0x10, "ETM_trace_en_ctrl1", },
102 /* ViewData configuration (data trace) */
103 { ETM_VIEWDATA_EVENT, 17, WO, 0x10, "ETM_viewdata_event", },
104 { ETM_VIEWDATA_CTRL1, 32, WO, 0x10, "ETM_viewdata_ctrl1", },
105 { ETM_VIEWDATA_CTRL2, 32, WO, 0x10, "ETM_viewdata_ctrl2", },
106 { ETM_VIEWDATA_CTRL3, 17, WO, 0x10, "ETM_viewdata_ctrl3", },
108 /* REVISIT exclude VIEWDATA_CTRL2 when it's not there */
110 { 0x78, 12, WO, 0x20, "ETM_sync_freq", },
111 { 0x7a, 22, RO, 0x31, "ETM_config_code_ext", },
112 { 0x7b, 32, WO, 0x31, "ETM_ext_input_select", },
113 { 0x7c, 32, WO, 0x34, "ETM_trace_start_stop", },
114 { 0x7d, 8, WO, 0x34, "ETM_behavior_control", },
117 static const struct etm_reg_info etm_fifofull[] = {
118 /* FIFOFULL configuration */
119 { ETM_FIFOFULL_REGION, 25, WO, 0x10, "ETM_fifofull_region", },
120 { ETM_FIFOFULL_LEVEL, 8, WO, 0x10, "ETM_fifofull_level", },
123 static const struct etm_reg_info etm_addr_comp[] = {
124 /* Address comparator register pairs */
125 #define ADDR_COMPARATOR(i) \
126 { ETM_ADDR_COMPARATOR_VALUE + (i) - 1, 32, WO, 0x10, \
127 "ETM_addr_" #i "_comparator_value", }, \
128 { ETM_ADDR_ACCESS_TYPE + (i) - 1, 7, WO, 0x10, \
129 "ETM_addr_" #i "_access_type", }
147 #undef ADDR_COMPARATOR
150 static const struct etm_reg_info etm_data_comp[] = {
151 /* Data Value Comparators (NOTE: odd addresses are reserved) */
152 #define DATA_COMPARATOR(i) \
153 { ETM_DATA_COMPARATOR_VALUE + 2*(i) - 1, 32, WO, 0x10, \
154 "ETM_data_" #i "_comparator_value", }, \
155 { ETM_DATA_COMPARATOR_MASK + 2*(i) - 1, 32, WO, 0x10, \
156 "ETM_data_" #i "_comparator_mask", }
165 #undef DATA_COMPARATOR
168 static const struct etm_reg_info etm_counters[] = {
169 #define ETM_COUNTER(i) \
170 { ETM_COUNTER_RELOAD_VALUE + (i) - 1, 16, WO, 0x10, \
171 "ETM_counter_" #i "_reload_value", }, \
172 { ETM_COUNTER_ENABLE + (i) - 1, 18, WO, 0x10, \
173 "ETM_counter_" #i "_enable", }, \
174 { ETM_COUNTER_RELOAD_EVENT + (i) - 1, 17, WO, 0x10, \
175 "ETM_counter_" #i "_reload_event", }, \
176 { ETM_COUNTER_VALUE + (i) - 1, 16, RO, 0x10, \
177 "ETM_counter_" #i "_value", }
185 static const struct etm_reg_info etm_sequencer[] = {
187 { ETM_SEQUENCER_EVENT + (i), 17, WO, 0x10, \
188 "ETM_sequencer_event" #i, }
189 ETM_SEQ(0), /* 1->2 */
190 ETM_SEQ(1), /* 2->1 */
191 ETM_SEQ(2), /* 2->3 */
192 ETM_SEQ(3), /* 3->1 */
193 ETM_SEQ(4), /* 3->2 */
194 ETM_SEQ(5), /* 1->3 */
197 { ETM_SEQUENCER_STATE, 2, RO, 0x10, "ETM_sequencer_state", },
200 static const struct etm_reg_info etm_outputs[] = {
201 #define ETM_OUTPUT(i) \
202 { ETM_EXTERNAL_OUTPUT + (i) - 1, 17, WO, 0x10, \
203 "ETM_external_output" #i, }
213 /* registers from 0x6c..0x7f were added after ETMv1.3 */
215 /* Context ID Comparators */
216 { 0x6c, 32, RO, 0x20, "ETM_contextid_comparator_value1", }
217 { 0x6d, 32, RO, 0x20, "ETM_contextid_comparator_value2", }
218 { 0x6e, 32, RO, 0x20, "ETM_contextid_comparator_value3", }
219 { 0x6f, 32, RO, 0x20, "ETM_contextid_comparator_mask", }
222 static int etm_get_reg(struct reg *reg);
223 static int etm_read_reg_w_check(struct reg *reg,
224 uint8_t* check_value, uint8_t* check_mask);
225 static int etm_register_user_commands(struct command_context *cmd_ctx);
226 static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf);
227 static int etm_write_reg(struct reg *reg, uint32_t value);
229 static const struct reg_arch_type etm_scan6_type = {
231 .set = etm_set_reg_w_exec,
234 /* Look up register by ID ... most ETM instances only
235 * support a subset of the possible registers.
237 static struct reg *etm_reg_lookup(struct etm_context *etm_ctx, unsigned id)
239 struct reg_cache *cache = etm_ctx->reg_cache;
242 for (i = 0; i < cache->num_regs; i++) {
243 struct etm_reg *reg = cache->reg_list[i].arch_info;
245 if (reg->reg_info->addr == id)
246 return &cache->reg_list[i];
249 /* caller asking for nonexistent register is a bug! */
250 /* REVISIT say which of the N targets was involved */
251 LOG_ERROR("ETM: register 0x%02x not available", id);
255 static void etm_reg_add(unsigned bcd_vers, struct arm_jtag *jtag_info,
256 struct reg_cache *cache, struct etm_reg *ereg,
257 const struct etm_reg_info *r, unsigned nreg)
259 struct reg *reg = cache->reg_list;
261 reg += cache->num_regs;
262 ereg += cache->num_regs;
264 /* add up to "nreg" registers from "r", if supported by this
265 * version of the ETM, to the specified cache.
267 for (; nreg--; r++) {
269 /* this ETM may be too old to have some registers */
270 if (r->bcd_vers > bcd_vers)
275 reg->value = &ereg->value;
276 reg->arch_info = ereg;
277 reg->type = &etm_scan6_type;
282 ereg->jtag_info = jtag_info;
287 struct reg_cache *etm_build_reg_cache(struct target *target,
288 struct arm_jtag *jtag_info, struct etm_context *etm_ctx)
290 struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
291 struct reg *reg_list = NULL;
292 struct etm_reg *arch_info = NULL;
293 unsigned bcd_vers, config;
295 /* the actual registers are kept in two arrays */
296 reg_list = calloc(128, sizeof(struct reg));
297 arch_info = calloc(128, sizeof(struct etm_reg));
299 /* fill in values for the reg cache */
300 reg_cache->name = "etm registers";
301 reg_cache->next = NULL;
302 reg_cache->reg_list = reg_list;
303 reg_cache->num_regs = 0;
305 /* add ETM_CONFIG, then parse its values to see
306 * which other registers exist in this ETM
308 etm_reg_add(0x10, jtag_info, reg_cache, arch_info,
311 etm_get_reg(reg_list);
312 etm_ctx->config = buf_get_u32((void *)&arch_info->value, 0, 32);
313 config = etm_ctx->config;
315 /* figure ETM version then add base registers */
316 if (config & (1 << 31)) {
318 LOG_WARNING("ETMv2+ support is incomplete");
320 /* REVISIT more registers may exist; they may now be
321 * readable; more register bits have defined meanings;
322 * don't presume trace start/stop support is present;
323 * and include any context ID comparator registers.
325 etm_reg_add(0x20, jtag_info, reg_cache, arch_info,
327 etm_get_reg(reg_list + 1);
328 etm_ctx->id = buf_get_u32(
329 (void *)&arch_info[1].value, 0, 32);
330 LOG_DEBUG("ETM ID: %08x", (unsigned) etm_ctx->id);
331 bcd_vers = 0x10 + (((etm_ctx->id) >> 4) & 0xff);
334 switch (config >> 28) {
351 LOG_WARNING("Bad ETMv1 protocol %d", config >> 28);
355 etm_ctx->bcd_vers = bcd_vers;
356 LOG_INFO("ETM v%d.%d", bcd_vers >> 4, bcd_vers & 0xf);
358 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
359 etm_basic, ARRAY_SIZE(etm_basic));
361 /* address and data comparators; counters; outputs */
362 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
363 etm_addr_comp, 4 * (0x0f & (config >> 0)));
364 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
365 etm_data_comp, 2 * (0x0f & (config >> 4)));
366 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
367 etm_counters, 4 * (0x07 & (config >> 13)));
368 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
369 etm_outputs, (0x07 & (config >> 20)));
371 /* FIFOFULL presence is optional
372 * REVISIT for ETMv1.2 and later, don't bother adding this
373 * unless ETM_SYS_CONFIG says it's also *supported* ...
375 if (config & (1 << 23))
376 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
377 etm_fifofull, ARRAY_SIZE(etm_fifofull));
379 /* sequencer is optional (for state-dependant triggering) */
380 if (config & (1 << 16))
381 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
382 etm_sequencer, ARRAY_SIZE(etm_sequencer));
384 /* REVISIT could realloc and likely save half the memory
385 * in the two chunks we allocated...
388 /* the ETM might have an ETB connected */
389 if (strcmp(etm_ctx->capture_driver->name, "etb") == 0)
391 struct etb *etb = etm_ctx->capture_driver_priv;
395 LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
399 reg_cache->next = etb_build_reg_cache(etb);
401 etb->reg_cache = reg_cache->next;
404 etm_ctx->reg_cache = reg_cache;
414 static int etm_read_reg(struct reg *reg)
416 return etm_read_reg_w_check(reg, NULL, NULL);
419 static int etm_store_reg(struct reg *reg)
421 return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
424 int etm_setup(struct target *target)
427 uint32_t etm_ctrl_value;
428 struct arm *arm = target_to_arm(target);
429 struct etm_context *etm_ctx = arm->etm;
430 struct reg *etm_ctrl_reg;
432 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
436 /* initialize some ETM control register settings */
437 etm_get_reg(etm_ctrl_reg);
438 etm_ctrl_value = buf_get_u32(etm_ctrl_reg->value, 0, 32);
440 /* clear the ETM powerdown bit (0) */
441 etm_ctrl_value &= ~ETM_CTRL_POWERDOWN;
443 /* configure port width (21,6:4), mode (13,17:16) and
444 * for older modules clocking (13)
446 etm_ctrl_value = (etm_ctrl_value
447 & ~ETM_PORT_WIDTH_MASK
448 & ~ETM_PORT_MODE_MASK
450 & ~ETM_PORT_CLOCK_MASK)
453 buf_set_u32(etm_ctrl_reg->value, 0, 32, etm_ctrl_value);
454 etm_store_reg(etm_ctrl_reg);
456 etm_ctx->control = etm_ctrl_value;
458 if ((retval = jtag_execute_queue()) != ERROR_OK)
461 /* REVISIT for ETMv3.0 and later, read ETM_sys_config to
462 * verify that those width and mode settings are OK ...
465 if ((retval = etm_ctx->capture_driver->init(etm_ctx)) != ERROR_OK)
467 LOG_ERROR("ETM capture driver initialization failed");
473 static int etm_get_reg(struct reg *reg)
477 if ((retval = etm_read_reg(reg)) != ERROR_OK)
479 LOG_ERROR("BUG: error scheduling etm register read");
483 if ((retval = jtag_execute_queue()) != ERROR_OK)
485 LOG_ERROR("register read failed");
492 static int etm_read_reg_w_check(struct reg *reg,
493 uint8_t* check_value, uint8_t* check_mask)
495 struct etm_reg *etm_reg = reg->arch_info;
496 const struct etm_reg_info *r = etm_reg->reg_info;
497 uint8_t reg_addr = r->addr & 0x7f;
498 struct scan_field fields[3];
500 if (etm_reg->reg_info->mode == WO) {
501 LOG_ERROR("BUG: can't read write-only register %s", r->name);
502 return ERROR_INVALID_ARGUMENTS;
505 LOG_DEBUG("%s (%u)", r->name, reg_addr);
507 jtag_set_end_state(TAP_IDLE);
508 arm_jtag_scann(etm_reg->jtag_info, 0x6);
509 arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
511 fields[0].tap = etm_reg->jtag_info->tap;
512 fields[0].num_bits = 32;
513 fields[0].out_value = reg->value;
514 fields[0].in_value = NULL;
515 fields[0].check_value = NULL;
516 fields[0].check_mask = NULL;
518 fields[1].tap = etm_reg->jtag_info->tap;
519 fields[1].num_bits = 7;
520 fields[1].out_value = malloc(1);
521 buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
522 fields[1].in_value = NULL;
523 fields[1].check_value = NULL;
524 fields[1].check_mask = NULL;
526 fields[2].tap = etm_reg->jtag_info->tap;
527 fields[2].num_bits = 1;
528 fields[2].out_value = malloc(1);
529 buf_set_u32(fields[2].out_value, 0, 1, 0);
530 fields[2].in_value = NULL;
531 fields[2].check_value = NULL;
532 fields[2].check_mask = NULL;
534 jtag_add_dr_scan(3, fields, jtag_get_end_state());
536 fields[0].in_value = reg->value;
537 fields[0].check_value = check_value;
538 fields[0].check_mask = check_mask;
540 jtag_add_dr_scan_check(3, fields, jtag_get_end_state());
542 free(fields[1].out_value);
543 free(fields[2].out_value);
548 static int etm_set_reg(struct reg *reg, uint32_t value)
552 if ((retval = etm_write_reg(reg, value)) != ERROR_OK)
554 LOG_ERROR("BUG: error scheduling etm register write");
558 buf_set_u32(reg->value, 0, reg->size, value);
565 static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf)
569 etm_set_reg(reg, buf_get_u32(buf, 0, reg->size));
571 if ((retval = jtag_execute_queue()) != ERROR_OK)
573 LOG_ERROR("register write failed");
579 static int etm_write_reg(struct reg *reg, uint32_t value)
581 struct etm_reg *etm_reg = reg->arch_info;
582 const struct etm_reg_info *r = etm_reg->reg_info;
583 uint8_t reg_addr = r->addr & 0x7f;
584 struct scan_field fields[3];
586 if (etm_reg->reg_info->mode == RO) {
587 LOG_ERROR("BUG: can't write read--only register %s", r->name);
588 return ERROR_INVALID_ARGUMENTS;
591 LOG_DEBUG("%s (%u): 0x%8.8" PRIx32 "", r->name, reg_addr, value);
593 jtag_set_end_state(TAP_IDLE);
594 arm_jtag_scann(etm_reg->jtag_info, 0x6);
595 arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
597 fields[0].tap = etm_reg->jtag_info->tap;
598 fields[0].num_bits = 32;
600 fields[0].out_value = tmp1;
601 buf_set_u32(fields[0].out_value, 0, 32, value);
602 fields[0].in_value = NULL;
604 fields[1].tap = etm_reg->jtag_info->tap;
605 fields[1].num_bits = 7;
607 fields[1].out_value = &tmp2;
608 buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
609 fields[1].in_value = NULL;
611 fields[2].tap = etm_reg->jtag_info->tap;
612 fields[2].num_bits = 1;
614 fields[2].out_value = &tmp3;
615 buf_set_u32(fields[2].out_value, 0, 1, 1);
616 fields[2].in_value = NULL;
618 jtag_add_dr_scan(3, fields, jtag_get_end_state());
624 /* ETM trace analysis functionality */
626 static struct etm_capture_driver *etm_capture_drivers[] =
629 &etm_dummy_capture_driver,
630 #if BUILD_OOCD_TRACE == 1
631 &oocd_trace_capture_driver,
636 static int etm_read_instruction(struct etm_context *ctx, struct arm_instruction *instruction)
645 return ERROR_TRACE_IMAGE_UNAVAILABLE;
647 /* search for the section the current instruction belongs to */
648 for (i = 0; i < ctx->image->num_sections; i++)
650 if ((ctx->image->sections[i].base_address <= ctx->current_pc) &&
651 (ctx->image->sections[i].base_address + ctx->image->sections[i].size > ctx->current_pc))
660 /* current instruction couldn't be found in the image */
661 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
664 if (ctx->core_state == ARM_STATE_ARM)
667 if ((retval = image_read_section(ctx->image, section,
668 ctx->current_pc - ctx->image->sections[section].base_address,
669 4, buf, &size_read)) != ERROR_OK)
671 LOG_ERROR("error while reading instruction: %i", retval);
672 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
674 opcode = target_buffer_get_u32(ctx->target, buf);
675 arm_evaluate_opcode(opcode, ctx->current_pc, instruction);
677 else if (ctx->core_state == ARM_STATE_THUMB)
680 if ((retval = image_read_section(ctx->image, section,
681 ctx->current_pc - ctx->image->sections[section].base_address,
682 2, buf, &size_read)) != ERROR_OK)
684 LOG_ERROR("error while reading instruction: %i", retval);
685 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
687 opcode = target_buffer_get_u16(ctx->target, buf);
688 thumb_evaluate_opcode(opcode, ctx->current_pc, instruction);
690 else if (ctx->core_state == ARM_STATE_JAZELLE)
692 LOG_ERROR("BUG: tracing of jazelle code not supported");
697 LOG_ERROR("BUG: unknown core state encountered");
704 static int etmv1_next_packet(struct etm_context *ctx, uint8_t *packet, int apo)
706 while (ctx->data_index < ctx->trace_depth)
708 /* if the caller specified an address packet offset, skip until the
709 * we reach the n-th cycle marked with tracesync */
712 if (ctx->trace_data[ctx->data_index].flags & ETMV1_TRACESYNC_CYCLE)
723 /* no tracedata output during a TD cycle
724 * or in a trigger cycle */
725 if ((ctx->trace_data[ctx->data_index].pipestat == STAT_TD)
726 || (ctx->trace_data[ctx->data_index].flags & ETMV1_TRIGGER_CYCLE))
733 /* FIXME there are more port widths than these... */
734 if ((ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_16BIT)
736 if (ctx->data_half == 0)
738 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
743 *packet = (ctx->trace_data[ctx->data_index].packet & 0xff00) >> 8;
748 else if ((ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
750 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
755 /* on a 4-bit port, a packet will be output during two consecutive cycles */
756 if (ctx->data_index > (ctx->trace_depth - 2))
759 *packet = ctx->trace_data[ctx->data_index].packet & 0xf;
760 *packet |= (ctx->trace_data[ctx->data_index + 1].packet & 0xf) << 4;
761 ctx->data_index += 2;
770 static int etmv1_branch_address(struct etm_context *ctx)
778 /* quit analysis if less than two cycles are left in the trace
779 * because we can't extract the APO */
780 if (ctx->data_index > (ctx->trace_depth - 2))
783 /* a BE could be output during an APO cycle, skip the current
784 * and continue with the new one */
785 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x4)
787 if (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x4)
790 /* address packet offset encoded in the next two cycles' pipestat bits */
791 apo = ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x3;
792 apo |= (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x3) << 2;
794 /* count number of tracesync cycles between current pipe_index and data_index
795 * i.e. the number of tracesyncs that data_index already passed by
796 * to subtract them from the APO */
797 for (i = ctx->pipe_index; i < ctx->data_index; i++)
799 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & ETMV1_TRACESYNC_CYCLE)
803 /* extract up to four 7-bit packets */
805 if ((retval = etmv1_next_packet(ctx, &packet, (shift == 0) ? apo + 1 : 0)) != 0)
807 ctx->last_branch &= ~(0x7f << shift);
808 ctx->last_branch |= (packet & 0x7f) << shift;
810 } while ((packet & 0x80) && (shift < 28));
812 /* one last packet holding 4 bits of the address, plus the branch reason code */
813 if ((shift == 28) && (packet & 0x80))
815 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
817 ctx->last_branch &= 0x0fffffff;
818 ctx->last_branch |= (packet & 0x0f) << 28;
819 ctx->last_branch_reason = (packet & 0x70) >> 4;
824 ctx->last_branch_reason = 0;
832 /* if a full address was output, we might have branched into Jazelle state */
833 if ((shift == 32) && (packet & 0x80))
835 ctx->core_state = ARM_STATE_JAZELLE;
839 /* if we didn't branch into Jazelle state, the current processor state is
840 * encoded in bit 0 of the branch target address */
841 if (ctx->last_branch & 0x1)
843 ctx->core_state = ARM_STATE_THUMB;
844 ctx->last_branch &= ~0x1;
848 ctx->core_state = ARM_STATE_ARM;
849 ctx->last_branch &= ~0x3;
856 static int etmv1_data(struct etm_context *ctx, int size, uint32_t *data)
862 for (j = 0; j < size; j++)
864 if ((retval = etmv1_next_packet(ctx, &buf[j], 0)) != 0)
870 LOG_ERROR("TODO: add support for 64-bit values");
874 *data = target_buffer_get_u32(ctx->target, buf);
876 *data = target_buffer_get_u16(ctx->target, buf);
885 static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context *cmd_ctx)
888 struct arm_instruction instruction;
890 /* read the trace data if it wasn't read already */
891 if (ctx->trace_depth == 0)
892 ctx->capture_driver->read_trace(ctx);
894 /* start at the beginning of the captured trace */
899 /* neither the PC nor the data pointer are valid */
903 while (ctx->pipe_index < ctx->trace_depth)
905 uint8_t pipestat = ctx->trace_data[ctx->pipe_index].pipestat;
906 uint32_t next_pc = ctx->current_pc;
907 uint32_t old_data_index = ctx->data_index;
908 uint32_t old_data_half = ctx->data_half;
909 uint32_t old_index = ctx->pipe_index;
910 uint32_t last_instruction = ctx->last_instruction;
912 int current_pc_ok = ctx->pc_ok;
914 if (ctx->trace_data[ctx->pipe_index].flags & ETMV1_TRIGGER_CYCLE)
916 command_print(cmd_ctx, "--- trigger ---");
919 /* instructions execute in IE/D or BE/D cycles */
920 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
921 ctx->last_instruction = ctx->pipe_index;
923 /* if we don't have a valid pc skip until we reach an indirect branch */
924 if ((!ctx->pc_ok) && (pipestat != STAT_BE))
930 /* any indirect branch could have interrupted instruction flow
931 * - the branch reason code could indicate a trace discontinuity
932 * - a branch to the exception vectors indicates an exception
934 if ((pipestat == STAT_BE) || (pipestat == STAT_BD))
936 /* backup current data index, to be able to consume the branch address
937 * before examining data address and values
939 old_data_index = ctx->data_index;
940 old_data_half = ctx->data_half;
942 ctx->last_instruction = ctx->pipe_index;
944 if ((retval = etmv1_branch_address(ctx)) != 0)
946 /* negative return value from etmv1_branch_address means we ran out of packets,
947 * quit analysing the trace */
951 /* a positive return values means the current branch was abandoned,
952 * and a new branch was encountered in cycle ctx->pipe_index + retval;
954 LOG_WARNING("abandoned branch encountered, correctnes of analysis uncertain");
955 ctx->pipe_index += retval;
959 /* skip over APO cycles */
960 ctx->pipe_index += 2;
962 switch (ctx->last_branch_reason)
964 case 0x0: /* normal PC change */
965 next_pc = ctx->last_branch;
967 case 0x1: /* tracing enabled */
968 command_print(cmd_ctx, "--- tracing enabled at 0x%8.8" PRIx32 " ---", ctx->last_branch);
969 ctx->current_pc = ctx->last_branch;
973 case 0x2: /* trace restarted after FIFO overflow */
974 command_print(cmd_ctx, "--- trace restarted after FIFO overflow at 0x%8.8" PRIx32 " ---", ctx->last_branch);
975 ctx->current_pc = ctx->last_branch;
979 case 0x3: /* exit from debug state */
980 command_print(cmd_ctx, "--- exit from debug state at 0x%8.8" PRIx32 " ---", ctx->last_branch);
981 ctx->current_pc = ctx->last_branch;
985 case 0x4: /* periodic synchronization point */
986 next_pc = ctx->last_branch;
987 /* if we had no valid PC prior to this synchronization point,
988 * we have to move on with the next trace cycle
992 command_print(cmd_ctx, "--- periodic synchronization point at 0x%8.8" PRIx32 " ---", next_pc);
993 ctx->current_pc = next_pc;
998 default: /* reserved */
999 LOG_ERROR("BUG: branch reason code 0x%" PRIx32 " is reserved", ctx->last_branch_reason);
1003 /* if we got here the branch was a normal PC change
1004 * (or a periodic synchronization point, which means the same for that matter)
1005 * if we didn't accquire a complete PC continue with the next cycle
1010 /* indirect branch to the exception vector means an exception occured */
1011 if ((ctx->last_branch <= 0x20)
1012 || ((ctx->last_branch >= 0xffff0000) && (ctx->last_branch <= 0xffff0020)))
1014 if ((ctx->last_branch & 0xff) == 0x10)
1016 command_print(cmd_ctx, "data abort");
1020 command_print(cmd_ctx, "exception vector 0x%2.2" PRIx32 "", ctx->last_branch);
1021 ctx->current_pc = ctx->last_branch;
1028 /* an instruction was executed (or not, depending on the condition flags)
1029 * retrieve it from the image for displaying */
1030 if (ctx->pc_ok && (pipestat != STAT_WT) && (pipestat != STAT_TD) &&
1031 !(((pipestat == STAT_BE) || (pipestat == STAT_BD)) &&
1032 ((ctx->last_branch_reason != 0x0) && (ctx->last_branch_reason != 0x4))))
1034 if ((retval = etm_read_instruction(ctx, &instruction)) != ERROR_OK)
1036 /* can't continue tracing with no image available */
1037 if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
1041 else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE)
1043 /* TODO: handle incomplete images
1044 * for now we just quit the analsysis*/
1049 cycles = old_index - last_instruction;
1052 if ((pipestat == STAT_ID) || (pipestat == STAT_BD))
1054 uint32_t new_data_index = ctx->data_index;
1055 uint32_t new_data_half = ctx->data_half;
1057 /* in case of a branch with data, the branch target address was consumed before
1058 * we temporarily go back to the saved data index */
1059 if (pipestat == STAT_BD)
1061 ctx->data_index = old_data_index;
1062 ctx->data_half = old_data_half;
1065 if (ctx->control & ETM_CTRL_TRACE_ADDR)
1071 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
1072 return ERROR_ETM_ANALYSIS_FAILED;
1073 ctx->last_ptr &= ~(0x7f << shift);
1074 ctx->last_ptr |= (packet & 0x7f) << shift;
1076 } while ((packet & 0x80) && (shift < 32));
1083 command_print(cmd_ctx, "address: 0x%8.8" PRIx32 "", ctx->last_ptr);
1087 if (ctx->control & ETM_CTRL_TRACE_DATA)
1089 if ((instruction.type == ARM_LDM) || (instruction.type == ARM_STM))
1092 for (i = 0; i < 16; i++)
1094 if (instruction.info.load_store_multiple.register_list & (1 << i))
1097 if (etmv1_data(ctx, 4, &data) != 0)
1098 return ERROR_ETM_ANALYSIS_FAILED;
1099 command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
1103 else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_STRH))
1106 if (etmv1_data(ctx, arm_access_size(&instruction), &data) != 0)
1107 return ERROR_ETM_ANALYSIS_FAILED;
1108 command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
1112 /* restore data index after consuming BD address and data */
1113 if (pipestat == STAT_BD)
1115 ctx->data_index = new_data_index;
1116 ctx->data_half = new_data_half;
1121 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
1123 if (((instruction.type == ARM_B) ||
1124 (instruction.type == ARM_BL) ||
1125 (instruction.type == ARM_BLX)) &&
1126 (instruction.info.b_bl_bx_blx.target_address != 0xffffffff))
1128 next_pc = instruction.info.b_bl_bx_blx.target_address;
1132 next_pc += (ctx->core_state == ARM_STATE_ARM) ? 4 : 2;
1135 else if (pipestat == STAT_IN)
1137 next_pc += (ctx->core_state == ARM_STATE_ARM) ? 4 : 2;
1140 if ((pipestat != STAT_TD) && (pipestat != STAT_WT))
1142 char cycles_text[32] = "";
1144 /* if the trace was captured with cycle accurate tracing enabled,
1145 * output the number of cycles since the last executed instruction
1147 if (ctx->control & ETM_CTRL_CYCLE_ACCURATE)
1149 snprintf(cycles_text, 32, " (%i %s)",
1151 (cycles == 1) ? "cycle" : "cycles");
1154 command_print(cmd_ctx, "%s%s%s",
1156 (pipestat == STAT_IN) ? " (not executed)" : "",
1159 ctx->current_pc = next_pc;
1161 /* packets for an instruction don't start on or before the preceding
1162 * functional pipestat (i.e. other than WT or TD)
1164 if (ctx->data_index <= ctx->pipe_index)
1166 ctx->data_index = ctx->pipe_index + 1;
1171 ctx->pipe_index += 1;
1177 static COMMAND_HELPER(handle_etm_tracemode_command_update,
1182 /* what parts of data access are traced? */
1183 if (strcmp(CMD_ARGV[0], "none") == 0)
1185 else if (strcmp(CMD_ARGV[0], "data") == 0)
1186 tracemode = ETM_CTRL_TRACE_DATA;
1187 else if (strcmp(CMD_ARGV[0], "address") == 0)
1188 tracemode = ETM_CTRL_TRACE_ADDR;
1189 else if (strcmp(CMD_ARGV[0], "all") == 0)
1190 tracemode = ETM_CTRL_TRACE_DATA | ETM_CTRL_TRACE_ADDR;
1193 command_print(CMD_CTX, "invalid option '%s'", CMD_ARGV[0]);
1194 return ERROR_INVALID_ARGUMENTS;
1198 COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], context_id);
1202 tracemode |= ETM_CTRL_CONTEXTID_NONE;
1205 tracemode |= ETM_CTRL_CONTEXTID_8;
1208 tracemode |= ETM_CTRL_CONTEXTID_16;
1211 tracemode |= ETM_CTRL_CONTEXTID_32;
1214 command_print(CMD_CTX, "invalid option '%s'", CMD_ARGV[1]);
1215 return ERROR_INVALID_ARGUMENTS;
1218 bool etmv1_cycle_accurate;
1219 COMMAND_PARSE_ENABLE(CMD_ARGV[2], etmv1_cycle_accurate);
1220 if (etmv1_cycle_accurate)
1221 tracemode |= ETM_CTRL_CYCLE_ACCURATE;
1223 bool etmv1_branch_output;
1224 COMMAND_PARSE_ENABLE(CMD_ARGV[3], etmv1_branch_output);
1225 if (etmv1_branch_output)
1226 tracemode |= ETM_CTRL_BRANCH_OUTPUT;
1229 * - CPRT tracing (coprocessor register transfers)
1230 * - debug request (causes debug entry on trigger)
1231 * - stall on FIFOFULL (preventing tracedata lossage)
1238 COMMAND_HANDLER(handle_etm_tracemode_command)
1240 struct target *target = get_current_target(CMD_CTX);
1241 struct arm *arm = target_to_arm(target);
1242 struct etm_context *etm;
1245 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1251 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1255 uint32_t tracemode = etm->control;
1262 CALL_COMMAND_HANDLER(handle_etm_tracemode_command_update,
1266 command_print(CMD_CTX, "usage: tracemode "
1267 "('none'|'data'|'address'|'all') "
1269 "('enable'|'disable') "
1270 "('enable'|'disable')"
1276 * todo: fail if parameters were invalid for this hardware,
1277 * or couldn't be written; display actual hardware state...
1280 command_print(CMD_CTX, "current tracemode configuration:");
1282 switch (tracemode & ETM_CTRL_TRACE_MASK)
1285 command_print(CMD_CTX, "data tracing: none");
1287 case ETM_CTRL_TRACE_DATA:
1288 command_print(CMD_CTX, "data tracing: data only");
1290 case ETM_CTRL_TRACE_ADDR:
1291 command_print(CMD_CTX, "data tracing: address only");
1293 case ETM_CTRL_TRACE_DATA | ETM_CTRL_TRACE_ADDR:
1294 command_print(CMD_CTX, "data tracing: address and data");
1298 switch (tracemode & ETM_CTRL_CONTEXTID_MASK)
1300 case ETM_CTRL_CONTEXTID_NONE:
1301 command_print(CMD_CTX, "contextid tracing: none");
1303 case ETM_CTRL_CONTEXTID_8:
1304 command_print(CMD_CTX, "contextid tracing: 8 bit");
1306 case ETM_CTRL_CONTEXTID_16:
1307 command_print(CMD_CTX, "contextid tracing: 16 bit");
1309 case ETM_CTRL_CONTEXTID_32:
1310 command_print(CMD_CTX, "contextid tracing: 32 bit");
1314 if (tracemode & ETM_CTRL_CYCLE_ACCURATE)
1316 command_print(CMD_CTX, "cycle-accurate tracing enabled");
1320 command_print(CMD_CTX, "cycle-accurate tracing disabled");
1323 if (tracemode & ETM_CTRL_BRANCH_OUTPUT)
1325 command_print(CMD_CTX, "full branch address output enabled");
1329 command_print(CMD_CTX, "full branch address output disabled");
1332 #define TRACEMODE_MASK ( \
1333 ETM_CTRL_CONTEXTID_MASK \
1334 | ETM_CTRL_BRANCH_OUTPUT \
1335 | ETM_CTRL_CYCLE_ACCURATE \
1336 | ETM_CTRL_TRACE_MASK \
1339 /* only update ETM_CTRL register if tracemode changed */
1340 if ((etm->control & TRACEMODE_MASK) != tracemode)
1342 struct reg *etm_ctrl_reg;
1344 etm_ctrl_reg = etm_reg_lookup(etm, ETM_CTRL);
1348 etm->control &= ~TRACEMODE_MASK;
1349 etm->control |= tracemode & TRACEMODE_MASK;
1351 buf_set_u32(etm_ctrl_reg->value, 0, 32, etm->control);
1352 etm_store_reg(etm_ctrl_reg);
1354 /* invalidate old trace data */
1355 etm->capture_status = TRACE_IDLE;
1356 if (etm->trace_depth > 0)
1358 free(etm->trace_data);
1359 etm->trace_data = NULL;
1361 etm->trace_depth = 0;
1364 #undef TRACEMODE_MASK
1369 COMMAND_HANDLER(handle_etm_config_command)
1371 struct target *target;
1373 uint32_t portmode = 0x0;
1374 struct etm_context *etm_ctx;
1378 return ERROR_COMMAND_SYNTAX_ERROR;
1380 target = get_target(CMD_ARGV[0]);
1383 LOG_ERROR("target '%s' not defined", CMD_ARGV[0]);
1387 arm = target_to_arm(target);
1389 command_print(CMD_CTX, "target '%s' is '%s'; not an ARM",
1390 target_name(target),
1391 target_type_name(target));
1395 /* FIXME for ETMv3.0 and above -- and we don't yet know what ETM
1396 * version we'll be using!! -- so we can't know how to validate
1397 * params yet. "etm config" should likely be *AFTER* hookup...
1399 * - Many more widths might be supported ... and we can easily
1400 * check whether our setting "took".
1402 * - The "clock" and "mode" bits are interpreted differently.
1403 * See ARM IHI 0014O table 2-17 for the old behavior, and
1404 * table 2-18 for the new. With ETB it's best to specify
1408 COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], port_width);
1411 /* before ETMv3.0 */
1413 portmode |= ETM_PORT_4BIT;
1416 portmode |= ETM_PORT_8BIT;
1419 portmode |= ETM_PORT_16BIT;
1421 /* ETMv3.0 and later*/
1423 portmode |= ETM_PORT_24BIT;
1426 portmode |= ETM_PORT_32BIT;
1429 portmode |= ETM_PORT_48BIT;
1432 portmode |= ETM_PORT_64BIT;
1435 portmode |= ETM_PORT_1BIT;
1438 portmode |= ETM_PORT_2BIT;
1441 command_print(CMD_CTX,
1442 "unsupported ETM port width '%s'", CMD_ARGV[1]);
1446 if (strcmp("normal", CMD_ARGV[2]) == 0)
1448 portmode |= ETM_PORT_NORMAL;
1450 else if (strcmp("multiplexed", CMD_ARGV[2]) == 0)
1452 portmode |= ETM_PORT_MUXED;
1454 else if (strcmp("demultiplexed", CMD_ARGV[2]) == 0)
1456 portmode |= ETM_PORT_DEMUXED;
1460 command_print(CMD_CTX, "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", CMD_ARGV[2]);
1464 if (strcmp("half", CMD_ARGV[3]) == 0)
1466 portmode |= ETM_PORT_HALF_CLOCK;
1468 else if (strcmp("full", CMD_ARGV[3]) == 0)
1470 portmode |= ETM_PORT_FULL_CLOCK;
1474 command_print(CMD_CTX, "unsupported ETM port clocking '%s', must be 'full' or 'half'", CMD_ARGV[3]);
1478 etm_ctx = calloc(1, sizeof(struct etm_context));
1480 LOG_DEBUG("out of memory");
1484 for (i = 0; etm_capture_drivers[i]; i++)
1486 if (strcmp(CMD_ARGV[4], etm_capture_drivers[i]->name) == 0)
1488 int retval = register_commands(CMD_CTX, NULL,
1489 etm_capture_drivers[i]->commands);
1490 if (ERROR_OK != retval)
1496 etm_ctx->capture_driver = etm_capture_drivers[i];
1502 if (!etm_capture_drivers[i])
1504 /* no supported capture driver found, don't register an ETM */
1506 LOG_ERROR("trace capture driver '%s' not found", CMD_ARGV[4]);
1510 etm_ctx->target = target;
1511 etm_ctx->trace_data = NULL;
1512 etm_ctx->control = portmode;
1513 etm_ctx->core_state = ARM_STATE_ARM;
1517 return etm_register_user_commands(CMD_CTX);
1520 COMMAND_HANDLER(handle_etm_info_command)
1522 struct target *target;
1524 struct etm_context *etm;
1525 struct reg *etm_sys_config_reg;
1529 target = get_current_target(CMD_CTX);
1530 arm = target_to_arm(target);
1533 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1540 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1544 command_print(CMD_CTX, "ETM v%d.%d",
1545 etm->bcd_vers >> 4, etm->bcd_vers & 0xf);
1546 command_print(CMD_CTX, "pairs of address comparators: %i",
1547 (int) (etm->config >> 0) & 0x0f);
1548 command_print(CMD_CTX, "data comparators: %i",
1549 (int) (etm->config >> 4) & 0x0f);
1550 command_print(CMD_CTX, "memory map decoders: %i",
1551 (int) (etm->config >> 8) & 0x1f);
1552 command_print(CMD_CTX, "number of counters: %i",
1553 (int) (etm->config >> 13) & 0x07);
1554 command_print(CMD_CTX, "sequencer %spresent",
1555 (int) (etm->config & (1 << 16)) ? "" : "not ");
1556 command_print(CMD_CTX, "number of ext. inputs: %i",
1557 (int) (etm->config >> 17) & 0x07);
1558 command_print(CMD_CTX, "number of ext. outputs: %i",
1559 (int) (etm->config >> 20) & 0x07);
1560 command_print(CMD_CTX, "FIFO full %spresent",
1561 (int) (etm->config & (1 << 23)) ? "" : "not ");
1562 if (etm->bcd_vers < 0x20)
1563 command_print(CMD_CTX, "protocol version: %i",
1564 (int) (etm->config >> 28) & 0x07);
1566 command_print(CMD_CTX,
1567 "coprocessor and memory access %ssupported",
1568 (etm->config & (1 << 26)) ? "" : "not ");
1569 command_print(CMD_CTX, "trace start/stop %spresent",
1570 (etm->config & (1 << 26)) ? "" : "not ");
1571 command_print(CMD_CTX, "number of context comparators: %i",
1572 (int) (etm->config >> 24) & 0x03);
1575 /* SYS_CONFIG isn't present before ETMv1.2 */
1576 etm_sys_config_reg = etm_reg_lookup(etm, ETM_SYS_CONFIG);
1577 if (!etm_sys_config_reg)
1580 etm_get_reg(etm_sys_config_reg);
1581 config = buf_get_u32(etm_sys_config_reg->value, 0, 32);
1583 LOG_DEBUG("ETM SYS CONFIG %08x", (unsigned) config);
1585 max_port_size = config & 0x7;
1586 if (etm->bcd_vers >= 0x30)
1587 max_port_size |= (config >> 6) & 0x08;
1588 switch (max_port_size)
1590 /* before ETMv3.0 */
1600 /* ETMv3.0 and later*/
1620 LOG_ERROR("Illegal max_port_size");
1623 command_print(CMD_CTX, "max. port size: %i", max_port_size);
1625 if (etm->bcd_vers < 0x30) {
1626 command_print(CMD_CTX, "half-rate clocking %ssupported",
1627 (config & (1 << 3)) ? "" : "not ");
1628 command_print(CMD_CTX, "full-rate clocking %ssupported",
1629 (config & (1 << 4)) ? "" : "not ");
1630 command_print(CMD_CTX, "normal trace format %ssupported",
1631 (config & (1 << 5)) ? "" : "not ");
1632 command_print(CMD_CTX, "multiplex trace format %ssupported",
1633 (config & (1 << 6)) ? "" : "not ");
1634 command_print(CMD_CTX, "demultiplex trace format %ssupported",
1635 (config & (1 << 7)) ? "" : "not ");
1637 /* REVISIT show which size and format are selected ... */
1638 command_print(CMD_CTX, "current port size %ssupported",
1639 (config & (1 << 10)) ? "" : "not ");
1640 command_print(CMD_CTX, "current trace format %ssupported",
1641 (config & (1 << 11)) ? "" : "not ");
1643 if (etm->bcd_vers >= 0x21)
1644 command_print(CMD_CTX, "fetch comparisons %ssupported",
1645 (config & (1 << 17)) ? "not " : "");
1646 command_print(CMD_CTX, "FIFO full %ssupported",
1647 (config & (1 << 8)) ? "" : "not ");
1652 COMMAND_HANDLER(handle_etm_status_command)
1654 struct target *target;
1656 struct etm_context *etm;
1657 trace_status_t trace_status;
1659 target = get_current_target(CMD_CTX);
1660 arm = target_to_arm(target);
1663 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1670 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1675 if (etm->bcd_vers >= 0x11) {
1678 reg = etm_reg_lookup(etm, ETM_STATUS);
1681 if (etm_get_reg(reg) == ERROR_OK) {
1682 unsigned s = buf_get_u32(reg->value, 0, reg->size);
1684 command_print(CMD_CTX, "etm: %s%s%s%s",
1685 /* bit(1) == progbit */
1686 (etm->bcd_vers >= 0x12)
1688 ? "disabled" : "enabled")
1690 ((s & (1 << 3)) && etm->bcd_vers >= 0x31)
1691 ? " triggered" : "",
1692 ((s & (1 << 2)) && etm->bcd_vers >= 0x12)
1693 ? " start/stop" : "",
1694 ((s & (1 << 0)) && etm->bcd_vers >= 0x11)
1695 ? " untraced-overflow" : "");
1696 } /* else ignore and try showing trace port status */
1699 /* Trace Port Driver status */
1700 trace_status = etm->capture_driver->status(etm);
1701 if (trace_status == TRACE_IDLE)
1703 command_print(CMD_CTX, "%s: idle", etm->capture_driver->name);
1707 static char *completed = " completed";
1708 static char *running = " is running";
1709 static char *overflowed = ", overflowed";
1710 static char *triggered = ", triggered";
1712 command_print(CMD_CTX, "%s: trace collection%s%s%s",
1713 etm->capture_driver->name,
1714 (trace_status & TRACE_RUNNING) ? running : completed,
1715 (trace_status & TRACE_OVERFLOWED) ? overflowed : "",
1716 (trace_status & TRACE_TRIGGERED) ? triggered : "");
1718 if (etm->trace_depth > 0)
1720 command_print(CMD_CTX, "%i frames of trace data read",
1721 (int)(etm->trace_depth));
1728 COMMAND_HANDLER(handle_etm_image_command)
1730 struct target *target;
1732 struct etm_context *etm_ctx;
1736 command_print(CMD_CTX, "usage: etm image <file> [base address] [type]");
1740 target = get_current_target(CMD_CTX);
1741 arm = target_to_arm(target);
1744 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1751 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1757 image_close(etm_ctx->image);
1758 free(etm_ctx->image);
1759 command_print(CMD_CTX, "previously loaded image found and closed");
1762 etm_ctx->image = malloc(sizeof(struct image));
1763 etm_ctx->image->base_address_set = 0;
1764 etm_ctx->image->start_address_set = 0;
1766 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1769 etm_ctx->image->base_address_set = 1;
1770 COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], etm_ctx->image->base_address);
1774 etm_ctx->image->base_address_set = 0;
1777 if (image_open(etm_ctx->image, CMD_ARGV[0], (CMD_ARGC >= 3) ? CMD_ARGV[2] : NULL) != ERROR_OK)
1779 free(etm_ctx->image);
1780 etm_ctx->image = NULL;
1787 COMMAND_HANDLER(handle_etm_dump_command)
1790 struct target *target;
1792 struct etm_context *etm_ctx;
1797 command_print(CMD_CTX, "usage: etm dump <file>");
1801 target = get_current_target(CMD_CTX);
1802 arm = target_to_arm(target);
1805 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1812 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1816 if (etm_ctx->capture_driver->status == TRACE_IDLE)
1818 command_print(CMD_CTX, "trace capture wasn't enabled, no trace data captured");
1822 if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1824 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1825 command_print(CMD_CTX, "trace capture not completed");
1829 /* read the trace data if it wasn't read already */
1830 if (etm_ctx->trace_depth == 0)
1831 etm_ctx->capture_driver->read_trace(etm_ctx);
1833 if (fileio_open(&file, CMD_ARGV[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1838 fileio_write_u32(&file, etm_ctx->capture_status);
1839 fileio_write_u32(&file, etm_ctx->control);
1840 fileio_write_u32(&file, etm_ctx->trace_depth);
1842 for (i = 0; i < etm_ctx->trace_depth; i++)
1844 fileio_write_u32(&file, etm_ctx->trace_data[i].pipestat);
1845 fileio_write_u32(&file, etm_ctx->trace_data[i].packet);
1846 fileio_write_u32(&file, etm_ctx->trace_data[i].flags);
1849 fileio_close(&file);
1854 COMMAND_HANDLER(handle_etm_load_command)
1857 struct target *target;
1859 struct etm_context *etm_ctx;
1864 command_print(CMD_CTX, "usage: etm load <file>");
1868 target = get_current_target(CMD_CTX);
1869 arm = target_to_arm(target);
1872 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1879 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1883 if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1885 command_print(CMD_CTX, "trace capture running, stop first");
1889 if (fileio_open(&file, CMD_ARGV[0], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1896 command_print(CMD_CTX, "size isn't a multiple of 4, no valid trace data");
1897 fileio_close(&file);
1901 if (etm_ctx->trace_depth > 0)
1903 free(etm_ctx->trace_data);
1904 etm_ctx->trace_data = NULL;
1909 fileio_read_u32(&file, &tmp); etm_ctx->capture_status = tmp;
1910 fileio_read_u32(&file, &tmp); etm_ctx->control = tmp;
1911 fileio_read_u32(&file, &etm_ctx->trace_depth);
1913 etm_ctx->trace_data = malloc(sizeof(struct etmv1_trace_data) * etm_ctx->trace_depth);
1914 if (etm_ctx->trace_data == NULL)
1916 command_print(CMD_CTX, "not enough memory to perform operation");
1917 fileio_close(&file);
1921 for (i = 0; i < etm_ctx->trace_depth; i++)
1923 uint32_t pipestat, packet, flags;
1924 fileio_read_u32(&file, &pipestat);
1925 fileio_read_u32(&file, &packet);
1926 fileio_read_u32(&file, &flags);
1927 etm_ctx->trace_data[i].pipestat = pipestat & 0xff;
1928 etm_ctx->trace_data[i].packet = packet & 0xffff;
1929 etm_ctx->trace_data[i].flags = flags;
1932 fileio_close(&file);
1937 COMMAND_HANDLER(handle_etm_start_command)
1939 struct target *target;
1941 struct etm_context *etm_ctx;
1942 struct reg *etm_ctrl_reg;
1944 target = get_current_target(CMD_CTX);
1945 arm = target_to_arm(target);
1948 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1955 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1959 /* invalidate old tracing data */
1960 etm_ctx->capture_status = TRACE_IDLE;
1961 if (etm_ctx->trace_depth > 0)
1963 free(etm_ctx->trace_data);
1964 etm_ctx->trace_data = NULL;
1966 etm_ctx->trace_depth = 0;
1968 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
1972 etm_get_reg(etm_ctrl_reg);
1974 /* Clear programming bit (10), set port selection bit (11) */
1975 buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x2);
1977 etm_store_reg(etm_ctrl_reg);
1978 jtag_execute_queue();
1980 etm_ctx->capture_driver->start_capture(etm_ctx);
1985 COMMAND_HANDLER(handle_etm_stop_command)
1987 struct target *target;
1989 struct etm_context *etm_ctx;
1990 struct reg *etm_ctrl_reg;
1992 target = get_current_target(CMD_CTX);
1993 arm = target_to_arm(target);
1996 command_print(CMD_CTX, "ETM: current target isn't an ARM");
2003 command_print(CMD_CTX, "current target doesn't have an ETM configured");
2007 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
2011 etm_get_reg(etm_ctrl_reg);
2013 /* Set programming bit (10), clear port selection bit (11) */
2014 buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x1);
2016 etm_store_reg(etm_ctrl_reg);
2017 jtag_execute_queue();
2019 etm_ctx->capture_driver->stop_capture(etm_ctx);
2024 COMMAND_HANDLER(handle_etm_trigger_debug_command)
2026 struct target *target;
2028 struct etm_context *etm;
2030 target = get_current_target(CMD_CTX);
2031 arm = target_to_arm(target);
2034 command_print(CMD_CTX, "ETM: %s isn't an ARM",
2035 target_name(target));
2042 command_print(CMD_CTX, "ETM: no ETM configured for %s",
2043 target_name(target));
2047 if (CMD_ARGC == 1) {
2048 struct reg *etm_ctrl_reg;
2051 etm_ctrl_reg = etm_reg_lookup(etm, ETM_CTRL);
2055 COMMAND_PARSE_ENABLE(CMD_ARGV[0], dbgrq);
2057 etm->control |= ETM_CTRL_DBGRQ;
2059 etm->control &= ~ETM_CTRL_DBGRQ;
2061 /* etm->control will be written to hardware
2062 * the next time an "etm start" is issued.
2064 buf_set_u32(etm_ctrl_reg->value, 0, 32, etm->control);
2067 command_print(CMD_CTX, "ETM: %s debug halt",
2068 (etm->control & ETM_CTRL_DBGRQ)
2070 : "does not trigger");
2074 COMMAND_HANDLER(handle_etm_analyze_command)
2076 struct target *target;
2078 struct etm_context *etm_ctx;
2081 target = get_current_target(CMD_CTX);
2082 arm = target_to_arm(target);
2085 command_print(CMD_CTX, "ETM: current target isn't an ARM");
2092 command_print(CMD_CTX, "current target doesn't have an ETM configured");
2096 if ((retval = etmv1_analyze_trace(etm_ctx, CMD_CTX)) != ERROR_OK)
2100 case ERROR_ETM_ANALYSIS_FAILED:
2101 command_print(CMD_CTX, "further analysis failed (corrupted trace data or just end of data");
2103 case ERROR_TRACE_INSTRUCTION_UNAVAILABLE:
2104 command_print(CMD_CTX, "no instruction for current address available, analysis aborted");
2106 case ERROR_TRACE_IMAGE_UNAVAILABLE:
2107 command_print(CMD_CTX, "no image available for trace analysis");
2110 command_print(CMD_CTX, "unknown error: %i", retval);
2117 static const struct command_registration etm_config_command_handlers[] = {
2119 /* NOTE: with ADIv5, ETMs are accessed by DAP operations,
2120 * possibly over SWD, not JTAG scanchain 6 of 'target'.
2122 * Also, these parameters don't match ETM v3+ modules...
2125 .handler = handle_etm_config_command,
2126 .mode = COMMAND_CONFIG,
2127 .help = "Set up ETM output port.",
2128 .usage = "target port_width port_mode clocking capture_driver",
2130 COMMAND_REGISTRATION_DONE
2132 const struct command_registration etm_command_handlers[] = {
2135 .mode = COMMAND_ANY,
2136 .help = "Emebdded Trace Macrocell command group",
2137 .chain = etm_config_command_handlers,
2139 COMMAND_REGISTRATION_DONE
2142 static const struct command_registration etm_exec_command_handlers[] = {
2144 .name = "tracemode",
2145 .handler = handle_etm_tracemode_command,
2146 .mode = COMMAND_EXEC,
2147 .help = "configure/display trace mode",
2148 .usage = "('none'|'data'|'address'|'all') "
2150 "['enable'|'disable'] "
2151 "['enable'|'disable']",
2155 .handler = handle_etm_info_command,
2156 .mode = COMMAND_EXEC,
2157 .help = "display info about the current target's ETM",
2161 .handler = handle_etm_status_command,
2162 .mode = COMMAND_EXEC,
2163 .help = "display current target's ETM status",
2167 .handler = handle_etm_start_command,
2168 .mode = COMMAND_EXEC,
2169 .help = "start ETM trace collection",
2173 .handler = handle_etm_stop_command,
2174 .mode = COMMAND_EXEC,
2175 .help = "stop ETM trace collection",
2178 .name = "trigger_debug",
2179 .handler = handle_etm_trigger_debug_command,
2180 .mode = COMMAND_EXEC,
2181 .help = "enable/disable debug entry on trigger",
2182 .usage = "['enable'|'disable']",
2186 .handler = handle_etm_analyze_command,
2187 .mode = COMMAND_EXEC,
2188 .help = "analyze collected ETM trace",
2192 .handler = handle_etm_image_command,
2193 .mode = COMMAND_EXEC,
2194 .help = "load image from file with optional offset",
2195 .usage = "filename [offset]",
2199 .handler = handle_etm_dump_command,
2200 .mode = COMMAND_EXEC,
2201 .help = "dump captured trace data to file",
2202 .usage = "filename",
2206 .handler = handle_etm_load_command,
2207 .mode = COMMAND_EXEC,
2208 .help = "load trace data for analysis <file>",
2210 COMMAND_REGISTRATION_DONE
2213 static int etm_register_user_commands(struct command_context *cmd_ctx)
2215 struct command *etm_cmd = command_find_in_context(cmd_ctx, "etm");
2216 return register_commands(cmd_ctx, etm_cmd, etm_exec_command_handlers);