1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
28 #include "arm_disassembler.h"
30 #include "etm_dummy.h"
32 #if BUILD_OOCD_TRACE == 1
33 #include "oocd_trace.h"
38 * ARM "Embedded Trace Macrocell" (ETM) support -- direct JTAG access.
40 * ETM modules collect instruction and/or data trace information, compress
41 * it, and transfer it to a debugging host through either a (buffered) trace
42 * port (often a 38-pin Mictor connector) or an Embedded Trace Buffer (ETB).
44 * There are several generations of these modules. Original versions have
45 * JTAG access through a dedicated scan chain. Recent versions have added
46 * access via coprocessor instructions, memory addressing, and the ARM Debug
47 * Interface v5 (ADIv5); and phased out direct JTAG access.
49 * This code supports up to the ETMv1.3 architecture, as seen in ETM9 and
50 * most common ARM9 systems. Note: "CoreSight ETM9" implements ETMv3.2,
51 * implying non-JTAG connectivity options.
53 * Relevant documentation includes:
54 * ARM DDI 0157G ... ETM9 (r2p2) Technical Reference Manual
55 * ARM DDI 0315B ... CoreSight ETM9 (r0p1) Technical Reference Manual
56 * ARM IHI 0014O ... Embedded Trace Macrocell, Architecture Specification
67 uint8_t size; /* low-N of 32 bits */
68 uint8_t mode; /* RO, WO, RW */
69 uint8_t bcd_vers; /* 1.0, 2.0, etc */
74 * Registers 0..0x7f are JTAG-addressable using scanchain 6.
75 * (Or on some processors, through coprocessor operations.)
76 * Newer versions of ETM make some W/O registers R/W, and
77 * provide definitions for some previously-unused bits.
80 /* core registers used to version/configure the ETM */
81 static const struct etm_reg_info etm_core[] = {
82 /* NOTE: we "know" the order here ... */
83 { ETM_CONFIG, 32, RO, 0x10, "ETM_config", },
84 { ETM_ID, 32, RO, 0x20, "ETM_id", },
87 /* basic registers that are always there given the right ETM version */
88 static const struct etm_reg_info etm_basic[] = {
89 /* ETM Trace Registers */
90 { ETM_CTRL, 32, RW, 0x10, "ETM_ctrl", },
91 { ETM_TRIG_EVENT, 17, WO, 0x10, "ETM_trig_event", },
92 { ETM_ASIC_CTRL, 8, WO, 0x10, "ETM_asic_ctrl", },
93 { ETM_STATUS, 3, RO, 0x11, "ETM_status", },
94 { ETM_SYS_CONFIG, 9, RO, 0x12, "ETM_sys_config", },
96 /* TraceEnable configuration */
97 { ETM_TRACE_RESOURCE_CTRL, 32, WO, 0x12, "ETM_trace_resource_ctrl", },
98 { ETM_TRACE_EN_CTRL2, 16, WO, 0x12, "ETM_trace_en_ctrl2", },
99 { ETM_TRACE_EN_EVENT, 17, WO, 0x10, "ETM_trace_en_event", },
100 { ETM_TRACE_EN_CTRL1, 26, WO, 0x10, "ETM_trace_en_ctrl1", },
102 /* ViewData configuration (data trace) */
103 { ETM_VIEWDATA_EVENT, 17, WO, 0x10, "ETM_viewdata_event", },
104 { ETM_VIEWDATA_CTRL1, 32, WO, 0x10, "ETM_viewdata_ctrl1", },
105 { ETM_VIEWDATA_CTRL2, 32, WO, 0x10, "ETM_viewdata_ctrl2", },
106 { ETM_VIEWDATA_CTRL3, 17, WO, 0x10, "ETM_viewdata_ctrl3", },
108 /* REVISIT exclude VIEWDATA_CTRL2 when it's not there */
110 { 0x78, 12, WO, 0x20, "ETM_sync_freq", },
111 { 0x7a, 22, RO, 0x31, "ETM_config_code_ext", },
112 { 0x7b, 32, WO, 0x31, "ETM_ext_input_select", },
113 { 0x7c, 32, WO, 0x34, "ETM_trace_start_stop", },
114 { 0x7d, 8, WO, 0x34, "ETM_behavior_control", },
117 static const struct etm_reg_info etm_fifofull[] = {
118 /* FIFOFULL configuration */
119 { ETM_FIFOFULL_REGION, 25, WO, 0x10, "ETM_fifofull_region", },
120 { ETM_FIFOFULL_LEVEL, 8, WO, 0x10, "ETM_fifofull_level", },
123 static const struct etm_reg_info etm_addr_comp[] = {
124 /* Address comparator register pairs */
125 #define ADDR_COMPARATOR(i) \
126 { ETM_ADDR_COMPARATOR_VALUE + (i) - 1, 32, WO, 0x10, \
127 "ETM_addr_" #i "_comparator_value", }, \
128 { ETM_ADDR_ACCESS_TYPE + (i) - 1, 7, WO, 0x10, \
129 "ETM_addr_" #i "_access_type", }
147 #undef ADDR_COMPARATOR
150 static const struct etm_reg_info etm_data_comp[] = {
151 /* Data Value Comparators (NOTE: odd addresses are reserved) */
152 #define DATA_COMPARATOR(i) \
153 { ETM_DATA_COMPARATOR_VALUE + 2*(i) - 1, 32, WO, 0x10, \
154 "ETM_data_" #i "_comparator_value", }, \
155 { ETM_DATA_COMPARATOR_MASK + 2*(i) - 1, 32, WO, 0x10, \
156 "ETM_data_" #i "_comparator_mask", }
165 #undef DATA_COMPARATOR
168 static const struct etm_reg_info etm_counters[] = {
169 #define ETM_COUNTER(i) \
170 { ETM_COUNTER_RELOAD_VALUE + (i) - 1, 16, WO, 0x10, \
171 "ETM_counter_" #i "_reload_value", }, \
172 { ETM_COUNTER_ENABLE + (i) - 1, 18, WO, 0x10, \
173 "ETM_counter_" #i "_enable", }, \
174 { ETM_COUNTER_RELOAD_EVENT + (i) - 1, 17, WO, 0x10, \
175 "ETM_counter_" #i "_reload_event", }, \
176 { ETM_COUNTER_VALUE + (i) - 1, 16, RO, 0x10, \
177 "ETM_counter_" #i "_value", }
185 static const struct etm_reg_info etm_sequencer[] = {
187 { ETM_SEQUENCER_EVENT + (i), 17, WO, 0x10, \
188 "ETM_sequencer_event" #i, }
189 ETM_SEQ(0), /* 1->2 */
190 ETM_SEQ(1), /* 2->1 */
191 ETM_SEQ(2), /* 2->3 */
192 ETM_SEQ(3), /* 3->1 */
193 ETM_SEQ(4), /* 3->2 */
194 ETM_SEQ(5), /* 1->3 */
197 { ETM_SEQUENCER_STATE, 2, RO, 0x10, "ETM_sequencer_state", },
200 static const struct etm_reg_info etm_outputs[] = {
201 #define ETM_OUTPUT(i) \
202 { ETM_EXTERNAL_OUTPUT + (i) - 1, 17, WO, 0x10, \
203 "ETM_external_output" #i, }
213 /* registers from 0x6c..0x7f were added after ETMv1.3 */
215 /* Context ID Comparators */
216 { 0x6c, 32, RO, 0x20, "ETM_contextid_comparator_value1", }
217 { 0x6d, 32, RO, 0x20, "ETM_contextid_comparator_value2", }
218 { 0x6e, 32, RO, 0x20, "ETM_contextid_comparator_value3", }
219 { 0x6f, 32, RO, 0x20, "ETM_contextid_comparator_mask", }
222 static int etm_get_reg(struct reg *reg);
223 static int etm_read_reg_w_check(struct reg *reg,
224 uint8_t* check_value, uint8_t* check_mask);
225 static int etm_register_user_commands(struct command_context *cmd_ctx);
226 static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf);
227 static int etm_write_reg(struct reg *reg, uint32_t value);
229 static const struct reg_arch_type etm_scan6_type = {
231 .set = etm_set_reg_w_exec,
234 /* Look up register by ID ... most ETM instances only
235 * support a subset of the possible registers.
237 static struct reg *etm_reg_lookup(struct etm_context *etm_ctx, unsigned id)
239 struct reg_cache *cache = etm_ctx->reg_cache;
242 for (i = 0; i < cache->num_regs; i++) {
243 struct etm_reg *reg = cache->reg_list[i].arch_info;
245 if (reg->reg_info->addr == id)
246 return &cache->reg_list[i];
249 /* caller asking for nonexistent register is a bug! */
250 /* REVISIT say which of the N targets was involved */
251 LOG_ERROR("ETM: register 0x%02x not available", id);
255 static void etm_reg_add(unsigned bcd_vers, struct arm_jtag *jtag_info,
256 struct reg_cache *cache, struct etm_reg *ereg,
257 const struct etm_reg_info *r, unsigned nreg)
259 struct reg *reg = cache->reg_list;
261 reg += cache->num_regs;
262 ereg += cache->num_regs;
264 /* add up to "nreg" registers from "r", if supported by this
265 * version of the ETM, to the specified cache.
267 for (; nreg--; r++) {
269 /* this ETM may be too old to have some registers */
270 if (r->bcd_vers > bcd_vers)
275 reg->value = &ereg->value;
276 reg->arch_info = ereg;
277 reg->type = &etm_scan6_type;
282 ereg->jtag_info = jtag_info;
287 struct reg_cache *etm_build_reg_cache(struct target *target,
288 struct arm_jtag *jtag_info, struct etm_context *etm_ctx)
290 struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
291 struct reg *reg_list = NULL;
292 struct etm_reg *arch_info = NULL;
293 unsigned bcd_vers, config;
295 /* the actual registers are kept in two arrays */
296 reg_list = calloc(128, sizeof(struct reg));
297 arch_info = calloc(128, sizeof(struct etm_reg));
299 /* fill in values for the reg cache */
300 reg_cache->name = "etm registers";
301 reg_cache->next = NULL;
302 reg_cache->reg_list = reg_list;
303 reg_cache->num_regs = 0;
305 /* add ETM_CONFIG, then parse its values to see
306 * which other registers exist in this ETM
308 etm_reg_add(0x10, jtag_info, reg_cache, arch_info,
311 etm_get_reg(reg_list);
312 etm_ctx->config = buf_get_u32((void *)&arch_info->value, 0, 32);
313 config = etm_ctx->config;
315 /* figure ETM version then add base registers */
316 if (config & (1 << 31)) {
318 LOG_WARNING("ETMv2+ support is incomplete");
320 /* REVISIT more registers may exist; they may now be
321 * readable; more register bits have defined meanings;
322 * don't presume trace start/stop support is present;
323 * and include any context ID comparator registers.
325 etm_reg_add(0x20, jtag_info, reg_cache, arch_info,
327 etm_get_reg(reg_list + 1);
328 etm_ctx->id = buf_get_u32(
329 (void *)&arch_info[1].value, 0, 32);
330 LOG_DEBUG("ETM ID: %08x", (unsigned) etm_ctx->id);
331 bcd_vers = 0x10 + (((etm_ctx->id) >> 4) & 0xff);
334 switch (config >> 28) {
351 LOG_WARNING("Bad ETMv1 protocol %d", config >> 28);
355 etm_ctx->bcd_vers = bcd_vers;
356 LOG_INFO("ETM v%d.%d", bcd_vers >> 4, bcd_vers & 0xf);
358 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
359 etm_basic, ARRAY_SIZE(etm_basic));
361 /* address and data comparators; counters; outputs */
362 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
363 etm_addr_comp, 4 * (0x0f & (config >> 0)));
364 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
365 etm_data_comp, 2 * (0x0f & (config >> 4)));
366 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
367 etm_counters, 4 * (0x07 & (config >> 13)));
368 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
369 etm_outputs, (0x07 & (config >> 20)));
371 /* FIFOFULL presence is optional
372 * REVISIT for ETMv1.2 and later, don't bother adding this
373 * unless ETM_SYS_CONFIG says it's also *supported* ...
375 if (config & (1 << 23))
376 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
377 etm_fifofull, ARRAY_SIZE(etm_fifofull));
379 /* sequencer is optional (for state-dependant triggering) */
380 if (config & (1 << 16))
381 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
382 etm_sequencer, ARRAY_SIZE(etm_sequencer));
384 /* REVISIT could realloc and likely save half the memory
385 * in the two chunks we allocated...
388 /* the ETM might have an ETB connected */
389 if (strcmp(etm_ctx->capture_driver->name, "etb") == 0)
391 struct etb *etb = etm_ctx->capture_driver_priv;
395 LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
399 reg_cache->next = etb_build_reg_cache(etb);
401 etb->reg_cache = reg_cache->next;
404 etm_ctx->reg_cache = reg_cache;
414 static int etm_read_reg(struct reg *reg)
416 return etm_read_reg_w_check(reg, NULL, NULL);
419 static int etm_store_reg(struct reg *reg)
421 return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
424 int etm_setup(struct target *target)
427 uint32_t etm_ctrl_value;
428 struct arm *arm = target_to_arm(target);
429 struct etm_context *etm_ctx = arm->etm;
430 struct reg *etm_ctrl_reg;
432 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
436 /* initialize some ETM control register settings */
437 etm_get_reg(etm_ctrl_reg);
438 etm_ctrl_value = buf_get_u32(etm_ctrl_reg->value, 0, 32);
440 /* clear the ETM powerdown bit (0) */
441 etm_ctrl_value &= ~ETM_CTRL_POWERDOWN;
443 /* configure port width (21,6:4), mode (13,17:16) and
444 * for older modules clocking (13)
446 etm_ctrl_value = (etm_ctrl_value
447 & ~ETM_PORT_WIDTH_MASK
448 & ~ETM_PORT_MODE_MASK
450 & ~ETM_PORT_CLOCK_MASK)
453 buf_set_u32(etm_ctrl_reg->value, 0, 32, etm_ctrl_value);
454 etm_store_reg(etm_ctrl_reg);
456 etm_ctx->control = etm_ctrl_value;
458 if ((retval = jtag_execute_queue()) != ERROR_OK)
461 /* REVISIT for ETMv3.0 and later, read ETM_sys_config to
462 * verify that those width and mode settings are OK ...
465 if ((retval = etm_ctx->capture_driver->init(etm_ctx)) != ERROR_OK)
467 LOG_ERROR("ETM capture driver initialization failed");
473 static int etm_get_reg(struct reg *reg)
477 if ((retval = etm_read_reg(reg)) != ERROR_OK)
479 LOG_ERROR("BUG: error scheduling etm register read");
483 if ((retval = jtag_execute_queue()) != ERROR_OK)
485 LOG_ERROR("register read failed");
492 static int etm_read_reg_w_check(struct reg *reg,
493 uint8_t* check_value, uint8_t* check_mask)
495 struct etm_reg *etm_reg = reg->arch_info;
496 const struct etm_reg_info *r = etm_reg->reg_info;
497 uint8_t reg_addr = r->addr & 0x7f;
498 struct scan_field fields[3];
500 if (etm_reg->reg_info->mode == WO) {
501 LOG_ERROR("BUG: can't read write-only register %s", r->name);
502 return ERROR_INVALID_ARGUMENTS;
505 LOG_DEBUG("%s (%u)", r->name, reg_addr);
507 jtag_set_end_state(TAP_IDLE);
508 arm_jtag_scann(etm_reg->jtag_info, 0x6, TAP_IDLE);
509 arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
511 fields[0].num_bits = 32;
512 fields[0].out_value = reg->value;
513 fields[0].in_value = NULL;
514 fields[0].check_value = NULL;
515 fields[0].check_mask = NULL;
517 fields[1].num_bits = 7;
518 fields[1].out_value = malloc(1);
519 buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
520 fields[1].in_value = NULL;
521 fields[1].check_value = NULL;
522 fields[1].check_mask = NULL;
524 fields[2].num_bits = 1;
525 fields[2].out_value = malloc(1);
526 buf_set_u32(fields[2].out_value, 0, 1, 0);
527 fields[2].in_value = NULL;
528 fields[2].check_value = NULL;
529 fields[2].check_mask = NULL;
531 jtag_add_dr_scan(etm_reg->jtag_info->tap, 3, fields, TAP_IDLE);
533 fields[0].in_value = reg->value;
534 fields[0].check_value = check_value;
535 fields[0].check_mask = check_mask;
537 jtag_add_dr_scan_check(etm_reg->jtag_info->tap, 3, fields, TAP_IDLE);
539 free(fields[1].out_value);
540 free(fields[2].out_value);
545 static int etm_set_reg(struct reg *reg, uint32_t value)
549 if ((retval = etm_write_reg(reg, value)) != ERROR_OK)
551 LOG_ERROR("BUG: error scheduling etm register write");
555 buf_set_u32(reg->value, 0, reg->size, value);
562 static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf)
566 etm_set_reg(reg, buf_get_u32(buf, 0, reg->size));
568 if ((retval = jtag_execute_queue()) != ERROR_OK)
570 LOG_ERROR("register write failed");
576 static int etm_write_reg(struct reg *reg, uint32_t value)
578 struct etm_reg *etm_reg = reg->arch_info;
579 const struct etm_reg_info *r = etm_reg->reg_info;
580 uint8_t reg_addr = r->addr & 0x7f;
581 struct scan_field fields[3];
583 if (etm_reg->reg_info->mode == RO) {
584 LOG_ERROR("BUG: can't write read--only register %s", r->name);
585 return ERROR_INVALID_ARGUMENTS;
588 LOG_DEBUG("%s (%u): 0x%8.8" PRIx32 "", r->name, reg_addr, value);
590 jtag_set_end_state(TAP_IDLE);
591 arm_jtag_scann(etm_reg->jtag_info, 0x6, TAP_IDLE);
592 arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
594 fields[0].num_bits = 32;
596 fields[0].out_value = tmp1;
597 buf_set_u32(fields[0].out_value, 0, 32, value);
598 fields[0].in_value = NULL;
600 fields[1].num_bits = 7;
602 fields[1].out_value = &tmp2;
603 buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
604 fields[1].in_value = NULL;
606 fields[2].num_bits = 1;
608 fields[2].out_value = &tmp3;
609 buf_set_u32(fields[2].out_value, 0, 1, 1);
610 fields[2].in_value = NULL;
612 jtag_add_dr_scan(etm_reg->jtag_info->tap, 3, fields, TAP_IDLE);
618 /* ETM trace analysis functionality */
620 static struct etm_capture_driver *etm_capture_drivers[] =
623 &etm_dummy_capture_driver,
624 #if BUILD_OOCD_TRACE == 1
625 &oocd_trace_capture_driver,
630 static int etm_read_instruction(struct etm_context *ctx, struct arm_instruction *instruction)
639 return ERROR_TRACE_IMAGE_UNAVAILABLE;
641 /* search for the section the current instruction belongs to */
642 for (i = 0; i < ctx->image->num_sections; i++)
644 if ((ctx->image->sections[i].base_address <= ctx->current_pc) &&
645 (ctx->image->sections[i].base_address + ctx->image->sections[i].size > ctx->current_pc))
654 /* current instruction couldn't be found in the image */
655 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
658 if (ctx->core_state == ARM_STATE_ARM)
661 if ((retval = image_read_section(ctx->image, section,
662 ctx->current_pc - ctx->image->sections[section].base_address,
663 4, buf, &size_read)) != ERROR_OK)
665 LOG_ERROR("error while reading instruction: %i", retval);
666 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
668 opcode = target_buffer_get_u32(ctx->target, buf);
669 arm_evaluate_opcode(opcode, ctx->current_pc, instruction);
671 else if (ctx->core_state == ARM_STATE_THUMB)
674 if ((retval = image_read_section(ctx->image, section,
675 ctx->current_pc - ctx->image->sections[section].base_address,
676 2, buf, &size_read)) != ERROR_OK)
678 LOG_ERROR("error while reading instruction: %i", retval);
679 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
681 opcode = target_buffer_get_u16(ctx->target, buf);
682 thumb_evaluate_opcode(opcode, ctx->current_pc, instruction);
684 else if (ctx->core_state == ARM_STATE_JAZELLE)
686 LOG_ERROR("BUG: tracing of jazelle code not supported");
691 LOG_ERROR("BUG: unknown core state encountered");
698 static int etmv1_next_packet(struct etm_context *ctx, uint8_t *packet, int apo)
700 while (ctx->data_index < ctx->trace_depth)
702 /* if the caller specified an address packet offset, skip until the
703 * we reach the n-th cycle marked with tracesync */
706 if (ctx->trace_data[ctx->data_index].flags & ETMV1_TRACESYNC_CYCLE)
717 /* no tracedata output during a TD cycle
718 * or in a trigger cycle */
719 if ((ctx->trace_data[ctx->data_index].pipestat == STAT_TD)
720 || (ctx->trace_data[ctx->data_index].flags & ETMV1_TRIGGER_CYCLE))
727 /* FIXME there are more port widths than these... */
728 if ((ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_16BIT)
730 if (ctx->data_half == 0)
732 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
737 *packet = (ctx->trace_data[ctx->data_index].packet & 0xff00) >> 8;
742 else if ((ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
744 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
749 /* on a 4-bit port, a packet will be output during two consecutive cycles */
750 if (ctx->data_index > (ctx->trace_depth - 2))
753 *packet = ctx->trace_data[ctx->data_index].packet & 0xf;
754 *packet |= (ctx->trace_data[ctx->data_index + 1].packet & 0xf) << 4;
755 ctx->data_index += 2;
764 static int etmv1_branch_address(struct etm_context *ctx)
772 /* quit analysis if less than two cycles are left in the trace
773 * because we can't extract the APO */
774 if (ctx->data_index > (ctx->trace_depth - 2))
777 /* a BE could be output during an APO cycle, skip the current
778 * and continue with the new one */
779 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x4)
781 if (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x4)
784 /* address packet offset encoded in the next two cycles' pipestat bits */
785 apo = ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x3;
786 apo |= (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x3) << 2;
788 /* count number of tracesync cycles between current pipe_index and data_index
789 * i.e. the number of tracesyncs that data_index already passed by
790 * to subtract them from the APO */
791 for (i = ctx->pipe_index; i < ctx->data_index; i++)
793 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & ETMV1_TRACESYNC_CYCLE)
797 /* extract up to four 7-bit packets */
799 if ((retval = etmv1_next_packet(ctx, &packet, (shift == 0) ? apo + 1 : 0)) != 0)
801 ctx->last_branch &= ~(0x7f << shift);
802 ctx->last_branch |= (packet & 0x7f) << shift;
804 } while ((packet & 0x80) && (shift < 28));
806 /* one last packet holding 4 bits of the address, plus the branch reason code */
807 if ((shift == 28) && (packet & 0x80))
809 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
811 ctx->last_branch &= 0x0fffffff;
812 ctx->last_branch |= (packet & 0x0f) << 28;
813 ctx->last_branch_reason = (packet & 0x70) >> 4;
818 ctx->last_branch_reason = 0;
826 /* if a full address was output, we might have branched into Jazelle state */
827 if ((shift == 32) && (packet & 0x80))
829 ctx->core_state = ARM_STATE_JAZELLE;
833 /* if we didn't branch into Jazelle state, the current processor state is
834 * encoded in bit 0 of the branch target address */
835 if (ctx->last_branch & 0x1)
837 ctx->core_state = ARM_STATE_THUMB;
838 ctx->last_branch &= ~0x1;
842 ctx->core_state = ARM_STATE_ARM;
843 ctx->last_branch &= ~0x3;
850 static int etmv1_data(struct etm_context *ctx, int size, uint32_t *data)
856 for (j = 0; j < size; j++)
858 if ((retval = etmv1_next_packet(ctx, &buf[j], 0)) != 0)
864 LOG_ERROR("TODO: add support for 64-bit values");
868 *data = target_buffer_get_u32(ctx->target, buf);
870 *data = target_buffer_get_u16(ctx->target, buf);
879 static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context *cmd_ctx)
882 struct arm_instruction instruction;
884 /* read the trace data if it wasn't read already */
885 if (ctx->trace_depth == 0)
886 ctx->capture_driver->read_trace(ctx);
888 /* start at the beginning of the captured trace */
893 /* neither the PC nor the data pointer are valid */
897 while (ctx->pipe_index < ctx->trace_depth)
899 uint8_t pipestat = ctx->trace_data[ctx->pipe_index].pipestat;
900 uint32_t next_pc = ctx->current_pc;
901 uint32_t old_data_index = ctx->data_index;
902 uint32_t old_data_half = ctx->data_half;
903 uint32_t old_index = ctx->pipe_index;
904 uint32_t last_instruction = ctx->last_instruction;
906 int current_pc_ok = ctx->pc_ok;
908 if (ctx->trace_data[ctx->pipe_index].flags & ETMV1_TRIGGER_CYCLE)
910 command_print(cmd_ctx, "--- trigger ---");
913 /* instructions execute in IE/D or BE/D cycles */
914 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
915 ctx->last_instruction = ctx->pipe_index;
917 /* if we don't have a valid pc skip until we reach an indirect branch */
918 if ((!ctx->pc_ok) && (pipestat != STAT_BE))
924 /* any indirect branch could have interrupted instruction flow
925 * - the branch reason code could indicate a trace discontinuity
926 * - a branch to the exception vectors indicates an exception
928 if ((pipestat == STAT_BE) || (pipestat == STAT_BD))
930 /* backup current data index, to be able to consume the branch address
931 * before examining data address and values
933 old_data_index = ctx->data_index;
934 old_data_half = ctx->data_half;
936 ctx->last_instruction = ctx->pipe_index;
938 if ((retval = etmv1_branch_address(ctx)) != 0)
940 /* negative return value from etmv1_branch_address means we ran out of packets,
941 * quit analysing the trace */
945 /* a positive return values means the current branch was abandoned,
946 * and a new branch was encountered in cycle ctx->pipe_index + retval;
948 LOG_WARNING("abandoned branch encountered, correctnes of analysis uncertain");
949 ctx->pipe_index += retval;
953 /* skip over APO cycles */
954 ctx->pipe_index += 2;
956 switch (ctx->last_branch_reason)
958 case 0x0: /* normal PC change */
959 next_pc = ctx->last_branch;
961 case 0x1: /* tracing enabled */
962 command_print(cmd_ctx, "--- tracing enabled at 0x%8.8" PRIx32 " ---", ctx->last_branch);
963 ctx->current_pc = ctx->last_branch;
967 case 0x2: /* trace restarted after FIFO overflow */
968 command_print(cmd_ctx, "--- trace restarted after FIFO overflow at 0x%8.8" PRIx32 " ---", ctx->last_branch);
969 ctx->current_pc = ctx->last_branch;
973 case 0x3: /* exit from debug state */
974 command_print(cmd_ctx, "--- exit from debug state at 0x%8.8" PRIx32 " ---", ctx->last_branch);
975 ctx->current_pc = ctx->last_branch;
979 case 0x4: /* periodic synchronization point */
980 next_pc = ctx->last_branch;
981 /* if we had no valid PC prior to this synchronization point,
982 * we have to move on with the next trace cycle
986 command_print(cmd_ctx, "--- periodic synchronization point at 0x%8.8" PRIx32 " ---", next_pc);
987 ctx->current_pc = next_pc;
992 default: /* reserved */
993 LOG_ERROR("BUG: branch reason code 0x%" PRIx32 " is reserved", ctx->last_branch_reason);
997 /* if we got here the branch was a normal PC change
998 * (or a periodic synchronization point, which means the same for that matter)
999 * if we didn't accquire a complete PC continue with the next cycle
1004 /* indirect branch to the exception vector means an exception occured */
1005 if ((ctx->last_branch <= 0x20)
1006 || ((ctx->last_branch >= 0xffff0000) && (ctx->last_branch <= 0xffff0020)))
1008 if ((ctx->last_branch & 0xff) == 0x10)
1010 command_print(cmd_ctx, "data abort");
1014 command_print(cmd_ctx, "exception vector 0x%2.2" PRIx32 "", ctx->last_branch);
1015 ctx->current_pc = ctx->last_branch;
1022 /* an instruction was executed (or not, depending on the condition flags)
1023 * retrieve it from the image for displaying */
1024 if (ctx->pc_ok && (pipestat != STAT_WT) && (pipestat != STAT_TD) &&
1025 !(((pipestat == STAT_BE) || (pipestat == STAT_BD)) &&
1026 ((ctx->last_branch_reason != 0x0) && (ctx->last_branch_reason != 0x4))))
1028 if ((retval = etm_read_instruction(ctx, &instruction)) != ERROR_OK)
1030 /* can't continue tracing with no image available */
1031 if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
1035 else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE)
1037 /* TODO: handle incomplete images
1038 * for now we just quit the analsysis*/
1043 cycles = old_index - last_instruction;
1046 if ((pipestat == STAT_ID) || (pipestat == STAT_BD))
1048 uint32_t new_data_index = ctx->data_index;
1049 uint32_t new_data_half = ctx->data_half;
1051 /* in case of a branch with data, the branch target address was consumed before
1052 * we temporarily go back to the saved data index */
1053 if (pipestat == STAT_BD)
1055 ctx->data_index = old_data_index;
1056 ctx->data_half = old_data_half;
1059 if (ctx->control & ETM_CTRL_TRACE_ADDR)
1065 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
1066 return ERROR_ETM_ANALYSIS_FAILED;
1067 ctx->last_ptr &= ~(0x7f << shift);
1068 ctx->last_ptr |= (packet & 0x7f) << shift;
1070 } while ((packet & 0x80) && (shift < 32));
1077 command_print(cmd_ctx, "address: 0x%8.8" PRIx32 "", ctx->last_ptr);
1081 if (ctx->control & ETM_CTRL_TRACE_DATA)
1083 if ((instruction.type == ARM_LDM) || (instruction.type == ARM_STM))
1086 for (i = 0; i < 16; i++)
1088 if (instruction.info.load_store_multiple.register_list & (1 << i))
1091 if (etmv1_data(ctx, 4, &data) != 0)
1092 return ERROR_ETM_ANALYSIS_FAILED;
1093 command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
1097 else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_STRH))
1100 if (etmv1_data(ctx, arm_access_size(&instruction), &data) != 0)
1101 return ERROR_ETM_ANALYSIS_FAILED;
1102 command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
1106 /* restore data index after consuming BD address and data */
1107 if (pipestat == STAT_BD)
1109 ctx->data_index = new_data_index;
1110 ctx->data_half = new_data_half;
1115 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
1117 if (((instruction.type == ARM_B) ||
1118 (instruction.type == ARM_BL) ||
1119 (instruction.type == ARM_BLX)) &&
1120 (instruction.info.b_bl_bx_blx.target_address != 0xffffffff))
1122 next_pc = instruction.info.b_bl_bx_blx.target_address;
1126 next_pc += (ctx->core_state == ARM_STATE_ARM) ? 4 : 2;
1129 else if (pipestat == STAT_IN)
1131 next_pc += (ctx->core_state == ARM_STATE_ARM) ? 4 : 2;
1134 if ((pipestat != STAT_TD) && (pipestat != STAT_WT))
1136 char cycles_text[32] = "";
1138 /* if the trace was captured with cycle accurate tracing enabled,
1139 * output the number of cycles since the last executed instruction
1141 if (ctx->control & ETM_CTRL_CYCLE_ACCURATE)
1143 snprintf(cycles_text, 32, " (%i %s)",
1145 (cycles == 1) ? "cycle" : "cycles");
1148 command_print(cmd_ctx, "%s%s%s",
1150 (pipestat == STAT_IN) ? " (not executed)" : "",
1153 ctx->current_pc = next_pc;
1155 /* packets for an instruction don't start on or before the preceding
1156 * functional pipestat (i.e. other than WT or TD)
1158 if (ctx->data_index <= ctx->pipe_index)
1160 ctx->data_index = ctx->pipe_index + 1;
1165 ctx->pipe_index += 1;
1171 static COMMAND_HELPER(handle_etm_tracemode_command_update,
1176 /* what parts of data access are traced? */
1177 if (strcmp(CMD_ARGV[0], "none") == 0)
1179 else if (strcmp(CMD_ARGV[0], "data") == 0)
1180 tracemode = ETM_CTRL_TRACE_DATA;
1181 else if (strcmp(CMD_ARGV[0], "address") == 0)
1182 tracemode = ETM_CTRL_TRACE_ADDR;
1183 else if (strcmp(CMD_ARGV[0], "all") == 0)
1184 tracemode = ETM_CTRL_TRACE_DATA | ETM_CTRL_TRACE_ADDR;
1187 command_print(CMD_CTX, "invalid option '%s'", CMD_ARGV[0]);
1188 return ERROR_INVALID_ARGUMENTS;
1192 COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], context_id);
1196 tracemode |= ETM_CTRL_CONTEXTID_NONE;
1199 tracemode |= ETM_CTRL_CONTEXTID_8;
1202 tracemode |= ETM_CTRL_CONTEXTID_16;
1205 tracemode |= ETM_CTRL_CONTEXTID_32;
1208 command_print(CMD_CTX, "invalid option '%s'", CMD_ARGV[1]);
1209 return ERROR_INVALID_ARGUMENTS;
1212 bool etmv1_cycle_accurate;
1213 COMMAND_PARSE_ENABLE(CMD_ARGV[2], etmv1_cycle_accurate);
1214 if (etmv1_cycle_accurate)
1215 tracemode |= ETM_CTRL_CYCLE_ACCURATE;
1217 bool etmv1_branch_output;
1218 COMMAND_PARSE_ENABLE(CMD_ARGV[3], etmv1_branch_output);
1219 if (etmv1_branch_output)
1220 tracemode |= ETM_CTRL_BRANCH_OUTPUT;
1223 * - CPRT tracing (coprocessor register transfers)
1224 * - debug request (causes debug entry on trigger)
1225 * - stall on FIFOFULL (preventing tracedata lossage)
1232 COMMAND_HANDLER(handle_etm_tracemode_command)
1234 struct target *target = get_current_target(CMD_CTX);
1235 struct arm *arm = target_to_arm(target);
1236 struct etm_context *etm;
1239 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1245 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1249 uint32_t tracemode = etm->control;
1256 CALL_COMMAND_HANDLER(handle_etm_tracemode_command_update,
1260 command_print(CMD_CTX, "usage: tracemode "
1261 "('none'|'data'|'address'|'all') "
1263 "('enable'|'disable') "
1264 "('enable'|'disable')"
1270 * todo: fail if parameters were invalid for this hardware,
1271 * or couldn't be written; display actual hardware state...
1274 command_print(CMD_CTX, "current tracemode configuration:");
1276 switch (tracemode & ETM_CTRL_TRACE_MASK)
1279 command_print(CMD_CTX, "data tracing: none");
1281 case ETM_CTRL_TRACE_DATA:
1282 command_print(CMD_CTX, "data tracing: data only");
1284 case ETM_CTRL_TRACE_ADDR:
1285 command_print(CMD_CTX, "data tracing: address only");
1287 case ETM_CTRL_TRACE_DATA | ETM_CTRL_TRACE_ADDR:
1288 command_print(CMD_CTX, "data tracing: address and data");
1292 switch (tracemode & ETM_CTRL_CONTEXTID_MASK)
1294 case ETM_CTRL_CONTEXTID_NONE:
1295 command_print(CMD_CTX, "contextid tracing: none");
1297 case ETM_CTRL_CONTEXTID_8:
1298 command_print(CMD_CTX, "contextid tracing: 8 bit");
1300 case ETM_CTRL_CONTEXTID_16:
1301 command_print(CMD_CTX, "contextid tracing: 16 bit");
1303 case ETM_CTRL_CONTEXTID_32:
1304 command_print(CMD_CTX, "contextid tracing: 32 bit");
1308 if (tracemode & ETM_CTRL_CYCLE_ACCURATE)
1310 command_print(CMD_CTX, "cycle-accurate tracing enabled");
1314 command_print(CMD_CTX, "cycle-accurate tracing disabled");
1317 if (tracemode & ETM_CTRL_BRANCH_OUTPUT)
1319 command_print(CMD_CTX, "full branch address output enabled");
1323 command_print(CMD_CTX, "full branch address output disabled");
1326 #define TRACEMODE_MASK ( \
1327 ETM_CTRL_CONTEXTID_MASK \
1328 | ETM_CTRL_BRANCH_OUTPUT \
1329 | ETM_CTRL_CYCLE_ACCURATE \
1330 | ETM_CTRL_TRACE_MASK \
1333 /* only update ETM_CTRL register if tracemode changed */
1334 if ((etm->control & TRACEMODE_MASK) != tracemode)
1336 struct reg *etm_ctrl_reg;
1338 etm_ctrl_reg = etm_reg_lookup(etm, ETM_CTRL);
1342 etm->control &= ~TRACEMODE_MASK;
1343 etm->control |= tracemode & TRACEMODE_MASK;
1345 buf_set_u32(etm_ctrl_reg->value, 0, 32, etm->control);
1346 etm_store_reg(etm_ctrl_reg);
1348 /* invalidate old trace data */
1349 etm->capture_status = TRACE_IDLE;
1350 if (etm->trace_depth > 0)
1352 free(etm->trace_data);
1353 etm->trace_data = NULL;
1355 etm->trace_depth = 0;
1358 #undef TRACEMODE_MASK
1363 COMMAND_HANDLER(handle_etm_config_command)
1365 struct target *target;
1367 uint32_t portmode = 0x0;
1368 struct etm_context *etm_ctx;
1372 return ERROR_COMMAND_SYNTAX_ERROR;
1374 target = get_target(CMD_ARGV[0]);
1377 LOG_ERROR("target '%s' not defined", CMD_ARGV[0]);
1381 arm = target_to_arm(target);
1383 command_print(CMD_CTX, "target '%s' is '%s'; not an ARM",
1384 target_name(target),
1385 target_type_name(target));
1389 /* FIXME for ETMv3.0 and above -- and we don't yet know what ETM
1390 * version we'll be using!! -- so we can't know how to validate
1391 * params yet. "etm config" should likely be *AFTER* hookup...
1393 * - Many more widths might be supported ... and we can easily
1394 * check whether our setting "took".
1396 * - The "clock" and "mode" bits are interpreted differently.
1397 * See ARM IHI 0014O table 2-17 for the old behavior, and
1398 * table 2-18 for the new. With ETB it's best to specify
1402 COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], port_width);
1405 /* before ETMv3.0 */
1407 portmode |= ETM_PORT_4BIT;
1410 portmode |= ETM_PORT_8BIT;
1413 portmode |= ETM_PORT_16BIT;
1415 /* ETMv3.0 and later*/
1417 portmode |= ETM_PORT_24BIT;
1420 portmode |= ETM_PORT_32BIT;
1423 portmode |= ETM_PORT_48BIT;
1426 portmode |= ETM_PORT_64BIT;
1429 portmode |= ETM_PORT_1BIT;
1432 portmode |= ETM_PORT_2BIT;
1435 command_print(CMD_CTX,
1436 "unsupported ETM port width '%s'", CMD_ARGV[1]);
1440 if (strcmp("normal", CMD_ARGV[2]) == 0)
1442 portmode |= ETM_PORT_NORMAL;
1444 else if (strcmp("multiplexed", CMD_ARGV[2]) == 0)
1446 portmode |= ETM_PORT_MUXED;
1448 else if (strcmp("demultiplexed", CMD_ARGV[2]) == 0)
1450 portmode |= ETM_PORT_DEMUXED;
1454 command_print(CMD_CTX, "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", CMD_ARGV[2]);
1458 if (strcmp("half", CMD_ARGV[3]) == 0)
1460 portmode |= ETM_PORT_HALF_CLOCK;
1462 else if (strcmp("full", CMD_ARGV[3]) == 0)
1464 portmode |= ETM_PORT_FULL_CLOCK;
1468 command_print(CMD_CTX, "unsupported ETM port clocking '%s', must be 'full' or 'half'", CMD_ARGV[3]);
1472 etm_ctx = calloc(1, sizeof(struct etm_context));
1474 LOG_DEBUG("out of memory");
1478 for (i = 0; etm_capture_drivers[i]; i++)
1480 if (strcmp(CMD_ARGV[4], etm_capture_drivers[i]->name) == 0)
1482 int retval = register_commands(CMD_CTX, NULL,
1483 etm_capture_drivers[i]->commands);
1484 if (ERROR_OK != retval)
1490 etm_ctx->capture_driver = etm_capture_drivers[i];
1496 if (!etm_capture_drivers[i])
1498 /* no supported capture driver found, don't register an ETM */
1500 LOG_ERROR("trace capture driver '%s' not found", CMD_ARGV[4]);
1504 etm_ctx->target = target;
1505 etm_ctx->trace_data = NULL;
1506 etm_ctx->control = portmode;
1507 etm_ctx->core_state = ARM_STATE_ARM;
1511 return etm_register_user_commands(CMD_CTX);
1514 COMMAND_HANDLER(handle_etm_info_command)
1516 struct target *target;
1518 struct etm_context *etm;
1519 struct reg *etm_sys_config_reg;
1523 target = get_current_target(CMD_CTX);
1524 arm = target_to_arm(target);
1527 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1534 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1538 command_print(CMD_CTX, "ETM v%d.%d",
1539 etm->bcd_vers >> 4, etm->bcd_vers & 0xf);
1540 command_print(CMD_CTX, "pairs of address comparators: %i",
1541 (int) (etm->config >> 0) & 0x0f);
1542 command_print(CMD_CTX, "data comparators: %i",
1543 (int) (etm->config >> 4) & 0x0f);
1544 command_print(CMD_CTX, "memory map decoders: %i",
1545 (int) (etm->config >> 8) & 0x1f);
1546 command_print(CMD_CTX, "number of counters: %i",
1547 (int) (etm->config >> 13) & 0x07);
1548 command_print(CMD_CTX, "sequencer %spresent",
1549 (int) (etm->config & (1 << 16)) ? "" : "not ");
1550 command_print(CMD_CTX, "number of ext. inputs: %i",
1551 (int) (etm->config >> 17) & 0x07);
1552 command_print(CMD_CTX, "number of ext. outputs: %i",
1553 (int) (etm->config >> 20) & 0x07);
1554 command_print(CMD_CTX, "FIFO full %spresent",
1555 (int) (etm->config & (1 << 23)) ? "" : "not ");
1556 if (etm->bcd_vers < 0x20)
1557 command_print(CMD_CTX, "protocol version: %i",
1558 (int) (etm->config >> 28) & 0x07);
1560 command_print(CMD_CTX,
1561 "coprocessor and memory access %ssupported",
1562 (etm->config & (1 << 26)) ? "" : "not ");
1563 command_print(CMD_CTX, "trace start/stop %spresent",
1564 (etm->config & (1 << 26)) ? "" : "not ");
1565 command_print(CMD_CTX, "number of context comparators: %i",
1566 (int) (etm->config >> 24) & 0x03);
1569 /* SYS_CONFIG isn't present before ETMv1.2 */
1570 etm_sys_config_reg = etm_reg_lookup(etm, ETM_SYS_CONFIG);
1571 if (!etm_sys_config_reg)
1574 etm_get_reg(etm_sys_config_reg);
1575 config = buf_get_u32(etm_sys_config_reg->value, 0, 32);
1577 LOG_DEBUG("ETM SYS CONFIG %08x", (unsigned) config);
1579 max_port_size = config & 0x7;
1580 if (etm->bcd_vers >= 0x30)
1581 max_port_size |= (config >> 6) & 0x08;
1582 switch (max_port_size)
1584 /* before ETMv3.0 */
1594 /* ETMv3.0 and later*/
1614 LOG_ERROR("Illegal max_port_size");
1617 command_print(CMD_CTX, "max. port size: %i", max_port_size);
1619 if (etm->bcd_vers < 0x30) {
1620 command_print(CMD_CTX, "half-rate clocking %ssupported",
1621 (config & (1 << 3)) ? "" : "not ");
1622 command_print(CMD_CTX, "full-rate clocking %ssupported",
1623 (config & (1 << 4)) ? "" : "not ");
1624 command_print(CMD_CTX, "normal trace format %ssupported",
1625 (config & (1 << 5)) ? "" : "not ");
1626 command_print(CMD_CTX, "multiplex trace format %ssupported",
1627 (config & (1 << 6)) ? "" : "not ");
1628 command_print(CMD_CTX, "demultiplex trace format %ssupported",
1629 (config & (1 << 7)) ? "" : "not ");
1631 /* REVISIT show which size and format are selected ... */
1632 command_print(CMD_CTX, "current port size %ssupported",
1633 (config & (1 << 10)) ? "" : "not ");
1634 command_print(CMD_CTX, "current trace format %ssupported",
1635 (config & (1 << 11)) ? "" : "not ");
1637 if (etm->bcd_vers >= 0x21)
1638 command_print(CMD_CTX, "fetch comparisons %ssupported",
1639 (config & (1 << 17)) ? "not " : "");
1640 command_print(CMD_CTX, "FIFO full %ssupported",
1641 (config & (1 << 8)) ? "" : "not ");
1646 COMMAND_HANDLER(handle_etm_status_command)
1648 struct target *target;
1650 struct etm_context *etm;
1651 trace_status_t trace_status;
1653 target = get_current_target(CMD_CTX);
1654 arm = target_to_arm(target);
1657 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1664 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1669 if (etm->bcd_vers >= 0x11) {
1672 reg = etm_reg_lookup(etm, ETM_STATUS);
1675 if (etm_get_reg(reg) == ERROR_OK) {
1676 unsigned s = buf_get_u32(reg->value, 0, reg->size);
1678 command_print(CMD_CTX, "etm: %s%s%s%s",
1679 /* bit(1) == progbit */
1680 (etm->bcd_vers >= 0x12)
1682 ? "disabled" : "enabled")
1684 ((s & (1 << 3)) && etm->bcd_vers >= 0x31)
1685 ? " triggered" : "",
1686 ((s & (1 << 2)) && etm->bcd_vers >= 0x12)
1687 ? " start/stop" : "",
1688 ((s & (1 << 0)) && etm->bcd_vers >= 0x11)
1689 ? " untraced-overflow" : "");
1690 } /* else ignore and try showing trace port status */
1693 /* Trace Port Driver status */
1694 trace_status = etm->capture_driver->status(etm);
1695 if (trace_status == TRACE_IDLE)
1697 command_print(CMD_CTX, "%s: idle", etm->capture_driver->name);
1701 static char *completed = " completed";
1702 static char *running = " is running";
1703 static char *overflowed = ", overflowed";
1704 static char *triggered = ", triggered";
1706 command_print(CMD_CTX, "%s: trace collection%s%s%s",
1707 etm->capture_driver->name,
1708 (trace_status & TRACE_RUNNING) ? running : completed,
1709 (trace_status & TRACE_OVERFLOWED) ? overflowed : "",
1710 (trace_status & TRACE_TRIGGERED) ? triggered : "");
1712 if (etm->trace_depth > 0)
1714 command_print(CMD_CTX, "%i frames of trace data read",
1715 (int)(etm->trace_depth));
1722 COMMAND_HANDLER(handle_etm_image_command)
1724 struct target *target;
1726 struct etm_context *etm_ctx;
1730 command_print(CMD_CTX, "usage: etm image <file> [base address] [type]");
1734 target = get_current_target(CMD_CTX);
1735 arm = target_to_arm(target);
1738 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1745 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1751 image_close(etm_ctx->image);
1752 free(etm_ctx->image);
1753 command_print(CMD_CTX, "previously loaded image found and closed");
1756 etm_ctx->image = malloc(sizeof(struct image));
1757 etm_ctx->image->base_address_set = 0;
1758 etm_ctx->image->start_address_set = 0;
1760 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1763 etm_ctx->image->base_address_set = 1;
1764 COMMAND_PARSE_NUMBER(llong, CMD_ARGV[1], etm_ctx->image->base_address);
1768 etm_ctx->image->base_address_set = 0;
1771 if (image_open(etm_ctx->image, CMD_ARGV[0], (CMD_ARGC >= 3) ? CMD_ARGV[2] : NULL) != ERROR_OK)
1773 free(etm_ctx->image);
1774 etm_ctx->image = NULL;
1781 COMMAND_HANDLER(handle_etm_dump_command)
1784 struct target *target;
1786 struct etm_context *etm_ctx;
1791 command_print(CMD_CTX, "usage: etm dump <file>");
1795 target = get_current_target(CMD_CTX);
1796 arm = target_to_arm(target);
1799 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1806 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1810 if (etm_ctx->capture_driver->status == TRACE_IDLE)
1812 command_print(CMD_CTX, "trace capture wasn't enabled, no trace data captured");
1816 if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1818 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1819 command_print(CMD_CTX, "trace capture not completed");
1823 /* read the trace data if it wasn't read already */
1824 if (etm_ctx->trace_depth == 0)
1825 etm_ctx->capture_driver->read_trace(etm_ctx);
1827 if (fileio_open(&file, CMD_ARGV[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1832 fileio_write_u32(&file, etm_ctx->capture_status);
1833 fileio_write_u32(&file, etm_ctx->control);
1834 fileio_write_u32(&file, etm_ctx->trace_depth);
1836 for (i = 0; i < etm_ctx->trace_depth; i++)
1838 fileio_write_u32(&file, etm_ctx->trace_data[i].pipestat);
1839 fileio_write_u32(&file, etm_ctx->trace_data[i].packet);
1840 fileio_write_u32(&file, etm_ctx->trace_data[i].flags);
1843 fileio_close(&file);
1848 COMMAND_HANDLER(handle_etm_load_command)
1851 struct target *target;
1853 struct etm_context *etm_ctx;
1858 command_print(CMD_CTX, "usage: etm load <file>");
1862 target = get_current_target(CMD_CTX);
1863 arm = target_to_arm(target);
1866 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1873 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1877 if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1879 command_print(CMD_CTX, "trace capture running, stop first");
1883 if (fileio_open(&file, CMD_ARGV[0], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1890 command_print(CMD_CTX, "size isn't a multiple of 4, no valid trace data");
1891 fileio_close(&file);
1895 if (etm_ctx->trace_depth > 0)
1897 free(etm_ctx->trace_data);
1898 etm_ctx->trace_data = NULL;
1903 fileio_read_u32(&file, &tmp); etm_ctx->capture_status = tmp;
1904 fileio_read_u32(&file, &tmp); etm_ctx->control = tmp;
1905 fileio_read_u32(&file, &etm_ctx->trace_depth);
1907 etm_ctx->trace_data = malloc(sizeof(struct etmv1_trace_data) * etm_ctx->trace_depth);
1908 if (etm_ctx->trace_data == NULL)
1910 command_print(CMD_CTX, "not enough memory to perform operation");
1911 fileio_close(&file);
1915 for (i = 0; i < etm_ctx->trace_depth; i++)
1917 uint32_t pipestat, packet, flags;
1918 fileio_read_u32(&file, &pipestat);
1919 fileio_read_u32(&file, &packet);
1920 fileio_read_u32(&file, &flags);
1921 etm_ctx->trace_data[i].pipestat = pipestat & 0xff;
1922 etm_ctx->trace_data[i].packet = packet & 0xffff;
1923 etm_ctx->trace_data[i].flags = flags;
1926 fileio_close(&file);
1931 COMMAND_HANDLER(handle_etm_start_command)
1933 struct target *target;
1935 struct etm_context *etm_ctx;
1936 struct reg *etm_ctrl_reg;
1938 target = get_current_target(CMD_CTX);
1939 arm = target_to_arm(target);
1942 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1949 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1953 /* invalidate old tracing data */
1954 etm_ctx->capture_status = TRACE_IDLE;
1955 if (etm_ctx->trace_depth > 0)
1957 free(etm_ctx->trace_data);
1958 etm_ctx->trace_data = NULL;
1960 etm_ctx->trace_depth = 0;
1962 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
1966 etm_get_reg(etm_ctrl_reg);
1968 /* Clear programming bit (10), set port selection bit (11) */
1969 buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x2);
1971 etm_store_reg(etm_ctrl_reg);
1972 jtag_execute_queue();
1974 etm_ctx->capture_driver->start_capture(etm_ctx);
1979 COMMAND_HANDLER(handle_etm_stop_command)
1981 struct target *target;
1983 struct etm_context *etm_ctx;
1984 struct reg *etm_ctrl_reg;
1986 target = get_current_target(CMD_CTX);
1987 arm = target_to_arm(target);
1990 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1997 command_print(CMD_CTX, "current target doesn't have an ETM configured");
2001 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
2005 etm_get_reg(etm_ctrl_reg);
2007 /* Set programming bit (10), clear port selection bit (11) */
2008 buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x1);
2010 etm_store_reg(etm_ctrl_reg);
2011 jtag_execute_queue();
2013 etm_ctx->capture_driver->stop_capture(etm_ctx);
2018 COMMAND_HANDLER(handle_etm_trigger_debug_command)
2020 struct target *target;
2022 struct etm_context *etm;
2024 target = get_current_target(CMD_CTX);
2025 arm = target_to_arm(target);
2028 command_print(CMD_CTX, "ETM: %s isn't an ARM",
2029 target_name(target));
2036 command_print(CMD_CTX, "ETM: no ETM configured for %s",
2037 target_name(target));
2041 if (CMD_ARGC == 1) {
2042 struct reg *etm_ctrl_reg;
2045 etm_ctrl_reg = etm_reg_lookup(etm, ETM_CTRL);
2049 COMMAND_PARSE_ENABLE(CMD_ARGV[0], dbgrq);
2051 etm->control |= ETM_CTRL_DBGRQ;
2053 etm->control &= ~ETM_CTRL_DBGRQ;
2055 /* etm->control will be written to hardware
2056 * the next time an "etm start" is issued.
2058 buf_set_u32(etm_ctrl_reg->value, 0, 32, etm->control);
2061 command_print(CMD_CTX, "ETM: %s debug halt",
2062 (etm->control & ETM_CTRL_DBGRQ)
2064 : "does not trigger");
2068 COMMAND_HANDLER(handle_etm_analyze_command)
2070 struct target *target;
2072 struct etm_context *etm_ctx;
2075 target = get_current_target(CMD_CTX);
2076 arm = target_to_arm(target);
2079 command_print(CMD_CTX, "ETM: current target isn't an ARM");
2086 command_print(CMD_CTX, "current target doesn't have an ETM configured");
2090 if ((retval = etmv1_analyze_trace(etm_ctx, CMD_CTX)) != ERROR_OK)
2094 case ERROR_ETM_ANALYSIS_FAILED:
2095 command_print(CMD_CTX, "further analysis failed (corrupted trace data or just end of data");
2097 case ERROR_TRACE_INSTRUCTION_UNAVAILABLE:
2098 command_print(CMD_CTX, "no instruction for current address available, analysis aborted");
2100 case ERROR_TRACE_IMAGE_UNAVAILABLE:
2101 command_print(CMD_CTX, "no image available for trace analysis");
2104 command_print(CMD_CTX, "unknown error: %i", retval);
2111 static const struct command_registration etm_config_command_handlers[] = {
2113 /* NOTE: with ADIv5, ETMs are accessed by DAP operations,
2114 * possibly over SWD, not JTAG scanchain 6 of 'target'.
2116 * Also, these parameters don't match ETM v3+ modules...
2119 .handler = handle_etm_config_command,
2120 .mode = COMMAND_CONFIG,
2121 .help = "Set up ETM output port.",
2122 .usage = "target port_width port_mode clocking capture_driver",
2124 COMMAND_REGISTRATION_DONE
2126 const struct command_registration etm_command_handlers[] = {
2129 .mode = COMMAND_ANY,
2130 .help = "Emebdded Trace Macrocell command group",
2131 .chain = etm_config_command_handlers,
2133 COMMAND_REGISTRATION_DONE
2136 static const struct command_registration etm_exec_command_handlers[] = {
2138 .name = "tracemode",
2139 .handler = handle_etm_tracemode_command,
2140 .mode = COMMAND_EXEC,
2141 .help = "configure/display trace mode",
2142 .usage = "('none'|'data'|'address'|'all') "
2144 "['enable'|'disable'] "
2145 "['enable'|'disable']",
2149 .handler = handle_etm_info_command,
2150 .mode = COMMAND_EXEC,
2151 .help = "display info about the current target's ETM",
2155 .handler = handle_etm_status_command,
2156 .mode = COMMAND_EXEC,
2157 .help = "display current target's ETM status",
2161 .handler = handle_etm_start_command,
2162 .mode = COMMAND_EXEC,
2163 .help = "start ETM trace collection",
2167 .handler = handle_etm_stop_command,
2168 .mode = COMMAND_EXEC,
2169 .help = "stop ETM trace collection",
2172 .name = "trigger_debug",
2173 .handler = handle_etm_trigger_debug_command,
2174 .mode = COMMAND_EXEC,
2175 .help = "enable/disable debug entry on trigger",
2176 .usage = "['enable'|'disable']",
2180 .handler = handle_etm_analyze_command,
2181 .mode = COMMAND_EXEC,
2182 .help = "analyze collected ETM trace",
2186 .handler = handle_etm_image_command,
2187 .mode = COMMAND_EXEC,
2188 .help = "load image from file with optional offset",
2189 .usage = "filename [offset]",
2193 .handler = handle_etm_dump_command,
2194 .mode = COMMAND_EXEC,
2195 .help = "dump captured trace data to file",
2196 .usage = "filename",
2200 .handler = handle_etm_load_command,
2201 .mode = COMMAND_EXEC,
2202 .help = "load trace data for analysis <file>",
2204 COMMAND_REGISTRATION_DONE
2207 static int etm_register_user_commands(struct command_context *cmd_ctx)
2209 struct command *etm_cmd = command_find_in_context(cmd_ctx, "etm");
2210 return register_commands(cmd_ctx, etm_cmd, etm_exec_command_handlers);