git.sur5r.net Git - openocd/blob - src/target/etm.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "etm.h"
  25 #include "etb.h"
  26 #include "image.h"
  27 #include "arm7_9_common.h"
  28 #include "arm_disassembler.h"
  29
  30
  31 /*
  32  * ARM "Embedded Trace Macrocell" (ETM) support -- direct JTAG access.
  33  *
  34  * ETM modules collect instruction and/or data trace information, compress
  35  * it, and transfer it to a debugging host through either a (buffered) trace
  36  * port (often a 38-pin Mictor connector) or an Embedded Trace Buffer (ETB).
  37  *
  38  * There are several generations of these modules.  Original versions have
  39  * JTAG access through a dedicated scan chain.  Recent versions have added
  40  * access via coprocessor instructions, memory addressing, and the ARM Debug
  41  * Interface v5 (ADIv5); and phased out direct JTAG access.
  42  *
  43  * This code supports up to the ETMv1.3 architecture, as seen in ETM9 and
  44  * most common ARM9 systems.  Note: "CoreSight ETM9" implements ETMv3.2,
  45  * implying non-JTAG connectivity options.
  46  *
  47  * Relevant documentation includes:
  48  *  ARM DDI 0157G ... ETM9 (r2p2) Technical Reference Manual
  49  *  ARM DDI 0315B ... CoreSight ETM9 (r0p1) Technical Reference Manual
  50  *  ARM IHI 0014O ... Embedded Trace Macrocell, Architecture Specification
  51  */
  52
  53 #define ARRAY_SIZE(x)   ((int)(sizeof(x)/sizeof((x)[0])))
  54
  55 enum {
  56         RO,                             /* read/only */
  57         WO,                             /* write/only */
  58         RW,                             /* read/write */
  59 };
  60
  61 struct etm_reg_info {
  62         uint8_t         addr;
  63         uint8_t         size;           /* low-N of 32 bits */
  64         uint8_t         mode;           /* RO, WO, RW */
  65         uint8_t         bcd_vers;       /* 1.0, 2.0, etc */
  66         char            *name;
  67 };
  68
  69 /*
  70  * Registers 0..0x7f are JTAG-addressable using scanchain 6.
  71  * (Or on some processors, through coprocessor operations.)
  72  * Newer versions of ETM make some W/O registers R/W, and
  73  * provide definitions for some previously-unused bits.
  74  */
  75
  76 /* basic registers that are always there given the right ETM version */
  77 static const struct etm_reg_info etm_core[] = {
  78         /* NOTE: we "know" ETM_CONFIG is listed first */
  79         { ETM_CONFIG, 32, RO, 0x10, "ETM_config", },
  80
  81         /* ETM Trace Registers */
  82         { ETM_CTRL, 32, RW, 0x10, "ETM_ctrl", },
  83         { ETM_TRIG_EVENT, 17, WO, 0x10, "ETM_trig_event", },
  84         { ETM_ASIC_CTRL,  8, WO, 0x10, "ETM_asic_ctrl", },
  85         { ETM_STATUS,  3, RO, 0x11, "ETM_status", },
  86         { ETM_SYS_CONFIG,  9, RO, 0x12, "ETM_sys_config", },
  87
  88         /* TraceEnable configuration */
  89         { ETM_TRACE_RESOURCE_CTRL, 32, WO, 0x12, "ETM_trace_resource_ctrl", },
  90         { ETM_TRACE_EN_CTRL2, 16, WO, 0x12, "ETM_trace_en_ctrl2", },
  91         { ETM_TRACE_EN_EVENT, 17, WO, 0x10, "ETM_trace_en_event", },
  92         { ETM_TRACE_EN_CTRL1, 26, WO, 0x10, "ETM_trace_en_ctrl1", },
  93
  94         /* ViewData configuration (data trace) */
  95         { ETM_VIEWDATA_EVENT, 17, WO, 0x10, "ETM_viewdata_event", },
  96         { ETM_VIEWDATA_CTRL1, 32, WO, 0x10, "ETM_viewdata_ctrl1", },
  97         { ETM_VIEWDATA_CTRL2, 32, WO, 0x10, "ETM_viewdata_ctrl2", },
  98         { ETM_VIEWDATA_CTRL3, 17, WO, 0x10, "ETM_viewdata_ctrl3", },
  99
 100         /* REVISIT exclude VIEWDATA_CTRL2 when it's not there */
 101
 102         { 0x78, 12, WO, 0x20, "ETM_sync_freq", },
 103         { 0x79, 32, RO, 0x20, "ETM_id", },
 104 };
 105
 106 static const struct etm_reg_info etm_fifofull[] = {
 107         /* FIFOFULL configuration */
 108         { ETM_FIFOFULL_REGION, 25, WO, 0x10, "ETM_fifofull_region", },
 109         { ETM_FIFOFULL_LEVEL,  8, WO, 0x10, "ETM_fifofull_level", },
 110 };
 111
 112 static const struct etm_reg_info etm_addr_comp[] = {
 113         /* Address comparator register pairs */
 114 #define ADDR_COMPARATOR(i) \
 115                 { ETM_ADDR_COMPARATOR_VALUE + (i) - 1, 32, WO, 0x10, \
 116                                 "ETM_addr_" #i "_comparator_value", }, \
 117                 { ETM_ADDR_ACCESS_TYPE + (i) - 1,  7, WO, 0x10, \
 118                                 "ETM_addr_" #i "_access_type", }
 119         ADDR_COMPARATOR(1),
 120         ADDR_COMPARATOR(2),
 121         ADDR_COMPARATOR(3),
 122         ADDR_COMPARATOR(4),
 123         ADDR_COMPARATOR(5),
 124         ADDR_COMPARATOR(6),
 125         ADDR_COMPARATOR(7),
 126         ADDR_COMPARATOR(8),
 127
 128         ADDR_COMPARATOR(9),
 129         ADDR_COMPARATOR(10),
 130         ADDR_COMPARATOR(11),
 131         ADDR_COMPARATOR(12),
 132         ADDR_COMPARATOR(13),
 133         ADDR_COMPARATOR(14),
 134         ADDR_COMPARATOR(15),
 135         ADDR_COMPARATOR(16),
 136 #undef ADDR_COMPARATOR
 137 };
 138
 139 static const struct etm_reg_info etm_data_comp[] = {
 140         /* Data Value Comparators (NOTE: odd addresses are reserved) */
 141 #define DATA_COMPARATOR(i) \
 142                 { ETM_DATA_COMPARATOR_VALUE + 2*(i) - 1, 32, WO, 0x10, \
 143                                 "ETM_data_" #i "_comparator_value", }, \
 144                 { ETM_DATA_COMPARATOR_MASK + 2*(i) - 1, 32, WO, 0x10, \
 145                                 "ETM_data_" #i "_comparator_mask", }
 146         DATA_COMPARATOR(1),
 147         DATA_COMPARATOR(2),
 148         DATA_COMPARATOR(3),
 149         DATA_COMPARATOR(4),
 150         DATA_COMPARATOR(5),
 151         DATA_COMPARATOR(6),
 152         DATA_COMPARATOR(7),
 153         DATA_COMPARATOR(8),
 154 #undef DATA_COMPARATOR
 155 };
 156
 157 static const struct etm_reg_info etm_counters[] = {
 158 #define ETM_COUNTER(i) \
 159                 { ETM_COUNTER_RELOAD_VALUE + (i) - 1, 16, WO, 0x10, \
 160                                 "ETM_counter_" #i "_reload_value", }, \
 161                 { ETM_COUNTER_ENABLE + (i) - 1, 18, WO, 0x10, \
 162                                 "ETM_counter_" #i "_enable", }, \
 163                 { ETM_COUNTER_RELOAD_EVENT + (i) - 1, 17, WO, 0x10, \
 164                                 "ETM_counter_" #i "_reload_event", }, \
 165                 { ETM_COUNTER_VALUE + (i) - 1, 16, RO, 0x10, \
 166                                 "ETM_counter_" #i "_value", }
 167         ETM_COUNTER(1),
 168         ETM_COUNTER(2),
 169         ETM_COUNTER(3),
 170         ETM_COUNTER(4),
 171 #undef ETM_COUNTER
 172 };
 173
 174 static const struct etm_reg_info etm_sequencer[] = {
 175 #define ETM_SEQ(i) \
 176                 { ETM_SEQUENCER_EVENT + (i), 17, WO, 0x10, \
 177                                 "ETM_sequencer_event" #i, }
 178         ETM_SEQ(0),                             /* 1->2 */
 179         ETM_SEQ(1),                             /* 2->1 */
 180         ETM_SEQ(2),                             /* 2->3 */
 181         ETM_SEQ(3),                             /* 3->1 */
 182         ETM_SEQ(4),                             /* 3->2 */
 183         ETM_SEQ(5),                             /* 1->3 */
 184 #undef ETM_SEQ
 185         /* 0x66 reserved */
 186         { ETM_SEQUENCER_STATE,  2, RO, 0x10, "ETM_sequencer_state", },
 187 };
 188
 189 static const struct etm_reg_info etm_outputs[] = {
 190 #define ETM_OUTPUT(i) \
 191                 { ETM_EXTERNAL_OUTPUT + (i) - 1, 17, WO, 0x10, \
 192                                 "ETM_external_output" #i, }
 193
 194         ETM_OUTPUT(1),
 195         ETM_OUTPUT(2),
 196         ETM_OUTPUT(3),
 197         ETM_OUTPUT(4),
 198 #undef ETM_OUTPUT
 199 };
 200
 201 #if 0
 202         /* registers from 0x6c..0x7f were added after ETMv1.3 */
 203
 204         /* Context ID Comparators */
 205         { 0x6c, 32, RO, 0x20, "ETM_contextid_comparator_value1", }
 206         { 0x6d, 32, RO, 0x20, "ETM_contextid_comparator_value2", }
 207         { 0x6e, 32, RO, 0x20, "ETM_contextid_comparator_value3", }
 208         { 0x6f, 32, RO, 0x20, "ETM_contextid_comparator_mask", }
 209 #endif
 210
 211 static int etm_reg_arch_type = -1;
 212
 213 static int etm_get_reg(reg_t *reg);
 214 static int etm_read_reg_w_check(reg_t *reg,
 215                 uint8_t* check_value, uint8_t* check_mask);
 216 static int etm_register_user_commands(struct command_context_s *cmd_ctx);
 217 static int etm_set_reg_w_exec(reg_t *reg, uint8_t *buf);
 218 static int etm_write_reg(reg_t *reg, uint32_t value);
 219
 220 static command_t *etm_cmd;
 221
 222
 223 /* Look up register by ID ... most ETM instances only
 224  * support a subset of the possible registers.
 225  */
 226 static reg_t *etm_reg_lookup(etm_context_t *etm_ctx, unsigned id)
 227 {
 228         reg_cache_t *cache = etm_ctx->reg_cache;
 229         int i;
 230
 231         for (i = 0; i < cache->num_regs; i++) {
 232                 struct etm_reg_s *reg = cache->reg_list[i].arch_info;
 233
 234                 if (reg->reg_info->addr == id)
 235                         return &cache->reg_list[i];
 236         }
 237
 238         /* caller asking for nonexistent register is a bug! */
 239         /* REVISIT say which of the N targets was involved */
 240         LOG_ERROR("ETM: register 0x%02x not available", id);
 241         return NULL;
 242 }
 243
 244 static void etm_reg_add(unsigned bcd_vers, arm_jtag_t *jtag_info,
 245                 reg_cache_t *cache, etm_reg_t *ereg,
 246                 const struct etm_reg_info *r, unsigned nreg)
 247 {
 248         reg_t *reg = cache->reg_list;
 249
 250         reg += cache->num_regs;
 251         ereg += cache->num_regs;
 252
 253         /* add up to "nreg" registers from "r", if supported by this
 254          * version of the ETM, to the specified cache.
 255          */
 256         for (; nreg--; r++) {
 257
 258                 /* this ETM may be too old to have some registers */
 259                 if (r->bcd_vers > bcd_vers)
 260                         continue;
 261
 262                 reg->name = r->name;
 263                 reg->size = r->size;
 264                 reg->value = &ereg->value;
 265                 reg->arch_info = ereg;
 266                 reg->arch_type = etm_reg_arch_type;
 267                 reg++;
 268                 cache->num_regs++;
 269
 270                 ereg->reg_info = r;
 271                 ereg->jtag_info = jtag_info;
 272                 ereg++;
 273         }
 274 }
 275
 276 reg_cache_t *etm_build_reg_cache(target_t *target,
 277                 arm_jtag_t *jtag_info, etm_context_t *etm_ctx)
 278 {
 279         reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
 280         reg_t *reg_list = NULL;
 281         etm_reg_t *arch_info = NULL;
 282         unsigned bcd_vers, config;
 283
 284         /* register a register arch-type for etm registers only once */
 285         if (etm_reg_arch_type == -1)
 286                 etm_reg_arch_type = register_reg_arch_type(etm_get_reg,
 287                                 etm_set_reg_w_exec);
 288
 289         /* the actual registers are kept in two arrays */
 290         reg_list = calloc(128, sizeof(reg_t));
 291         arch_info = calloc(128, sizeof(etm_reg_t));
 292
 293         /* fill in values for the reg cache */
 294         reg_cache->name = "etm registers";
 295         reg_cache->next = NULL;
 296         reg_cache->reg_list = reg_list;
 297         reg_cache->num_regs = 0;
 298
 299         /* add ETM_CONFIG, then parse its values to see
 300          * which other registers exist in this ETM
 301          */
 302         etm_reg_add(0x10, jtag_info, reg_cache, arch_info,
 303                         etm_core, 1);
 304
 305         etm_get_reg(reg_list);
 306         etm_ctx->config = buf_get_u32((void *)&arch_info->value, 0, 32);
 307         config = etm_ctx->config;
 308
 309         /* figure ETM version then add base registers */
 310         if (config & (1 << 31)) {
 311                 bcd_vers = 0x20;
 312                 LOG_WARNING("ETMv2+ support is incomplete");
 313
 314                 /* REVISIT read ID register, distinguish ETMv3.3 etc;
 315                  * don't presume trace start/stop support is present;
 316                  * and include any context ID comparator registers.
 317                  */
 318         } else {
 319                 switch (config >> 28) {
 320                 case 7:
 321                 case 5:
 322                 case 3:
 323                         bcd_vers = 0x13;
 324                         break;
 325                 case 4:
 326                 case 2:
 327                         bcd_vers = 0x12;
 328                         break;
 329                 case 1:
 330                         bcd_vers = 0x11;
 331                         break;
 332                 case 0:
 333                         bcd_vers = 0x10;
 334                         break;
 335                 default:
 336                         LOG_WARNING("Bad ETMv1 protocol %d", config >> 28);
 337                         free(reg_cache);
 338                         free(reg_list);
 339                         free(arch_info);
 340                         return ERROR_OK;
 341                 }
 342         }
 343         etm_ctx->bcd_vers = bcd_vers;
 344         LOG_INFO("ETM v%d.%d", bcd_vers >> 4, bcd_vers & 0xf);
 345
 346         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 347                         etm_core + 1, ARRAY_SIZE(etm_core) - 1);
 348
 349         /* address and data comparators; counters; outputs */
 350         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 351                         etm_addr_comp, 4 * (0x0f & (config >> 0)));
 352         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 353                         etm_data_comp, 2 * (0x0f & (config >> 4)));
 354         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 355                         etm_counters, 4 * (0x07 & (config >> 13)));
 356         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 357                         etm_outputs, (0x07 & (config >> 20)));
 358
 359         /* FIFOFULL presence is optional
 360          * REVISIT for ETMv1.2 and later, don't bother adding this
 361          * unless ETM_SYS_CONFIG says it's also *supported* ...
 362          */
 363         if (config & (1 << 23))
 364                 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 365                                 etm_fifofull, ARRAY_SIZE(etm_fifofull));
 366
 367         /* sequencer is optional (for state-dependant triggering) */
 368         if (config & (1 << 16))
 369                 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 370                                 etm_sequencer, ARRAY_SIZE(etm_sequencer));
 371
 372         /* REVISIT could realloc and likely save half the memory
 373          * in the two chunks we allocated...
 374          */
 375
 376         /* the ETM might have an ETB connected */
 377         if (strcmp(etm_ctx->capture_driver->name, "etb") == 0)
 378         {
 379                 etb_t *etb = etm_ctx->capture_driver_priv;
 380
 381                 if (!etb)
 382                 {
 383                         LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
 384                         free(reg_cache);
 385                         free(reg_list);
 386                         free(arch_info);
 387                         return ERROR_OK;
 388                 }
 389
 390                 reg_cache->next = etb_build_reg_cache(etb);
 391
 392                 etb->reg_cache = reg_cache->next;
 393         }
 394
 395
 396         return reg_cache;
 397 }
 398
 399 static int etm_read_reg(reg_t *reg)
 400 {
 401         return etm_read_reg_w_check(reg, NULL, NULL);
 402 }
 403
 404 static int etm_store_reg(reg_t *reg)
 405 {
 406         return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
 407 }
 408
 409 int etm_setup(target_t *target)
 410 {
 411         int retval;
 412         uint32_t etm_ctrl_value;
 413         armv4_5_common_t *armv4_5 = target->arch_info;
 414         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 415         etm_context_t *etm_ctx = arm7_9->etm_ctx;
 416         reg_t *etm_ctrl_reg;
 417
 418         etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
 419         if (!etm_ctrl_reg)
 420                 return ERROR_OK;
 421
 422         /* initialize some ETM control register settings */
 423         etm_get_reg(etm_ctrl_reg);
 424         etm_ctrl_value = buf_get_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size);
 425
 426         /* clear the ETM powerdown bit (0) */
 427         etm_ctrl_value &= ~0x1;
 428
 429         /* configure port width (6:4), mode (17:16) and clocking (13) */
 430         etm_ctrl_value = (etm_ctrl_value &
 431                 ~ETM_PORT_WIDTH_MASK & ~ETM_PORT_MODE_MASK & ~ETM_PORT_CLOCK_MASK)
 432                 | etm_ctx->portmode;
 433
 434         buf_set_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size, etm_ctrl_value);
 435         etm_store_reg(etm_ctrl_reg);
 436
 437         if ((retval = jtag_execute_queue()) != ERROR_OK)
 438                 return retval;
 439
 440         if ((retval = etm_ctx->capture_driver->init(etm_ctx)) != ERROR_OK)
 441         {
 442                 LOG_ERROR("ETM capture driver initialization failed");
 443                 return retval;
 444         }
 445         return ERROR_OK;
 446 }
 447
 448 static int etm_get_reg(reg_t *reg)
 449 {
 450         int retval;
 451
 452         if ((retval = etm_read_reg(reg)) != ERROR_OK)
 453         {
 454                 LOG_ERROR("BUG: error scheduling etm register read");
 455                 return retval;
 456         }
 457
 458         if ((retval = jtag_execute_queue()) != ERROR_OK)
 459         {
 460                 LOG_ERROR("register read failed");
 461                 return retval;
 462         }
 463
 464         return ERROR_OK;
 465 }
 466
 467 static int etm_read_reg_w_check(reg_t *reg,
 468                 uint8_t* check_value, uint8_t* check_mask)
 469 {
 470         etm_reg_t *etm_reg = reg->arch_info;
 471         const struct etm_reg_info *r = etm_reg->reg_info;
 472         uint8_t reg_addr = r->addr & 0x7f;
 473         scan_field_t fields[3];
 474
 475         if (etm_reg->reg_info->mode == WO) {
 476                 LOG_ERROR("BUG: can't read write-only register %s", r->name);
 477                 return ERROR_INVALID_ARGUMENTS;
 478         }
 479
 480         LOG_DEBUG("%s (%u)", r->name, reg_addr);
 481
 482         jtag_set_end_state(TAP_IDLE);
 483         arm_jtag_scann(etm_reg->jtag_info, 0x6);
 484         arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
 485
 486         fields[0].tap = etm_reg->jtag_info->tap;
 487         fields[0].num_bits = 32;
 488         fields[0].out_value = reg->value;
 489         fields[0].in_value = NULL;
 490         fields[0].check_value = NULL;
 491         fields[0].check_mask = NULL;
 492
 493         fields[1].tap = etm_reg->jtag_info->tap;
 494         fields[1].num_bits = 7;
 495         fields[1].out_value = malloc(1);
 496         buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
 497         fields[1].in_value = NULL;
 498         fields[1].check_value = NULL;
 499         fields[1].check_mask = NULL;
 500
 501         fields[2].tap = etm_reg->jtag_info->tap;
 502         fields[2].num_bits = 1;
 503         fields[2].out_value = malloc(1);
 504         buf_set_u32(fields[2].out_value, 0, 1, 0);
 505         fields[2].in_value = NULL;
 506         fields[2].check_value = NULL;
 507         fields[2].check_mask = NULL;
 508
 509         jtag_add_dr_scan(3, fields, jtag_get_end_state());
 510
 511         fields[0].in_value = reg->value;
 512         fields[0].check_value = check_value;
 513         fields[0].check_mask = check_mask;
 514
 515         jtag_add_dr_scan_check(3, fields, jtag_get_end_state());
 516
 517         free(fields[1].out_value);
 518         free(fields[2].out_value);
 519
 520         return ERROR_OK;
 521 }
 522
 523 static int etm_set_reg(reg_t *reg, uint32_t value)
 524 {
 525         int retval;
 526
 527         if ((retval = etm_write_reg(reg, value)) != ERROR_OK)
 528         {
 529                 LOG_ERROR("BUG: error scheduling etm register write");
 530                 return retval;
 531         }
 532
 533         buf_set_u32(reg->value, 0, reg->size, value);
 534         reg->valid = 1;
 535         reg->dirty = 0;
 536
 537         return ERROR_OK;
 538 }
 539
 540 static int etm_set_reg_w_exec(reg_t *reg, uint8_t *buf)
 541 {
 542         int retval;
 543
 544         etm_set_reg(reg, buf_get_u32(buf, 0, reg->size));
 545
 546         if ((retval = jtag_execute_queue()) != ERROR_OK)
 547         {
 548                 LOG_ERROR("register write failed");
 549                 return retval;
 550         }
 551         return ERROR_OK;
 552 }
 553
 554 static int etm_write_reg(reg_t *reg, uint32_t value)
 555 {
 556         etm_reg_t *etm_reg = reg->arch_info;
 557         const struct etm_reg_info *r = etm_reg->reg_info;
 558         uint8_t reg_addr = r->addr & 0x7f;
 559         scan_field_t fields[3];
 560
 561         if (etm_reg->reg_info->mode == RO) {
 562                 LOG_ERROR("BUG: can't write read--only register %s", r->name);
 563                 return ERROR_INVALID_ARGUMENTS;
 564         }
 565
 566         LOG_DEBUG("%s (%u): 0x%8.8" PRIx32 "", r->name, reg_addr, value);
 567
 568         jtag_set_end_state(TAP_IDLE);
 569         arm_jtag_scann(etm_reg->jtag_info, 0x6);
 570         arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
 571
 572         fields[0].tap = etm_reg->jtag_info->tap;
 573         fields[0].num_bits = 32;
 574         uint8_t tmp1[4];
 575         fields[0].out_value = tmp1;
 576         buf_set_u32(fields[0].out_value, 0, 32, value);
 577         fields[0].in_value = NULL;
 578
 579         fields[1].tap = etm_reg->jtag_info->tap;
 580         fields[1].num_bits = 7;
 581         uint8_t tmp2;
 582         fields[1].out_value = &tmp2;
 583         buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
 584         fields[1].in_value = NULL;
 585
 586         fields[2].tap = etm_reg->jtag_info->tap;
 587         fields[2].num_bits = 1;
 588         uint8_t tmp3;
 589         fields[2].out_value = &tmp3;
 590         buf_set_u32(fields[2].out_value, 0, 1, 1);
 591         fields[2].in_value = NULL;
 592
 593         jtag_add_dr_scan(3, fields, jtag_get_end_state());
 594
 595         return ERROR_OK;
 596 }
 597
 598
 599 /* ETM trace analysis functionality
 600  *
 601  */
 602 extern etm_capture_driver_t etm_dummy_capture_driver;
 603 #if BUILD_OOCD_TRACE == 1
 604 extern etm_capture_driver_t oocd_trace_capture_driver;
 605 #endif
 606
 607 static etm_capture_driver_t *etm_capture_drivers[] =
 608 {
 609         &etb_capture_driver,
 610         &etm_dummy_capture_driver,
 611 #if BUILD_OOCD_TRACE == 1
 612         &oocd_trace_capture_driver,
 613 #endif
 614         NULL
 615 };
 616
 617 static int etm_read_instruction(etm_context_t *ctx, arm_instruction_t *instruction)
 618 {
 619         int i;
 620         int section = -1;
 621         uint32_t size_read;
 622         uint32_t opcode;
 623         int retval;
 624
 625         if (!ctx->image)
 626                 return ERROR_TRACE_IMAGE_UNAVAILABLE;
 627
 628         /* search for the section the current instruction belongs to */
 629         for (i = 0; i < ctx->image->num_sections; i++)
 630         {
 631                 if ((ctx->image->sections[i].base_address <= ctx->current_pc) &&
 632                         (ctx->image->sections[i].base_address + ctx->image->sections[i].size > ctx->current_pc))
 633                 {
 634                         section = i;
 635                         break;
 636                 }
 637         }
 638
 639         if (section == -1)
 640         {
 641                 /* current instruction couldn't be found in the image */
 642                 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
 643         }
 644
 645         if (ctx->core_state == ARMV4_5_STATE_ARM)
 646         {
 647                 uint8_t buf[4];
 648                 if ((retval = image_read_section(ctx->image, section,
 649                         ctx->current_pc - ctx->image->sections[section].base_address,
 650                         4, buf, &size_read)) != ERROR_OK)
 651                 {
 652                         LOG_ERROR("error while reading instruction: %i", retval);
 653                         return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
 654                 }
 655                 opcode = target_buffer_get_u32(ctx->target, buf);
 656                 arm_evaluate_opcode(opcode, ctx->current_pc, instruction);
 657         }
 658         else if (ctx->core_state == ARMV4_5_STATE_THUMB)
 659         {
 660                 uint8_t buf[2];
 661                 if ((retval = image_read_section(ctx->image, section,
 662                         ctx->current_pc - ctx->image->sections[section].base_address,
 663                         2, buf, &size_read)) != ERROR_OK)
 664                 {
 665                         LOG_ERROR("error while reading instruction: %i", retval);
 666                         return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
 667                 }
 668                 opcode = target_buffer_get_u16(ctx->target, buf);
 669                 thumb_evaluate_opcode(opcode, ctx->current_pc, instruction);
 670         }
 671         else if (ctx->core_state == ARMV4_5_STATE_JAZELLE)
 672         {
 673                 LOG_ERROR("BUG: tracing of jazelle code not supported");
 674                 exit(-1);
 675         }
 676         else
 677         {
 678                 LOG_ERROR("BUG: unknown core state encountered");
 679                 exit(-1);
 680         }
 681
 682         return ERROR_OK;
 683 }
 684
 685 static int etmv1_next_packet(etm_context_t *ctx, uint8_t *packet, int apo)
 686 {
 687         while (ctx->data_index < ctx->trace_depth)
 688         {
 689                 /* if the caller specified an address packet offset, skip until the
 690                  * we reach the n-th cycle marked with tracesync */
 691                 if (apo > 0)
 692                 {
 693                         if (ctx->trace_data[ctx->data_index].flags & ETMV1_TRACESYNC_CYCLE)
 694                                 apo--;
 695
 696                         if (apo > 0)
 697                         {
 698                                 ctx->data_index++;
 699                                 ctx->data_half = 0;
 700                         }
 701                         continue;
 702                 }
 703
 704                 /* no tracedata output during a TD cycle
 705                  * or in a trigger cycle */
 706                 if ((ctx->trace_data[ctx->data_index].pipestat == STAT_TD)
 707                         || (ctx->trace_data[ctx->data_index].flags & ETMV1_TRIGGER_CYCLE))
 708                 {
 709                         ctx->data_index++;
 710                         ctx->data_half = 0;
 711                         continue;
 712                 }
 713
 714                 if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_16BIT)
 715                 {
 716                         if (ctx->data_half == 0)
 717                         {
 718                                 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
 719                                 ctx->data_half = 1;
 720                         }
 721                         else
 722                         {
 723                                 *packet = (ctx->trace_data[ctx->data_index].packet & 0xff00) >> 8;
 724                                 ctx->data_half = 0;
 725                                 ctx->data_index++;
 726                         }
 727                 }
 728                 else if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
 729                 {
 730                         *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
 731                         ctx->data_index++;
 732                 }
 733                 else
 734                 {
 735                         /* on a 4-bit port, a packet will be output during two consecutive cycles */
 736                         if (ctx->data_index > (ctx->trace_depth - 2))
 737                                 return -1;
 738
 739                         *packet = ctx->trace_data[ctx->data_index].packet & 0xf;
 740                         *packet |= (ctx->trace_data[ctx->data_index + 1].packet & 0xf) << 4;
 741                         ctx->data_index += 2;
 742                 }
 743
 744                 return 0;
 745         }
 746
 747         return -1;
 748 }
 749
 750 static int etmv1_branch_address(etm_context_t *ctx)
 751 {
 752         int retval;
 753         uint8_t packet;
 754         int shift = 0;
 755         int apo;
 756         uint32_t i;
 757
 758         /* quit analysis if less than two cycles are left in the trace
 759          * because we can't extract the APO */
 760         if (ctx->data_index > (ctx->trace_depth - 2))
 761                 return -1;
 762
 763         /* a BE could be output during an APO cycle, skip the current
 764          * and continue with the new one */
 765         if (ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x4)
 766                 return 1;
 767         if (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x4)
 768                 return 2;
 769
 770         /* address packet offset encoded in the next two cycles' pipestat bits */
 771         apo = ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x3;
 772         apo |= (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x3) << 2;
 773
 774         /* count number of tracesync cycles between current pipe_index and data_index
 775          * i.e. the number of tracesyncs that data_index already passed by
 776          * to subtract them from the APO */
 777         for (i = ctx->pipe_index; i < ctx->data_index; i++)
 778         {
 779                 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & ETMV1_TRACESYNC_CYCLE)
 780                         apo--;
 781         }
 782
 783         /* extract up to four 7-bit packets */
 784         do {
 785                 if ((retval = etmv1_next_packet(ctx, &packet, (shift == 0) ? apo + 1 : 0)) != 0)
 786                         return -1;
 787                 ctx->last_branch &= ~(0x7f << shift);
 788                 ctx->last_branch |= (packet & 0x7f) << shift;
 789                 shift += 7;
 790         } while ((packet & 0x80) && (shift < 28));
 791
 792         /* one last packet holding 4 bits of the address, plus the branch reason code */
 793         if ((shift == 28) && (packet & 0x80))
 794         {
 795                 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
 796                         return -1;
 797                 ctx->last_branch &= 0x0fffffff;
 798                 ctx->last_branch |= (packet & 0x0f) << 28;
 799                 ctx->last_branch_reason = (packet & 0x70) >> 4;
 800                 shift += 4;
 801         }
 802         else
 803         {
 804                 ctx->last_branch_reason = 0;
 805         }
 806
 807         if (shift == 32)
 808         {
 809                 ctx->pc_ok = 1;
 810         }
 811
 812         /* if a full address was output, we might have branched into Jazelle state */
 813         if ((shift == 32) && (packet & 0x80))
 814         {
 815                 ctx->core_state = ARMV4_5_STATE_JAZELLE;
 816         }
 817         else
 818         {
 819                 /* if we didn't branch into Jazelle state, the current processor state is
 820                  * encoded in bit 0 of the branch target address */
 821                 if (ctx->last_branch & 0x1)
 822                 {
 823                         ctx->core_state = ARMV4_5_STATE_THUMB;
 824                         ctx->last_branch &= ~0x1;
 825                 }
 826                 else
 827                 {
 828                         ctx->core_state = ARMV4_5_STATE_ARM;
 829                         ctx->last_branch &= ~0x3;
 830                 }
 831         }
 832
 833         return 0;
 834 }
 835
 836 static int etmv1_data(etm_context_t *ctx, int size, uint32_t *data)
 837 {
 838         int j;
 839         uint8_t buf[4];
 840         int retval;
 841
 842         for (j = 0; j < size; j++)
 843         {
 844                 if ((retval = etmv1_next_packet(ctx, &buf[j], 0)) != 0)
 845                         return -1;
 846         }
 847
 848         if (size == 8)
 849         {
 850                 LOG_ERROR("TODO: add support for 64-bit values");
 851                 return -1;
 852         }
 853         else if (size == 4)
 854                 *data = target_buffer_get_u32(ctx->target, buf);
 855         else if (size == 2)
 856                 *data = target_buffer_get_u16(ctx->target, buf);
 857         else if (size == 1)
 858                 *data = buf[0];
 859         else
 860                 return -1;
 861
 862         return 0;
 863 }
 864
 865 static int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd_ctx)
 866 {
 867         int retval;
 868         arm_instruction_t instruction;
 869
 870         /* read the trace data if it wasn't read already */
 871         if (ctx->trace_depth == 0)
 872                 ctx->capture_driver->read_trace(ctx);
 873
 874         /* start at the beginning of the captured trace */
 875         ctx->pipe_index = 0;
 876         ctx->data_index = 0;
 877         ctx->data_half = 0;
 878
 879         /* neither the PC nor the data pointer are valid */
 880         ctx->pc_ok = 0;
 881         ctx->ptr_ok = 0;
 882
 883         while (ctx->pipe_index < ctx->trace_depth)
 884         {
 885                 uint8_t pipestat = ctx->trace_data[ctx->pipe_index].pipestat;
 886                 uint32_t next_pc = ctx->current_pc;
 887                 uint32_t old_data_index = ctx->data_index;
 888                 uint32_t old_data_half = ctx->data_half;
 889                 uint32_t old_index = ctx->pipe_index;
 890                 uint32_t last_instruction = ctx->last_instruction;
 891                 uint32_t cycles = 0;
 892                 int current_pc_ok = ctx->pc_ok;
 893
 894                 if (ctx->trace_data[ctx->pipe_index].flags & ETMV1_TRIGGER_CYCLE)
 895                 {
 896                         command_print(cmd_ctx, "--- trigger ---");
 897                 }
 898
 899                 /* instructions execute in IE/D or BE/D cycles */
 900                 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
 901                         ctx->last_instruction = ctx->pipe_index;
 902
 903                 /* if we don't have a valid pc skip until we reach an indirect branch */
 904                 if ((!ctx->pc_ok) && (pipestat != STAT_BE))
 905                 {
 906                         ctx->pipe_index++;
 907                         continue;
 908                 }
 909
 910                 /* any indirect branch could have interrupted instruction flow
 911                  * - the branch reason code could indicate a trace discontinuity
 912                  * - a branch to the exception vectors indicates an exception
 913                  */
 914                 if ((pipestat == STAT_BE) || (pipestat == STAT_BD))
 915                 {
 916                         /* backup current data index, to be able to consume the branch address
 917                          * before examining data address and values
 918                          */
 919                         old_data_index = ctx->data_index;
 920                         old_data_half = ctx->data_half;
 921
 922                         ctx->last_instruction = ctx->pipe_index;
 923
 924                         if ((retval = etmv1_branch_address(ctx)) != 0)
 925                         {
 926                                 /* negative return value from etmv1_branch_address means we ran out of packets,
 927                                  * quit analysing the trace */
 928                                 if (retval < 0)
 929                                         break;
 930
 931                                 /* a positive return values means the current branch was abandoned,
 932                                  * and a new branch was encountered in cycle ctx->pipe_index + retval;
 933                                  */
 934                                 LOG_WARNING("abandoned branch encountered, correctnes of analysis uncertain");
 935                                 ctx->pipe_index += retval;
 936                                 continue;
 937                         }
 938
 939                         /* skip over APO cycles */
 940                         ctx->pipe_index += 2;
 941
 942                         switch (ctx->last_branch_reason)
 943                         {
 944                                 case 0x0:       /* normal PC change */
 945                                         next_pc = ctx->last_branch;
 946                                         break;
 947                                 case 0x1:       /* tracing enabled */
 948                                         command_print(cmd_ctx, "--- tracing enabled at 0x%8.8" PRIx32 " ---", ctx->last_branch);
 949                                         ctx->current_pc = ctx->last_branch;
 950                                         ctx->pipe_index++;
 951                                         continue;
 952                                         break;
 953                                 case 0x2:       /* trace restarted after FIFO overflow */
 954                                         command_print(cmd_ctx, "--- trace restarted after FIFO overflow at 0x%8.8" PRIx32 " ---", ctx->last_branch);
 955                                         ctx->current_pc = ctx->last_branch;
 956                                         ctx->pipe_index++;
 957                                         continue;
 958                                         break;
 959                                 case 0x3:       /* exit from debug state */
 960                                         command_print(cmd_ctx, "--- exit from debug state at 0x%8.8" PRIx32 " ---", ctx->last_branch);
 961                                         ctx->current_pc = ctx->last_branch;
 962                                         ctx->pipe_index++;
 963                                         continue;
 964                                         break;
 965                                 case 0x4:       /* periodic synchronization point */
 966                                         next_pc = ctx->last_branch;
 967                                         /* if we had no valid PC prior to this synchronization point,
 968                                          * we have to move on with the next trace cycle
 969                                          */
 970                                         if (!current_pc_ok)
 971                                         {
 972                                                 command_print(cmd_ctx, "--- periodic synchronization point at 0x%8.8" PRIx32 " ---", next_pc);
 973                                                 ctx->current_pc = next_pc;
 974                                                 ctx->pipe_index++;
 975                                                 continue;
 976                                         }
 977                                         break;
 978                                 default:        /* reserved */
 979                                         LOG_ERROR("BUG: branch reason code 0x%" PRIx32 " is reserved", ctx->last_branch_reason);
 980                                         exit(-1);
 981                                         break;
 982                         }
 983
 984                         /* if we got here the branch was a normal PC change
 985                          * (or a periodic synchronization point, which means the same for that matter)
 986                          * if we didn't accquire a complete PC continue with the next cycle
 987                          */
 988                         if (!ctx->pc_ok)
 989                                 continue;
 990
 991                         /* indirect branch to the exception vector means an exception occured */
 992                         if ((ctx->last_branch <= 0x20)
 993                                 || ((ctx->last_branch >= 0xffff0000) && (ctx->last_branch <= 0xffff0020)))
 994                         {
 995                                 if ((ctx->last_branch & 0xff) == 0x10)
 996                                 {
 997                                         command_print(cmd_ctx, "data abort");
 998                                 }
 999                                 else
1000                                 {
1001                                         command_print(cmd_ctx, "exception vector 0x%2.2" PRIx32 "", ctx->last_branch);
1002                                         ctx->current_pc = ctx->last_branch;
1003                                         ctx->pipe_index++;
1004                                         continue;
1005                                 }
1006                         }
1007                 }
1008
1009                 /* an instruction was executed (or not, depending on the condition flags)
1010                  * retrieve it from the image for displaying */
1011                 if (ctx->pc_ok && (pipestat != STAT_WT) && (pipestat != STAT_TD) &&
1012                         !(((pipestat == STAT_BE) || (pipestat == STAT_BD)) &&
1013                                 ((ctx->last_branch_reason != 0x0) && (ctx->last_branch_reason != 0x4))))
1014                 {
1015                         if ((retval = etm_read_instruction(ctx, &instruction)) != ERROR_OK)
1016                         {
1017                                 /* can't continue tracing with no image available */
1018                                 if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
1019                                 {
1020                                         return retval;
1021                                 }
1022                                 else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE)
1023                                 {
1024                                         /* TODO: handle incomplete images
1025                                          * for now we just quit the analsysis*/
1026                                         return retval;
1027                                 }
1028                         }
1029
1030                         cycles = old_index - last_instruction;
1031                 }
1032
1033                 if ((pipestat == STAT_ID) || (pipestat == STAT_BD))
1034                 {
1035                         uint32_t new_data_index = ctx->data_index;
1036                         uint32_t new_data_half = ctx->data_half;
1037
1038                         /* in case of a branch with data, the branch target address was consumed before
1039                          * we temporarily go back to the saved data index */
1040                         if (pipestat == STAT_BD)
1041                         {
1042                                 ctx->data_index = old_data_index;
1043                                 ctx->data_half = old_data_half;
1044                         }
1045
1046                         if (ctx->tracemode & ETMV1_TRACE_ADDR)
1047                         {
1048                                 uint8_t packet;
1049                                 int shift = 0;
1050
1051                                 do {
1052                                         if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
1053                                                 return ERROR_ETM_ANALYSIS_FAILED;
1054                                         ctx->last_ptr &= ~(0x7f << shift);
1055                                         ctx->last_ptr |= (packet & 0x7f) << shift;
1056                                         shift += 7;
1057                                 } while ((packet & 0x80) && (shift < 32));
1058
1059                                 if (shift >= 32)
1060                                         ctx->ptr_ok = 1;
1061
1062                                 if (ctx->ptr_ok)
1063                                 {
1064                                         command_print(cmd_ctx, "address: 0x%8.8" PRIx32 "", ctx->last_ptr);
1065                                 }
1066                         }
1067
1068                         if (ctx->tracemode & ETMV1_TRACE_DATA)
1069                         {
1070                                 if ((instruction.type == ARM_LDM) || (instruction.type == ARM_STM))
1071                                 {
1072                                         int i;
1073                                         for (i = 0; i < 16; i++)
1074                                         {
1075                                                 if (instruction.info.load_store_multiple.register_list & (1 << i))
1076                                                 {
1077                                                         uint32_t data;
1078                                                         if (etmv1_data(ctx, 4, &data) != 0)
1079                                                                 return ERROR_ETM_ANALYSIS_FAILED;
1080                                                         command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
1081                                                 }
1082                                         }
1083                                 }
1084                                 else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_STRH))
1085                                 {
1086                                         uint32_t data;
1087                                         if (etmv1_data(ctx, arm_access_size(&instruction), &data) != 0)
1088                                                 return ERROR_ETM_ANALYSIS_FAILED;
1089                                         command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
1090                                 }
1091                         }
1092
1093                         /* restore data index after consuming BD address and data */
1094                         if (pipestat == STAT_BD)
1095                         {
1096                                 ctx->data_index = new_data_index;
1097                                 ctx->data_half = new_data_half;
1098                         }
1099                 }
1100
1101                 /* adjust PC */
1102                 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
1103                 {
1104                         if (((instruction.type == ARM_B) ||
1105                              (instruction.type == ARM_BL) ||
1106                              (instruction.type == ARM_BLX)) &&
1107                             (instruction.info.b_bl_bx_blx.target_address != 0xffffffff))
1108                         {
1109                                 next_pc = instruction.info.b_bl_bx_blx.target_address;
1110                         }
1111                         else
1112                         {
1113                                 next_pc += (ctx->core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
1114                         }
1115                 }
1116                 else if (pipestat == STAT_IN)
1117                 {
1118                         next_pc += (ctx->core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
1119                 }
1120
1121                 if ((pipestat != STAT_TD) && (pipestat != STAT_WT))
1122                 {
1123                         char cycles_text[32] = "";
1124
1125                         /* if the trace was captured with cycle accurate tracing enabled,
1126                          * output the number of cycles since the last executed instruction
1127                          */
1128                         if (ctx->tracemode & ETMV1_CYCLE_ACCURATE)
1129                         {
1130                                 snprintf(cycles_text, 32, " (%i %s)",
1131                                          (int)cycles,
1132                                         (cycles == 1) ? "cycle" : "cycles");
1133                         }
1134
1135                         command_print(cmd_ctx, "%s%s%s",
1136                                 instruction.text,
1137                                 (pipestat == STAT_IN) ? " (not executed)" : "",
1138                                 cycles_text);
1139
1140                         ctx->current_pc = next_pc;
1141
1142                         /* packets for an instruction don't start on or before the preceding
1143                          * functional pipestat (i.e. other than WT or TD)
1144                          */
1145                         if (ctx->data_index <= ctx->pipe_index)
1146                         {
1147                                 ctx->data_index = ctx->pipe_index + 1;
1148                                 ctx->data_half = 0;
1149                         }
1150                 }
1151
1152                 ctx->pipe_index += 1;
1153         }
1154
1155         return ERROR_OK;
1156 }
1157
1158 static int handle_etm_tracemode_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1159 {
1160         target_t *target;
1161         armv4_5_common_t *armv4_5;
1162         arm7_9_common_t *arm7_9;
1163         etmv1_tracemode_t tracemode;
1164
1165         target = get_current_target(cmd_ctx);
1166
1167         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1168         {
1169                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1170                 return ERROR_OK;
1171         }
1172
1173         if (!arm7_9->etm_ctx)
1174         {
1175                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1176                 return ERROR_OK;
1177         }
1178
1179         tracemode = arm7_9->etm_ctx->tracemode;
1180
1181         if (argc == 4)
1182         {
1183                 /* what parts of data access are traced? */
1184                 if (strcmp(args[0], "none") == 0)
1185                 {
1186                         tracemode = ETMV1_TRACE_NONE;
1187                 }
1188                 else if (strcmp(args[0], "data") == 0)
1189                 {
1190                         tracemode = ETMV1_TRACE_DATA;
1191                 }
1192                 else if (strcmp(args[0], "address") == 0)
1193                 {
1194                         tracemode = ETMV1_TRACE_ADDR;
1195                 }
1196                 else if (strcmp(args[0], "all") == 0)
1197                 {
1198                         tracemode = ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR;
1199                 }
1200                 else
1201                 {
1202                         command_print(cmd_ctx, "invalid option '%s'", args[0]);
1203                         return ERROR_OK;
1204                 }
1205
1206                 switch (strtol(args[1], NULL, 0))
1207                 {
1208                         case 0:
1209                                 tracemode |= ETMV1_CONTEXTID_NONE;
1210                                 break;
1211                         case 8:
1212                                 tracemode |= ETMV1_CONTEXTID_8;
1213                                 break;
1214                         case 16:
1215                                 tracemode |= ETMV1_CONTEXTID_16;
1216                                 break;
1217                         case 32:
1218                                 tracemode |= ETMV1_CONTEXTID_32;
1219                                 break;
1220                         default:
1221                                 command_print(cmd_ctx, "invalid option '%s'", args[1]);
1222                                 return ERROR_OK;
1223                 }
1224
1225                 if (strcmp(args[2], "enable") == 0)
1226                 {
1227                         tracemode |= ETMV1_CYCLE_ACCURATE;
1228                 }
1229                 else if (strcmp(args[2], "disable") == 0)
1230                 {
1231                         tracemode |= 0;
1232                 }
1233                 else
1234                 {
1235                         command_print(cmd_ctx, "invalid option '%s'", args[2]);
1236                         return ERROR_OK;
1237                 }
1238
1239                 if (strcmp(args[3], "enable") == 0)
1240                 {
1241                         tracemode |= ETMV1_BRANCH_OUTPUT;
1242                 }
1243                 else if (strcmp(args[3], "disable") == 0)
1244                 {
1245                         tracemode |= 0;
1246                 }
1247                 else
1248                 {
1249                         command_print(cmd_ctx, "invalid option '%s'", args[2]);
1250                         return ERROR_OK;
1251                 }
1252
1253                 /* IGNORED:
1254                  *  - CPRT tracing (coprocessor register transfers)
1255                  *  - debug request (causes debug entry on trigger)
1256                  *  - stall on FIFOFULL (preventing tracedata lossage)
1257                  */
1258         }
1259         else if (argc != 0)
1260         {
1261                 command_print(cmd_ctx, "usage: configure trace mode <none | data | address | all> <context id bits> <cycle accurate> <branch output>");
1262                 return ERROR_OK;
1263         }
1264
1265         command_print(cmd_ctx, "current tracemode configuration:");
1266
1267         switch (tracemode & ETMV1_TRACE_MASK)
1268         {
1269                 case ETMV1_TRACE_NONE:
1270                         command_print(cmd_ctx, "data tracing: none");
1271                         break;
1272                 case ETMV1_TRACE_DATA:
1273                         command_print(cmd_ctx, "data tracing: data only");
1274                         break;
1275                 case ETMV1_TRACE_ADDR:
1276                         command_print(cmd_ctx, "data tracing: address only");
1277                         break;
1278                 case ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR:
1279                         command_print(cmd_ctx, "data tracing: address and data");
1280                         break;
1281         }
1282
1283         switch (tracemode & ETMV1_CONTEXTID_MASK)
1284         {
1285                 case ETMV1_CONTEXTID_NONE:
1286                         command_print(cmd_ctx, "contextid tracing: none");
1287                         break;
1288                 case ETMV1_CONTEXTID_8:
1289                         command_print(cmd_ctx, "contextid tracing: 8 bit");
1290                         break;
1291                 case ETMV1_CONTEXTID_16:
1292                         command_print(cmd_ctx, "contextid tracing: 16 bit");
1293                         break;
1294                 case ETMV1_CONTEXTID_32:
1295                         command_print(cmd_ctx, "contextid tracing: 32 bit");
1296                         break;
1297         }
1298
1299         if (tracemode & ETMV1_CYCLE_ACCURATE)
1300         {
1301                 command_print(cmd_ctx, "cycle-accurate tracing enabled");
1302         }
1303         else
1304         {
1305                 command_print(cmd_ctx, "cycle-accurate tracing disabled");
1306         }
1307
1308         if (tracemode & ETMV1_BRANCH_OUTPUT)
1309         {
1310                 command_print(cmd_ctx, "full branch address output enabled");
1311         }
1312         else
1313         {
1314                 command_print(cmd_ctx, "full branch address output disabled");
1315         }
1316
1317         /* only update ETM_CTRL register if tracemode changed */
1318         if (arm7_9->etm_ctx->tracemode != tracemode)
1319         {
1320                 reg_t *etm_ctrl_reg;
1321
1322                 etm_ctrl_reg = etm_reg_lookup(arm7_9->etm_ctx, ETM_CTRL);
1323                 if (!etm_ctrl_reg)
1324                         return ERROR_OK;
1325
1326                 etm_get_reg(etm_ctrl_reg);
1327
1328                 buf_set_u32(etm_ctrl_reg->value, 2, 2, tracemode & ETMV1_TRACE_MASK);
1329                 buf_set_u32(etm_ctrl_reg->value, 14, 2, (tracemode & ETMV1_CONTEXTID_MASK) >> 4);
1330                 buf_set_u32(etm_ctrl_reg->value, 12, 1, (tracemode & ETMV1_CYCLE_ACCURATE) >> 8);
1331                 buf_set_u32(etm_ctrl_reg->value, 8, 1, (tracemode & ETMV1_BRANCH_OUTPUT) >> 9);
1332                 etm_store_reg(etm_ctrl_reg);
1333
1334                 arm7_9->etm_ctx->tracemode = tracemode;
1335
1336                 /* invalidate old trace data */
1337                 arm7_9->etm_ctx->capture_status = TRACE_IDLE;
1338                 if (arm7_9->etm_ctx->trace_depth > 0)
1339                 {
1340                         free(arm7_9->etm_ctx->trace_data);
1341                         arm7_9->etm_ctx->trace_data = NULL;
1342                 }
1343                 arm7_9->etm_ctx->trace_depth = 0;
1344         }
1345
1346         return ERROR_OK;
1347 }
1348
1349 static int handle_etm_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1350 {
1351         target_t *target;
1352         armv4_5_common_t *armv4_5;
1353         arm7_9_common_t *arm7_9;
1354         etm_portmode_t portmode = 0x0;
1355         etm_context_t *etm_ctx = malloc(sizeof(etm_context_t));
1356         int i;
1357
1358         if (argc != 5)
1359         {
1360                 free(etm_ctx);
1361                 return ERROR_COMMAND_SYNTAX_ERROR;
1362         }
1363
1364         target = get_target(args[0]);
1365         if (!target)
1366         {
1367                 LOG_ERROR("target '%s' not defined", args[0]);
1368                 free(etm_ctx);
1369                 return ERROR_FAIL;
1370         }
1371
1372         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1373         {
1374                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1375                 free(etm_ctx);
1376                 return ERROR_FAIL;
1377         }
1378
1379         switch (strtoul(args[1], NULL, 0))
1380         {
1381                 case 4:
1382                         portmode |= ETM_PORT_4BIT;
1383                         break;
1384                 case 8:
1385                         portmode |= ETM_PORT_8BIT;
1386                         break;
1387                 case 16:
1388                         portmode |= ETM_PORT_16BIT;
1389                         break;
1390                 default:
1391                         command_print(cmd_ctx, "unsupported ETM port width '%s', must be 4, 8 or 16", args[1]);
1392                         free(etm_ctx);
1393                         return ERROR_FAIL;
1394         }
1395
1396         if (strcmp("normal", args[2]) == 0)
1397         {
1398                 portmode |= ETM_PORT_NORMAL;
1399         }
1400         else if (strcmp("multiplexed", args[2]) == 0)
1401         {
1402                 portmode |= ETM_PORT_MUXED;
1403         }
1404         else if (strcmp("demultiplexed", args[2]) == 0)
1405         {
1406                 portmode |= ETM_PORT_DEMUXED;
1407         }
1408         else
1409         {
1410                 command_print(cmd_ctx, "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", args[2]);
1411                 free(etm_ctx);
1412                 return ERROR_FAIL;
1413         }
1414
1415         if (strcmp("half", args[3]) == 0)
1416         {
1417                 portmode |= ETM_PORT_HALF_CLOCK;
1418         }
1419         else if (strcmp("full", args[3]) == 0)
1420         {
1421                 portmode |= ETM_PORT_FULL_CLOCK;
1422         }
1423         else
1424         {
1425                 command_print(cmd_ctx, "unsupported ETM port clocking '%s', must be 'full' or 'half'", args[3]);
1426                 free(etm_ctx);
1427                 return ERROR_FAIL;
1428         }
1429
1430         for (i = 0; etm_capture_drivers[i]; i++)
1431         {
1432                 if (strcmp(args[4], etm_capture_drivers[i]->name) == 0)
1433                 {
1434                         int retval;
1435                         if ((retval = etm_capture_drivers[i]->register_commands(cmd_ctx)) != ERROR_OK)
1436                         {
1437                                 free(etm_ctx);
1438                                 return retval;
1439                         }
1440
1441                         etm_ctx->capture_driver = etm_capture_drivers[i];
1442
1443                         break;
1444                 }
1445         }
1446
1447         if (!etm_capture_drivers[i])
1448         {
1449                 /* no supported capture driver found, don't register an ETM */
1450                 free(etm_ctx);
1451                 LOG_ERROR("trace capture driver '%s' not found", args[4]);
1452                 return ERROR_FAIL;
1453         }
1454
1455         etm_ctx->target = target;
1456         etm_ctx->trigger_percent = 50;
1457         etm_ctx->trace_data = NULL;
1458         etm_ctx->trace_depth = 0;
1459         etm_ctx->portmode = portmode;
1460         etm_ctx->tracemode = 0x0;
1461         etm_ctx->core_state = ARMV4_5_STATE_ARM;
1462         etm_ctx->image = NULL;
1463         etm_ctx->pipe_index = 0;
1464         etm_ctx->data_index = 0;
1465         etm_ctx->current_pc = 0x0;
1466         etm_ctx->pc_ok = 0;
1467         etm_ctx->last_branch = 0x0;
1468         etm_ctx->last_branch_reason = 0x0;
1469         etm_ctx->last_ptr = 0x0;
1470         etm_ctx->ptr_ok = 0x0;
1471         etm_ctx->last_instruction = 0;
1472
1473         arm7_9->etm_ctx = etm_ctx;
1474
1475         return etm_register_user_commands(cmd_ctx);
1476 }
1477
1478 static int handle_etm_info_command(struct command_context_s *cmd_ctx,
1479                 char *cmd, char **args, int argc)
1480 {
1481         target_t *target;
1482         armv4_5_common_t *armv4_5;
1483         arm7_9_common_t *arm7_9;
1484         etm_context_t *etm;
1485         reg_t *etm_sys_config_reg;
1486
1487         int max_port_size;
1488
1489         target = get_current_target(cmd_ctx);
1490
1491         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1492         {
1493                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1494                 return ERROR_OK;
1495         }
1496
1497         etm = arm7_9->etm_ctx;
1498         if (!etm)
1499         {
1500                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1501                 return ERROR_OK;
1502         }
1503
1504         command_print(cmd_ctx, "ETM v%d.%d",
1505                         etm->bcd_vers >> 4, etm->bcd_vers & 0xf);
1506         command_print(cmd_ctx, "pairs of address comparators: %i",
1507                         (int) (etm->config >> 0) & 0x0f);
1508         command_print(cmd_ctx, "data comparators: %i",
1509                         (int) (etm->config >> 4) & 0x0f);
1510         command_print(cmd_ctx, "memory map decoders: %i",
1511                         (int) (etm->config >> 8) & 0x1f);
1512         command_print(cmd_ctx, "number of counters: %i",
1513                         (int) (etm->config >> 13) & 0x07);
1514         command_print(cmd_ctx, "sequencer %spresent",
1515                         (int) (etm->config & (1 << 16)) ? "" : "not ");
1516         command_print(cmd_ctx, "number of ext. inputs: %i",
1517                         (int) (etm->config >> 17) & 0x07);
1518         command_print(cmd_ctx, "number of ext. outputs: %i",
1519                         (int) (etm->config >> 20) & 0x07);
1520         command_print(cmd_ctx, "FIFO full %spresent",
1521                         (int) (etm->config & (1 << 23)) ? "" : "not ");
1522         if (etm->bcd_vers < 0x20)
1523                 command_print(cmd_ctx, "protocol version: %i",
1524                                 (int) (etm->config >> 28) & 0x07);
1525         else {
1526                 command_print(cmd_ctx, "trace start/stop %spresent",
1527                                 (etm->config & (1 << 26)) ? "" : "not ");
1528                 command_print(cmd_ctx, "number of context comparators: %i",
1529                                 (int) (etm->config >> 24) & 0x03);
1530         }
1531
1532         /* SYS_CONFIG isn't present before ETMv1.2 */
1533         etm_sys_config_reg = etm_reg_lookup(etm, ETM_SYS_CONFIG);
1534         if (!etm_sys_config_reg)
1535                 return ERROR_OK;
1536
1537         etm_get_reg(etm_sys_config_reg);
1538
1539         switch (buf_get_u32(etm_sys_config_reg->value, 0, 3))
1540         {
1541                 case 0:
1542                         max_port_size = 4;
1543                         break;
1544                 case 1:
1545                         max_port_size = 8;
1546                         break;
1547                 case 2:
1548                         max_port_size = 16;
1549                         break;
1550                 default:
1551                         LOG_ERROR("Illegal max_port_size");
1552                         exit(-1);
1553         }
1554         command_print(cmd_ctx, "max. port size: %i", max_port_size);
1555
1556         command_print(cmd_ctx, "half-rate clocking %ssupported",
1557                         (buf_get_u32(etm_sys_config_reg->value, 3, 1) == 1) ? "" : "not ");
1558         command_print(cmd_ctx, "full-rate clocking %ssupported",
1559                         (buf_get_u32(etm_sys_config_reg->value, 4, 1) == 1) ? "" : "not ");
1560         command_print(cmd_ctx, "normal trace format %ssupported",
1561                         (buf_get_u32(etm_sys_config_reg->value, 5, 1) == 1) ? "" : "not ");
1562         command_print(cmd_ctx, "multiplex trace format %ssupported",
1563                         (buf_get_u32(etm_sys_config_reg->value, 6, 1) == 1) ? "" : "not ");
1564         command_print(cmd_ctx, "demultiplex trace format %ssupported",
1565                         (buf_get_u32(etm_sys_config_reg->value, 7, 1) == 1) ? "" : "not ");
1566         command_print(cmd_ctx, "FIFO full %ssupported",
1567                         (buf_get_u32(etm_sys_config_reg->value, 8, 1) == 1) ? "" : "not ");
1568
1569         return ERROR_OK;
1570 }
1571
1572 static int handle_etm_status_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1573 {
1574         target_t *target;
1575         armv4_5_common_t *armv4_5;
1576         arm7_9_common_t *arm7_9;
1577         etm_context_t *etm;
1578         trace_status_t trace_status;
1579
1580         target = get_current_target(cmd_ctx);
1581
1582         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1583         {
1584                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1585                 return ERROR_OK;
1586         }
1587
1588         if (!arm7_9->etm_ctx)
1589         {
1590                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1591                 return ERROR_OK;
1592         }
1593         etm = arm7_9->etm_ctx;
1594
1595         /* ETM status */
1596         if (etm->bcd_vers >= 0x11) {
1597                 reg_t *reg;
1598
1599                 reg = etm_reg_lookup(etm, ETM_STATUS);
1600                 if (!reg)
1601                         return ERROR_OK;
1602                 if (etm_get_reg(reg) == ERROR_OK) {
1603                         unsigned s = buf_get_u32(reg->value, 0, reg->size);
1604
1605                         command_print(cmd_ctx, "etm: %s%s%s%s",
1606                                 /* bit(1) == progbit */
1607                                 (etm->bcd_vers >= 0x12)
1608                                         ? ((s & (1 << 1))
1609                                                 ? "disabled" : "enabled")
1610                                         : "?",
1611                                 ((s & (1 << 3)) && etm->bcd_vers >= 0x31)
1612                                         ? " triggered" : "",
1613                                 ((s & (1 << 2)) && etm->bcd_vers >= 0x12)
1614                                         ? " start/stop" : "",
1615                                 ((s & (1 << 0)) && etm->bcd_vers >= 0x11)
1616                                         ? " untraced-overflow" : "");
1617                 } /* else ignore and try showing trace port status */
1618         }
1619
1620         /* Trace Port Driver status */
1621         trace_status = etm->capture_driver->status(etm);
1622         if (trace_status == TRACE_IDLE)
1623         {
1624                 command_print(cmd_ctx, "%s: idle", etm->capture_driver->name);
1625         }
1626         else
1627         {
1628                 static char *completed = " completed";
1629                 static char *running = " is running";
1630                 static char *overflowed = ", overflowed";
1631                 static char *triggered = ", triggered";
1632
1633                 command_print(cmd_ctx, "%s: trace collection%s%s%s",
1634                         etm->capture_driver->name,
1635                         (trace_status & TRACE_RUNNING) ? running : completed,
1636                         (trace_status & TRACE_OVERFLOWED) ? overflowed : "",
1637                         (trace_status & TRACE_TRIGGERED) ? triggered : "");
1638
1639                 if (etm->trace_depth > 0)
1640                 {
1641                         command_print(cmd_ctx, "%i frames of trace data read",
1642                                         (int)(etm->trace_depth));
1643                 }
1644         }
1645
1646         return ERROR_OK;
1647 }
1648
1649 static int handle_etm_image_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1650 {
1651         target_t *target;
1652         armv4_5_common_t *armv4_5;
1653         arm7_9_common_t *arm7_9;
1654         etm_context_t *etm_ctx;
1655
1656         if (argc < 1)
1657         {
1658                 command_print(cmd_ctx, "usage: etm image <file> [base address] [type]");
1659                 return ERROR_OK;
1660         }
1661
1662         target = get_current_target(cmd_ctx);
1663
1664         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1665         {
1666                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1667                 return ERROR_OK;
1668         }
1669
1670         if (!(etm_ctx = arm7_9->etm_ctx))
1671         {
1672                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1673                 return ERROR_OK;
1674         }
1675
1676         if (etm_ctx->image)
1677         {
1678                 image_close(etm_ctx->image);
1679                 free(etm_ctx->image);
1680                 command_print(cmd_ctx, "previously loaded image found and closed");
1681         }
1682
1683         etm_ctx->image = malloc(sizeof(image_t));
1684         etm_ctx->image->base_address_set = 0;
1685         etm_ctx->image->start_address_set = 0;
1686
1687         /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1688         if (argc >= 2)
1689         {
1690                 etm_ctx->image->base_address_set = 1;
1691                 etm_ctx->image->base_address = strtoul(args[1], NULL, 0);
1692         }
1693         else
1694         {
1695                 etm_ctx->image->base_address_set = 0;
1696         }
1697
1698         if (image_open(etm_ctx->image, args[0], (argc >= 3) ? args[2] : NULL) != ERROR_OK)
1699         {
1700                 free(etm_ctx->image);
1701                 etm_ctx->image = NULL;
1702                 return ERROR_OK;
1703         }
1704
1705         return ERROR_OK;
1706 }
1707
1708 static int handle_etm_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1709 {
1710         fileio_t file;
1711         target_t *target;
1712         armv4_5_common_t *armv4_5;
1713         arm7_9_common_t *arm7_9;
1714         etm_context_t *etm_ctx;
1715         uint32_t i;
1716
1717         if (argc != 1)
1718         {
1719                 command_print(cmd_ctx, "usage: etm dump <file>");
1720                 return ERROR_OK;
1721         }
1722
1723         target = get_current_target(cmd_ctx);
1724
1725         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1726         {
1727                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1728                 return ERROR_OK;
1729         }
1730
1731         if (!(etm_ctx = arm7_9->etm_ctx))
1732         {
1733                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1734                 return ERROR_OK;
1735         }
1736
1737         if (etm_ctx->capture_driver->status == TRACE_IDLE)
1738         {
1739                 command_print(cmd_ctx, "trace capture wasn't enabled, no trace data captured");
1740                 return ERROR_OK;
1741         }
1742
1743         if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1744         {
1745                 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1746                 command_print(cmd_ctx, "trace capture not completed");
1747                 return ERROR_OK;
1748         }
1749
1750         /* read the trace data if it wasn't read already */
1751         if (etm_ctx->trace_depth == 0)
1752                 etm_ctx->capture_driver->read_trace(etm_ctx);
1753
1754         if (fileio_open(&file, args[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1755         {
1756                 return ERROR_OK;
1757         }
1758
1759         fileio_write_u32(&file, etm_ctx->capture_status);
1760         fileio_write_u32(&file, etm_ctx->portmode);
1761         fileio_write_u32(&file, etm_ctx->tracemode);
1762         fileio_write_u32(&file, etm_ctx->trace_depth);
1763
1764         for (i = 0; i < etm_ctx->trace_depth; i++)
1765         {
1766                 fileio_write_u32(&file, etm_ctx->trace_data[i].pipestat);
1767                 fileio_write_u32(&file, etm_ctx->trace_data[i].packet);
1768                 fileio_write_u32(&file, etm_ctx->trace_data[i].flags);
1769         }
1770
1771         fileio_close(&file);
1772
1773         return ERROR_OK;
1774 }
1775
1776 static int handle_etm_load_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1777 {
1778         fileio_t file;
1779         target_t *target;
1780         armv4_5_common_t *armv4_5;
1781         arm7_9_common_t *arm7_9;
1782         etm_context_t *etm_ctx;
1783         uint32_t i;
1784
1785         if (argc != 1)
1786         {
1787                 command_print(cmd_ctx, "usage: etm load <file>");
1788                 return ERROR_OK;
1789         }
1790
1791         target = get_current_target(cmd_ctx);
1792
1793         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1794         {
1795                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1796                 return ERROR_OK;
1797         }
1798
1799         if (!(etm_ctx = arm7_9->etm_ctx))
1800         {
1801                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1802                 return ERROR_OK;
1803         }
1804
1805         if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1806         {
1807                 command_print(cmd_ctx, "trace capture running, stop first");
1808                 return ERROR_OK;
1809         }
1810
1811         if (fileio_open(&file, args[0], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1812         {
1813                 return ERROR_OK;
1814         }
1815
1816         if (file.size % 4)
1817         {
1818                 command_print(cmd_ctx, "size isn't a multiple of 4, no valid trace data");
1819                 fileio_close(&file);
1820                 return ERROR_OK;
1821         }
1822
1823         if (etm_ctx->trace_depth > 0)
1824         {
1825                 free(etm_ctx->trace_data);
1826                 etm_ctx->trace_data = NULL;
1827         }
1828
1829         {
1830           uint32_t tmp;
1831           fileio_read_u32(&file, &tmp); etm_ctx->capture_status = tmp;
1832           fileio_read_u32(&file, &tmp); etm_ctx->portmode = tmp;
1833           fileio_read_u32(&file, &tmp); etm_ctx->tracemode = tmp;
1834           fileio_read_u32(&file, &etm_ctx->trace_depth);
1835         }
1836         etm_ctx->trace_data = malloc(sizeof(etmv1_trace_data_t) * etm_ctx->trace_depth);
1837         if (etm_ctx->trace_data == NULL)
1838         {
1839                 command_print(cmd_ctx, "not enough memory to perform operation");
1840                 fileio_close(&file);
1841                 return ERROR_OK;
1842         }
1843
1844         for (i = 0; i < etm_ctx->trace_depth; i++)
1845         {
1846                 uint32_t pipestat, packet, flags;
1847                 fileio_read_u32(&file, &pipestat);
1848                 fileio_read_u32(&file, &packet);
1849                 fileio_read_u32(&file, &flags);
1850                 etm_ctx->trace_data[i].pipestat = pipestat & 0xff;
1851                 etm_ctx->trace_data[i].packet = packet & 0xffff;
1852                 etm_ctx->trace_data[i].flags = flags;
1853         }
1854
1855         fileio_close(&file);
1856
1857         return ERROR_OK;
1858 }
1859
1860 static int handle_etm_trigger_percent_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1861 {
1862         target_t *target;
1863         armv4_5_common_t *armv4_5;
1864         arm7_9_common_t *arm7_9;
1865         etm_context_t *etm_ctx;
1866
1867         target = get_current_target(cmd_ctx);
1868
1869         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1870         {
1871                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1872                 return ERROR_OK;
1873         }
1874
1875         if (!(etm_ctx = arm7_9->etm_ctx))
1876         {
1877                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1878                 return ERROR_OK;
1879         }
1880
1881         if (argc > 0)
1882         {
1883                 uint32_t new_value = strtoul(args[0], NULL, 0);
1884
1885                 if ((new_value < 2) || (new_value > 100))
1886                 {
1887                         command_print(cmd_ctx, "valid settings are 2%% to 100%%");
1888                 }
1889                 else
1890                 {
1891                         etm_ctx->trigger_percent = new_value;
1892                 }
1893         }
1894
1895         command_print(cmd_ctx, "%i percent of the tracebuffer reserved for after the trigger", ((int)(etm_ctx->trigger_percent)));
1896
1897         return ERROR_OK;
1898 }
1899
1900 static int handle_etm_start_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1901 {
1902         target_t *target;
1903         armv4_5_common_t *armv4_5;
1904         arm7_9_common_t *arm7_9;
1905         etm_context_t *etm_ctx;
1906         reg_t *etm_ctrl_reg;
1907
1908         target = get_current_target(cmd_ctx);
1909
1910         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1911         {
1912                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1913                 return ERROR_OK;
1914         }
1915
1916         if (!(etm_ctx = arm7_9->etm_ctx))
1917         {
1918                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1919                 return ERROR_OK;
1920         }
1921
1922         /* invalidate old tracing data */
1923         arm7_9->etm_ctx->capture_status = TRACE_IDLE;
1924         if (arm7_9->etm_ctx->trace_depth > 0)
1925         {
1926                 free(arm7_9->etm_ctx->trace_data);
1927                 arm7_9->etm_ctx->trace_data = NULL;
1928         }
1929         arm7_9->etm_ctx->trace_depth = 0;
1930
1931         etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
1932         if (!etm_ctrl_reg)
1933                 return ERROR_OK;
1934
1935         etm_get_reg(etm_ctrl_reg);
1936
1937         /* Clear programming bit (10), set port selection bit (11) */
1938         buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x2);
1939
1940         etm_store_reg(etm_ctrl_reg);
1941         jtag_execute_queue();
1942
1943         etm_ctx->capture_driver->start_capture(etm_ctx);
1944
1945         return ERROR_OK;
1946 }
1947
1948 static int handle_etm_stop_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1949 {
1950         target_t *target;
1951         armv4_5_common_t *armv4_5;
1952         arm7_9_common_t *arm7_9;
1953         etm_context_t *etm_ctx;
1954         reg_t *etm_ctrl_reg;
1955
1956         target = get_current_target(cmd_ctx);
1957
1958         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1959         {
1960                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1961                 return ERROR_OK;
1962         }
1963
1964         if (!(etm_ctx = arm7_9->etm_ctx))
1965         {
1966                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1967                 return ERROR_OK;
1968         }
1969
1970         etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
1971         if (!etm_ctrl_reg)
1972                 return ERROR_OK;
1973
1974         etm_get_reg(etm_ctrl_reg);
1975
1976         /* Set programming bit (10), clear port selection bit (11) */
1977         buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x1);
1978
1979         etm_store_reg(etm_ctrl_reg);
1980         jtag_execute_queue();
1981
1982         etm_ctx->capture_driver->stop_capture(etm_ctx);
1983
1984         return ERROR_OK;
1985 }
1986
1987 static int handle_etm_analyze_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1988 {
1989         target_t *target;
1990         armv4_5_common_t *armv4_5;
1991         arm7_9_common_t *arm7_9;
1992         etm_context_t *etm_ctx;
1993         int retval;
1994
1995         target = get_current_target(cmd_ctx);
1996
1997         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1998         {
1999                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2000                 return ERROR_OK;
2001         }
2002
2003         if (!(etm_ctx = arm7_9->etm_ctx))
2004         {
2005                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
2006                 return ERROR_OK;
2007         }
2008
2009         if ((retval = etmv1_analyze_trace(etm_ctx, cmd_ctx)) != ERROR_OK)
2010         {
2011                 switch (retval)
2012                 {
2013                         case ERROR_ETM_ANALYSIS_FAILED:
2014                                 command_print(cmd_ctx, "further analysis failed (corrupted trace data or just end of data");
2015                                 break;
2016                         case ERROR_TRACE_INSTRUCTION_UNAVAILABLE:
2017                                 command_print(cmd_ctx, "no instruction for current address available, analysis aborted");
2018                                 break;
2019                         case ERROR_TRACE_IMAGE_UNAVAILABLE:
2020                                 command_print(cmd_ctx, "no image available for trace analysis");
2021                                 break;
2022                         default:
2023                                 command_print(cmd_ctx, "unknown error: %i", retval);
2024                 }
2025         }
2026
2027         return ERROR_OK;
2028 }
2029
2030 int etm_register_commands(struct command_context_s *cmd_ctx)
2031 {
2032         etm_cmd = register_command(cmd_ctx, NULL, "etm", NULL, COMMAND_ANY, "Embedded Trace Macrocell");
2033
2034         register_command(cmd_ctx, etm_cmd, "config", handle_etm_config_command,
2035                 COMMAND_CONFIG, "etm config <target> <port_width> <port_mode> <clocking> <capture_driver>");
2036
2037         return ERROR_OK;
2038 }
2039
2040 static int etm_register_user_commands(struct command_context_s *cmd_ctx)
2041 {
2042         register_command(cmd_ctx, etm_cmd, "tracemode", handle_etm_tracemode_command,
2043                 COMMAND_EXEC, "configure/display trace mode: "
2044                         "<none | data | address | all> "
2045                         "<context_id_bits> <cycle_accurate> <branch_output>");
2046
2047         register_command(cmd_ctx, etm_cmd, "info", handle_etm_info_command,
2048                 COMMAND_EXEC, "display info about the current target's ETM");
2049
2050         register_command(cmd_ctx, etm_cmd, "trigger_percent", handle_etm_trigger_percent_command,
2051                 COMMAND_EXEC, "amount (<percent>) of trace buffer to be filled after the trigger occured");
2052         register_command(cmd_ctx, etm_cmd, "status", handle_etm_status_command,
2053                 COMMAND_EXEC, "display current target's ETM status");
2054         register_command(cmd_ctx, etm_cmd, "start", handle_etm_start_command,
2055                 COMMAND_EXEC, "start ETM trace collection");
2056         register_command(cmd_ctx, etm_cmd, "stop", handle_etm_stop_command,
2057                 COMMAND_EXEC, "stop ETM trace collection");
2058
2059         register_command(cmd_ctx, etm_cmd, "analyze", handle_etm_analyze_command,
2060                 COMMAND_EXEC, "anaylze collected ETM trace");
2061
2062         register_command(cmd_ctx, etm_cmd, "image", handle_etm_image_command,
2063                 COMMAND_EXEC, "load image from <file> [base address]");
2064
2065         register_command(cmd_ctx, etm_cmd, "dump", handle_etm_dump_command,
2066                 COMMAND_EXEC, "dump captured trace data <file>");
2067         register_command(cmd_ctx, etm_cmd, "load", handle_etm_load_command,
2068                 COMMAND_EXEC, "load trace data for analysis <file>");
2069
2070         return ERROR_OK;
2071 }