1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
28 #include "arm_disassembler.h"
33 * ARM "Embedded Trace Macrocell" (ETM) support -- direct JTAG access.
35 * ETM modules collect instruction and/or data trace information, compress
36 * it, and transfer it to a debugging host through either a (buffered) trace
37 * port (often a 38-pin Mictor connector) or an Embedded Trace Buffer (ETB).
39 * There are several generations of these modules. Original versions have
40 * JTAG access through a dedicated scan chain. Recent versions have added
41 * access via coprocessor instructions, memory addressing, and the ARM Debug
42 * Interface v5 (ADIv5); and phased out direct JTAG access.
44 * This code supports up to the ETMv1.3 architecture, as seen in ETM9 and
45 * most common ARM9 systems. Note: "CoreSight ETM9" implements ETMv3.2,
46 * implying non-JTAG connectivity options.
48 * Relevant documentation includes:
49 * ARM DDI 0157G ... ETM9 (r2p2) Technical Reference Manual
50 * ARM DDI 0315B ... CoreSight ETM9 (r0p1) Technical Reference Manual
51 * ARM IHI 0014O ... Embedded Trace Macrocell, Architecture Specification
62 uint8_t size; /* low-N of 32 bits */
63 uint8_t mode; /* RO, WO, RW */
64 uint8_t bcd_vers; /* 1.0, 2.0, etc */
69 * Registers 0..0x7f are JTAG-addressable using scanchain 6.
70 * (Or on some processors, through coprocessor operations.)
71 * Newer versions of ETM make some W/O registers R/W, and
72 * provide definitions for some previously-unused bits.
75 /* core registers used to version/configure the ETM */
76 static const struct etm_reg_info etm_core[] = {
77 /* NOTE: we "know" the order here ... */
78 { ETM_CONFIG, 32, RO, 0x10, "ETM_config", },
79 { ETM_ID, 32, RO, 0x20, "ETM_id", },
82 /* basic registers that are always there given the right ETM version */
83 static const struct etm_reg_info etm_basic[] = {
84 /* ETM Trace Registers */
85 { ETM_CTRL, 32, RW, 0x10, "ETM_ctrl", },
86 { ETM_TRIG_EVENT, 17, WO, 0x10, "ETM_trig_event", },
87 { ETM_ASIC_CTRL, 8, WO, 0x10, "ETM_asic_ctrl", },
88 { ETM_STATUS, 3, RO, 0x11, "ETM_status", },
89 { ETM_SYS_CONFIG, 9, RO, 0x12, "ETM_sys_config", },
91 /* TraceEnable configuration */
92 { ETM_TRACE_RESOURCE_CTRL, 32, WO, 0x12, "ETM_trace_resource_ctrl", },
93 { ETM_TRACE_EN_CTRL2, 16, WO, 0x12, "ETM_trace_en_ctrl2", },
94 { ETM_TRACE_EN_EVENT, 17, WO, 0x10, "ETM_trace_en_event", },
95 { ETM_TRACE_EN_CTRL1, 26, WO, 0x10, "ETM_trace_en_ctrl1", },
97 /* ViewData configuration (data trace) */
98 { ETM_VIEWDATA_EVENT, 17, WO, 0x10, "ETM_viewdata_event", },
99 { ETM_VIEWDATA_CTRL1, 32, WO, 0x10, "ETM_viewdata_ctrl1", },
100 { ETM_VIEWDATA_CTRL2, 32, WO, 0x10, "ETM_viewdata_ctrl2", },
101 { ETM_VIEWDATA_CTRL3, 17, WO, 0x10, "ETM_viewdata_ctrl3", },
103 /* REVISIT exclude VIEWDATA_CTRL2 when it's not there */
105 { 0x78, 12, WO, 0x20, "ETM_sync_freq", },
106 { 0x7a, 22, RO, 0x31, "ETM_config_code_ext", },
107 { 0x7b, 32, WO, 0x31, "ETM_ext_input_select", },
108 { 0x7c, 32, WO, 0x34, "ETM_trace_start_stop", },
109 { 0x7d, 8, WO, 0x34, "ETM_behavior_control", },
112 static const struct etm_reg_info etm_fifofull[] = {
113 /* FIFOFULL configuration */
114 { ETM_FIFOFULL_REGION, 25, WO, 0x10, "ETM_fifofull_region", },
115 { ETM_FIFOFULL_LEVEL, 8, WO, 0x10, "ETM_fifofull_level", },
118 static const struct etm_reg_info etm_addr_comp[] = {
119 /* Address comparator register pairs */
120 #define ADDR_COMPARATOR(i) \
121 { ETM_ADDR_COMPARATOR_VALUE + (i) - 1, 32, WO, 0x10, \
122 "ETM_addr_" #i "_comparator_value", }, \
123 { ETM_ADDR_ACCESS_TYPE + (i) - 1, 7, WO, 0x10, \
124 "ETM_addr_" #i "_access_type", }
142 #undef ADDR_COMPARATOR
145 static const struct etm_reg_info etm_data_comp[] = {
146 /* Data Value Comparators (NOTE: odd addresses are reserved) */
147 #define DATA_COMPARATOR(i) \
148 { ETM_DATA_COMPARATOR_VALUE + 2*(i) - 1, 32, WO, 0x10, \
149 "ETM_data_" #i "_comparator_value", }, \
150 { ETM_DATA_COMPARATOR_MASK + 2*(i) - 1, 32, WO, 0x10, \
151 "ETM_data_" #i "_comparator_mask", }
160 #undef DATA_COMPARATOR
163 static const struct etm_reg_info etm_counters[] = {
164 #define ETM_COUNTER(i) \
165 { ETM_COUNTER_RELOAD_VALUE + (i) - 1, 16, WO, 0x10, \
166 "ETM_counter_" #i "_reload_value", }, \
167 { ETM_COUNTER_ENABLE + (i) - 1, 18, WO, 0x10, \
168 "ETM_counter_" #i "_enable", }, \
169 { ETM_COUNTER_RELOAD_EVENT + (i) - 1, 17, WO, 0x10, \
170 "ETM_counter_" #i "_reload_event", }, \
171 { ETM_COUNTER_VALUE + (i) - 1, 16, RO, 0x10, \
172 "ETM_counter_" #i "_value", }
180 static const struct etm_reg_info etm_sequencer[] = {
182 { ETM_SEQUENCER_EVENT + (i), 17, WO, 0x10, \
183 "ETM_sequencer_event" #i, }
184 ETM_SEQ(0), /* 1->2 */
185 ETM_SEQ(1), /* 2->1 */
186 ETM_SEQ(2), /* 2->3 */
187 ETM_SEQ(3), /* 3->1 */
188 ETM_SEQ(4), /* 3->2 */
189 ETM_SEQ(5), /* 1->3 */
192 { ETM_SEQUENCER_STATE, 2, RO, 0x10, "ETM_sequencer_state", },
195 static const struct etm_reg_info etm_outputs[] = {
196 #define ETM_OUTPUT(i) \
197 { ETM_EXTERNAL_OUTPUT + (i) - 1, 17, WO, 0x10, \
198 "ETM_external_output" #i, }
208 /* registers from 0x6c..0x7f were added after ETMv1.3 */
210 /* Context ID Comparators */
211 { 0x6c, 32, RO, 0x20, "ETM_contextid_comparator_value1", }
212 { 0x6d, 32, RO, 0x20, "ETM_contextid_comparator_value2", }
213 { 0x6e, 32, RO, 0x20, "ETM_contextid_comparator_value3", }
214 { 0x6f, 32, RO, 0x20, "ETM_contextid_comparator_mask", }
217 static int etm_get_reg(struct reg *reg);
218 static int etm_read_reg_w_check(struct reg *reg,
219 uint8_t* check_value, uint8_t* check_mask);
220 static int etm_register_user_commands(struct command_context *cmd_ctx);
221 static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf);
222 static int etm_write_reg(struct reg *reg, uint32_t value);
224 static struct command *etm_cmd;
226 static const struct reg_arch_type etm_scan6_type = {
228 .set = etm_set_reg_w_exec,
231 /* Look up register by ID ... most ETM instances only
232 * support a subset of the possible registers.
234 static struct reg *etm_reg_lookup(struct etm_context *etm_ctx, unsigned id)
236 struct reg_cache *cache = etm_ctx->reg_cache;
239 for (i = 0; i < cache->num_regs; i++) {
240 struct etm_reg *reg = cache->reg_list[i].arch_info;
242 if (reg->reg_info->addr == id)
243 return &cache->reg_list[i];
246 /* caller asking for nonexistent register is a bug! */
247 /* REVISIT say which of the N targets was involved */
248 LOG_ERROR("ETM: register 0x%02x not available", id);
252 static void etm_reg_add(unsigned bcd_vers, struct arm_jtag *jtag_info,
253 struct reg_cache *cache, struct etm_reg *ereg,
254 const struct etm_reg_info *r, unsigned nreg)
256 struct reg *reg = cache->reg_list;
258 reg += cache->num_regs;
259 ereg += cache->num_regs;
261 /* add up to "nreg" registers from "r", if supported by this
262 * version of the ETM, to the specified cache.
264 for (; nreg--; r++) {
266 /* this ETM may be too old to have some registers */
267 if (r->bcd_vers > bcd_vers)
272 reg->value = &ereg->value;
273 reg->arch_info = ereg;
274 reg->type = &etm_scan6_type;
279 ereg->jtag_info = jtag_info;
284 struct reg_cache *etm_build_reg_cache(struct target *target,
285 struct arm_jtag *jtag_info, struct etm_context *etm_ctx)
287 struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
288 struct reg *reg_list = NULL;
289 struct etm_reg *arch_info = NULL;
290 unsigned bcd_vers, config;
292 /* the actual registers are kept in two arrays */
293 reg_list = calloc(128, sizeof(struct reg));
294 arch_info = calloc(128, sizeof(struct etm_reg));
296 /* fill in values for the reg cache */
297 reg_cache->name = "etm registers";
298 reg_cache->next = NULL;
299 reg_cache->reg_list = reg_list;
300 reg_cache->num_regs = 0;
302 /* add ETM_CONFIG, then parse its values to see
303 * which other registers exist in this ETM
305 etm_reg_add(0x10, jtag_info, reg_cache, arch_info,
308 etm_get_reg(reg_list);
309 etm_ctx->config = buf_get_u32((void *)&arch_info->value, 0, 32);
310 config = etm_ctx->config;
312 /* figure ETM version then add base registers */
313 if (config & (1 << 31)) {
315 LOG_WARNING("ETMv2+ support is incomplete");
317 /* REVISIT more registers may exist; they may now be
318 * readable; more register bits have defined meanings;
319 * don't presume trace start/stop support is present;
320 * and include any context ID comparator registers.
322 etm_reg_add(0x20, jtag_info, reg_cache, arch_info,
324 etm_get_reg(reg_list + 1);
325 etm_ctx->id = buf_get_u32(
326 (void *)&arch_info[1].value, 0, 32);
327 LOG_DEBUG("ETM ID: %08x", (unsigned) etm_ctx->id);
328 bcd_vers = 0x10 + (((etm_ctx->id) >> 4) & 0xff);
331 switch (config >> 28) {
348 LOG_WARNING("Bad ETMv1 protocol %d", config >> 28);
352 etm_ctx->bcd_vers = bcd_vers;
353 LOG_INFO("ETM v%d.%d", bcd_vers >> 4, bcd_vers & 0xf);
355 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
356 etm_basic, ARRAY_SIZE(etm_basic));
358 /* address and data comparators; counters; outputs */
359 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
360 etm_addr_comp, 4 * (0x0f & (config >> 0)));
361 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
362 etm_data_comp, 2 * (0x0f & (config >> 4)));
363 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
364 etm_counters, 4 * (0x07 & (config >> 13)));
365 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
366 etm_outputs, (0x07 & (config >> 20)));
368 /* FIFOFULL presence is optional
369 * REVISIT for ETMv1.2 and later, don't bother adding this
370 * unless ETM_SYS_CONFIG says it's also *supported* ...
372 if (config & (1 << 23))
373 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
374 etm_fifofull, ARRAY_SIZE(etm_fifofull));
376 /* sequencer is optional (for state-dependant triggering) */
377 if (config & (1 << 16))
378 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
379 etm_sequencer, ARRAY_SIZE(etm_sequencer));
381 /* REVISIT could realloc and likely save half the memory
382 * in the two chunks we allocated...
385 /* the ETM might have an ETB connected */
386 if (strcmp(etm_ctx->capture_driver->name, "etb") == 0)
388 struct etb *etb = etm_ctx->capture_driver_priv;
392 LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
396 reg_cache->next = etb_build_reg_cache(etb);
398 etb->reg_cache = reg_cache->next;
401 etm_ctx->reg_cache = reg_cache;
411 static int etm_read_reg(struct reg *reg)
413 return etm_read_reg_w_check(reg, NULL, NULL);
416 static int etm_store_reg(struct reg *reg)
418 return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
421 int etm_setup(struct target *target)
424 uint32_t etm_ctrl_value;
425 struct arm *arm = target_to_arm(target);
426 struct etm_context *etm_ctx = arm->etm;
427 struct reg *etm_ctrl_reg;
429 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
433 /* initialize some ETM control register settings */
434 etm_get_reg(etm_ctrl_reg);
435 etm_ctrl_value = buf_get_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size);
437 /* clear the ETM powerdown bit (0) */
438 etm_ctrl_value &= ~0x1;
440 /* configure port width (21,6:4), mode (13,17:16) and
441 * for older modules clocking (13)
443 etm_ctrl_value = (etm_ctrl_value
444 & ~ETM_PORT_WIDTH_MASK
445 & ~ETM_PORT_MODE_MASK
446 & ~ETM_PORT_CLOCK_MASK)
449 buf_set_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size, etm_ctrl_value);
450 etm_store_reg(etm_ctrl_reg);
452 if ((retval = jtag_execute_queue()) != ERROR_OK)
455 /* REVISIT for ETMv3.0 and later, read ETM_sys_config to
456 * verify that those width and mode settings are OK ...
459 if ((retval = etm_ctx->capture_driver->init(etm_ctx)) != ERROR_OK)
461 LOG_ERROR("ETM capture driver initialization failed");
467 static int etm_get_reg(struct reg *reg)
471 if ((retval = etm_read_reg(reg)) != ERROR_OK)
473 LOG_ERROR("BUG: error scheduling etm register read");
477 if ((retval = jtag_execute_queue()) != ERROR_OK)
479 LOG_ERROR("register read failed");
486 static int etm_read_reg_w_check(struct reg *reg,
487 uint8_t* check_value, uint8_t* check_mask)
489 struct etm_reg *etm_reg = reg->arch_info;
490 const struct etm_reg_info *r = etm_reg->reg_info;
491 uint8_t reg_addr = r->addr & 0x7f;
492 struct scan_field fields[3];
494 if (etm_reg->reg_info->mode == WO) {
495 LOG_ERROR("BUG: can't read write-only register %s", r->name);
496 return ERROR_INVALID_ARGUMENTS;
499 LOG_DEBUG("%s (%u)", r->name, reg_addr);
501 jtag_set_end_state(TAP_IDLE);
502 arm_jtag_scann(etm_reg->jtag_info, 0x6);
503 arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
505 fields[0].tap = etm_reg->jtag_info->tap;
506 fields[0].num_bits = 32;
507 fields[0].out_value = reg->value;
508 fields[0].in_value = NULL;
509 fields[0].check_value = NULL;
510 fields[0].check_mask = NULL;
512 fields[1].tap = etm_reg->jtag_info->tap;
513 fields[1].num_bits = 7;
514 fields[1].out_value = malloc(1);
515 buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
516 fields[1].in_value = NULL;
517 fields[1].check_value = NULL;
518 fields[1].check_mask = NULL;
520 fields[2].tap = etm_reg->jtag_info->tap;
521 fields[2].num_bits = 1;
522 fields[2].out_value = malloc(1);
523 buf_set_u32(fields[2].out_value, 0, 1, 0);
524 fields[2].in_value = NULL;
525 fields[2].check_value = NULL;
526 fields[2].check_mask = NULL;
528 jtag_add_dr_scan(3, fields, jtag_get_end_state());
530 fields[0].in_value = reg->value;
531 fields[0].check_value = check_value;
532 fields[0].check_mask = check_mask;
534 jtag_add_dr_scan_check(3, fields, jtag_get_end_state());
536 free(fields[1].out_value);
537 free(fields[2].out_value);
542 static int etm_set_reg(struct reg *reg, uint32_t value)
546 if ((retval = etm_write_reg(reg, value)) != ERROR_OK)
548 LOG_ERROR("BUG: error scheduling etm register write");
552 buf_set_u32(reg->value, 0, reg->size, value);
559 static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf)
563 etm_set_reg(reg, buf_get_u32(buf, 0, reg->size));
565 if ((retval = jtag_execute_queue()) != ERROR_OK)
567 LOG_ERROR("register write failed");
573 static int etm_write_reg(struct reg *reg, uint32_t value)
575 struct etm_reg *etm_reg = reg->arch_info;
576 const struct etm_reg_info *r = etm_reg->reg_info;
577 uint8_t reg_addr = r->addr & 0x7f;
578 struct scan_field fields[3];
580 if (etm_reg->reg_info->mode == RO) {
581 LOG_ERROR("BUG: can't write read--only register %s", r->name);
582 return ERROR_INVALID_ARGUMENTS;
585 LOG_DEBUG("%s (%u): 0x%8.8" PRIx32 "", r->name, reg_addr, value);
587 jtag_set_end_state(TAP_IDLE);
588 arm_jtag_scann(etm_reg->jtag_info, 0x6);
589 arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
591 fields[0].tap = etm_reg->jtag_info->tap;
592 fields[0].num_bits = 32;
594 fields[0].out_value = tmp1;
595 buf_set_u32(fields[0].out_value, 0, 32, value);
596 fields[0].in_value = NULL;
598 fields[1].tap = etm_reg->jtag_info->tap;
599 fields[1].num_bits = 7;
601 fields[1].out_value = &tmp2;
602 buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
603 fields[1].in_value = NULL;
605 fields[2].tap = etm_reg->jtag_info->tap;
606 fields[2].num_bits = 1;
608 fields[2].out_value = &tmp3;
609 buf_set_u32(fields[2].out_value, 0, 1, 1);
610 fields[2].in_value = NULL;
612 jtag_add_dr_scan(3, fields, jtag_get_end_state());
618 /* ETM trace analysis functionality
621 extern struct etm_capture_driver etm_dummy_capture_driver;
622 #if BUILD_OOCD_TRACE == 1
623 extern struct etm_capture_driver oocd_trace_capture_driver;
626 static struct etm_capture_driver *etm_capture_drivers[] =
629 &etm_dummy_capture_driver,
630 #if BUILD_OOCD_TRACE == 1
631 &oocd_trace_capture_driver,
636 static int etm_read_instruction(struct etm_context *ctx, struct arm_instruction *instruction)
645 return ERROR_TRACE_IMAGE_UNAVAILABLE;
647 /* search for the section the current instruction belongs to */
648 for (i = 0; i < ctx->image->num_sections; i++)
650 if ((ctx->image->sections[i].base_address <= ctx->current_pc) &&
651 (ctx->image->sections[i].base_address + ctx->image->sections[i].size > ctx->current_pc))
660 /* current instruction couldn't be found in the image */
661 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
664 if (ctx->core_state == ARMV4_5_STATE_ARM)
667 if ((retval = image_read_section(ctx->image, section,
668 ctx->current_pc - ctx->image->sections[section].base_address,
669 4, buf, &size_read)) != ERROR_OK)
671 LOG_ERROR("error while reading instruction: %i", retval);
672 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
674 opcode = target_buffer_get_u32(ctx->target, buf);
675 arm_evaluate_opcode(opcode, ctx->current_pc, instruction);
677 else if (ctx->core_state == ARMV4_5_STATE_THUMB)
680 if ((retval = image_read_section(ctx->image, section,
681 ctx->current_pc - ctx->image->sections[section].base_address,
682 2, buf, &size_read)) != ERROR_OK)
684 LOG_ERROR("error while reading instruction: %i", retval);
685 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
687 opcode = target_buffer_get_u16(ctx->target, buf);
688 thumb_evaluate_opcode(opcode, ctx->current_pc, instruction);
690 else if (ctx->core_state == ARMV4_5_STATE_JAZELLE)
692 LOG_ERROR("BUG: tracing of jazelle code not supported");
697 LOG_ERROR("BUG: unknown core state encountered");
704 static int etmv1_next_packet(struct etm_context *ctx, uint8_t *packet, int apo)
706 while (ctx->data_index < ctx->trace_depth)
708 /* if the caller specified an address packet offset, skip until the
709 * we reach the n-th cycle marked with tracesync */
712 if (ctx->trace_data[ctx->data_index].flags & ETMV1_TRACESYNC_CYCLE)
723 /* no tracedata output during a TD cycle
724 * or in a trigger cycle */
725 if ((ctx->trace_data[ctx->data_index].pipestat == STAT_TD)
726 || (ctx->trace_data[ctx->data_index].flags & ETMV1_TRIGGER_CYCLE))
733 if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_16BIT)
735 if (ctx->data_half == 0)
737 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
742 *packet = (ctx->trace_data[ctx->data_index].packet & 0xff00) >> 8;
747 else if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
749 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
754 /* on a 4-bit port, a packet will be output during two consecutive cycles */
755 if (ctx->data_index > (ctx->trace_depth - 2))
758 *packet = ctx->trace_data[ctx->data_index].packet & 0xf;
759 *packet |= (ctx->trace_data[ctx->data_index + 1].packet & 0xf) << 4;
760 ctx->data_index += 2;
769 static int etmv1_branch_address(struct etm_context *ctx)
777 /* quit analysis if less than two cycles are left in the trace
778 * because we can't extract the APO */
779 if (ctx->data_index > (ctx->trace_depth - 2))
782 /* a BE could be output during an APO cycle, skip the current
783 * and continue with the new one */
784 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x4)
786 if (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x4)
789 /* address packet offset encoded in the next two cycles' pipestat bits */
790 apo = ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x3;
791 apo |= (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x3) << 2;
793 /* count number of tracesync cycles between current pipe_index and data_index
794 * i.e. the number of tracesyncs that data_index already passed by
795 * to subtract them from the APO */
796 for (i = ctx->pipe_index; i < ctx->data_index; i++)
798 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & ETMV1_TRACESYNC_CYCLE)
802 /* extract up to four 7-bit packets */
804 if ((retval = etmv1_next_packet(ctx, &packet, (shift == 0) ? apo + 1 : 0)) != 0)
806 ctx->last_branch &= ~(0x7f << shift);
807 ctx->last_branch |= (packet & 0x7f) << shift;
809 } while ((packet & 0x80) && (shift < 28));
811 /* one last packet holding 4 bits of the address, plus the branch reason code */
812 if ((shift == 28) && (packet & 0x80))
814 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
816 ctx->last_branch &= 0x0fffffff;
817 ctx->last_branch |= (packet & 0x0f) << 28;
818 ctx->last_branch_reason = (packet & 0x70) >> 4;
823 ctx->last_branch_reason = 0;
831 /* if a full address was output, we might have branched into Jazelle state */
832 if ((shift == 32) && (packet & 0x80))
834 ctx->core_state = ARMV4_5_STATE_JAZELLE;
838 /* if we didn't branch into Jazelle state, the current processor state is
839 * encoded in bit 0 of the branch target address */
840 if (ctx->last_branch & 0x1)
842 ctx->core_state = ARMV4_5_STATE_THUMB;
843 ctx->last_branch &= ~0x1;
847 ctx->core_state = ARMV4_5_STATE_ARM;
848 ctx->last_branch &= ~0x3;
855 static int etmv1_data(struct etm_context *ctx, int size, uint32_t *data)
861 for (j = 0; j < size; j++)
863 if ((retval = etmv1_next_packet(ctx, &buf[j], 0)) != 0)
869 LOG_ERROR("TODO: add support for 64-bit values");
873 *data = target_buffer_get_u32(ctx->target, buf);
875 *data = target_buffer_get_u16(ctx->target, buf);
884 static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context *cmd_ctx)
887 struct arm_instruction instruction;
889 /* read the trace data if it wasn't read already */
890 if (ctx->trace_depth == 0)
891 ctx->capture_driver->read_trace(ctx);
893 /* start at the beginning of the captured trace */
898 /* neither the PC nor the data pointer are valid */
902 while (ctx->pipe_index < ctx->trace_depth)
904 uint8_t pipestat = ctx->trace_data[ctx->pipe_index].pipestat;
905 uint32_t next_pc = ctx->current_pc;
906 uint32_t old_data_index = ctx->data_index;
907 uint32_t old_data_half = ctx->data_half;
908 uint32_t old_index = ctx->pipe_index;
909 uint32_t last_instruction = ctx->last_instruction;
911 int current_pc_ok = ctx->pc_ok;
913 if (ctx->trace_data[ctx->pipe_index].flags & ETMV1_TRIGGER_CYCLE)
915 command_print(cmd_ctx, "--- trigger ---");
918 /* instructions execute in IE/D or BE/D cycles */
919 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
920 ctx->last_instruction = ctx->pipe_index;
922 /* if we don't have a valid pc skip until we reach an indirect branch */
923 if ((!ctx->pc_ok) && (pipestat != STAT_BE))
929 /* any indirect branch could have interrupted instruction flow
930 * - the branch reason code could indicate a trace discontinuity
931 * - a branch to the exception vectors indicates an exception
933 if ((pipestat == STAT_BE) || (pipestat == STAT_BD))
935 /* backup current data index, to be able to consume the branch address
936 * before examining data address and values
938 old_data_index = ctx->data_index;
939 old_data_half = ctx->data_half;
941 ctx->last_instruction = ctx->pipe_index;
943 if ((retval = etmv1_branch_address(ctx)) != 0)
945 /* negative return value from etmv1_branch_address means we ran out of packets,
946 * quit analysing the trace */
950 /* a positive return values means the current branch was abandoned,
951 * and a new branch was encountered in cycle ctx->pipe_index + retval;
953 LOG_WARNING("abandoned branch encountered, correctnes of analysis uncertain");
954 ctx->pipe_index += retval;
958 /* skip over APO cycles */
959 ctx->pipe_index += 2;
961 switch (ctx->last_branch_reason)
963 case 0x0: /* normal PC change */
964 next_pc = ctx->last_branch;
966 case 0x1: /* tracing enabled */
967 command_print(cmd_ctx, "--- tracing enabled at 0x%8.8" PRIx32 " ---", ctx->last_branch);
968 ctx->current_pc = ctx->last_branch;
972 case 0x2: /* trace restarted after FIFO overflow */
973 command_print(cmd_ctx, "--- trace restarted after FIFO overflow at 0x%8.8" PRIx32 " ---", ctx->last_branch);
974 ctx->current_pc = ctx->last_branch;
978 case 0x3: /* exit from debug state */
979 command_print(cmd_ctx, "--- exit from debug state at 0x%8.8" PRIx32 " ---", ctx->last_branch);
980 ctx->current_pc = ctx->last_branch;
984 case 0x4: /* periodic synchronization point */
985 next_pc = ctx->last_branch;
986 /* if we had no valid PC prior to this synchronization point,
987 * we have to move on with the next trace cycle
991 command_print(cmd_ctx, "--- periodic synchronization point at 0x%8.8" PRIx32 " ---", next_pc);
992 ctx->current_pc = next_pc;
997 default: /* reserved */
998 LOG_ERROR("BUG: branch reason code 0x%" PRIx32 " is reserved", ctx->last_branch_reason);
1002 /* if we got here the branch was a normal PC change
1003 * (or a periodic synchronization point, which means the same for that matter)
1004 * if we didn't accquire a complete PC continue with the next cycle
1009 /* indirect branch to the exception vector means an exception occured */
1010 if ((ctx->last_branch <= 0x20)
1011 || ((ctx->last_branch >= 0xffff0000) && (ctx->last_branch <= 0xffff0020)))
1013 if ((ctx->last_branch & 0xff) == 0x10)
1015 command_print(cmd_ctx, "data abort");
1019 command_print(cmd_ctx, "exception vector 0x%2.2" PRIx32 "", ctx->last_branch);
1020 ctx->current_pc = ctx->last_branch;
1027 /* an instruction was executed (or not, depending on the condition flags)
1028 * retrieve it from the image for displaying */
1029 if (ctx->pc_ok && (pipestat != STAT_WT) && (pipestat != STAT_TD) &&
1030 !(((pipestat == STAT_BE) || (pipestat == STAT_BD)) &&
1031 ((ctx->last_branch_reason != 0x0) && (ctx->last_branch_reason != 0x4))))
1033 if ((retval = etm_read_instruction(ctx, &instruction)) != ERROR_OK)
1035 /* can't continue tracing with no image available */
1036 if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
1040 else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE)
1042 /* TODO: handle incomplete images
1043 * for now we just quit the analsysis*/
1048 cycles = old_index - last_instruction;
1051 if ((pipestat == STAT_ID) || (pipestat == STAT_BD))
1053 uint32_t new_data_index = ctx->data_index;
1054 uint32_t new_data_half = ctx->data_half;
1056 /* in case of a branch with data, the branch target address was consumed before
1057 * we temporarily go back to the saved data index */
1058 if (pipestat == STAT_BD)
1060 ctx->data_index = old_data_index;
1061 ctx->data_half = old_data_half;
1064 if (ctx->tracemode & ETMV1_TRACE_ADDR)
1070 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
1071 return ERROR_ETM_ANALYSIS_FAILED;
1072 ctx->last_ptr &= ~(0x7f << shift);
1073 ctx->last_ptr |= (packet & 0x7f) << shift;
1075 } while ((packet & 0x80) && (shift < 32));
1082 command_print(cmd_ctx, "address: 0x%8.8" PRIx32 "", ctx->last_ptr);
1086 if (ctx->tracemode & ETMV1_TRACE_DATA)
1088 if ((instruction.type == ARM_LDM) || (instruction.type == ARM_STM))
1091 for (i = 0; i < 16; i++)
1093 if (instruction.info.load_store_multiple.register_list & (1 << i))
1096 if (etmv1_data(ctx, 4, &data) != 0)
1097 return ERROR_ETM_ANALYSIS_FAILED;
1098 command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
1102 else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_STRH))
1105 if (etmv1_data(ctx, arm_access_size(&instruction), &data) != 0)
1106 return ERROR_ETM_ANALYSIS_FAILED;
1107 command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
1111 /* restore data index after consuming BD address and data */
1112 if (pipestat == STAT_BD)
1114 ctx->data_index = new_data_index;
1115 ctx->data_half = new_data_half;
1120 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
1122 if (((instruction.type == ARM_B) ||
1123 (instruction.type == ARM_BL) ||
1124 (instruction.type == ARM_BLX)) &&
1125 (instruction.info.b_bl_bx_blx.target_address != 0xffffffff))
1127 next_pc = instruction.info.b_bl_bx_blx.target_address;
1131 next_pc += (ctx->core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
1134 else if (pipestat == STAT_IN)
1136 next_pc += (ctx->core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
1139 if ((pipestat != STAT_TD) && (pipestat != STAT_WT))
1141 char cycles_text[32] = "";
1143 /* if the trace was captured with cycle accurate tracing enabled,
1144 * output the number of cycles since the last executed instruction
1146 if (ctx->tracemode & ETMV1_CYCLE_ACCURATE)
1148 snprintf(cycles_text, 32, " (%i %s)",
1150 (cycles == 1) ? "cycle" : "cycles");
1153 command_print(cmd_ctx, "%s%s%s",
1155 (pipestat == STAT_IN) ? " (not executed)" : "",
1158 ctx->current_pc = next_pc;
1160 /* packets for an instruction don't start on or before the preceding
1161 * functional pipestat (i.e. other than WT or TD)
1163 if (ctx->data_index <= ctx->pipe_index)
1165 ctx->data_index = ctx->pipe_index + 1;
1170 ctx->pipe_index += 1;
1176 static COMMAND_HELPER(handle_etm_tracemode_command_update,
1177 etmv1_tracemode_t *mode)
1179 etmv1_tracemode_t tracemode;
1181 /* what parts of data access are traced? */
1182 if (strcmp(CMD_ARGV[0], "none") == 0)
1183 tracemode = ETMV1_TRACE_NONE;
1184 else if (strcmp(CMD_ARGV[0], "data") == 0)
1185 tracemode = ETMV1_TRACE_DATA;
1186 else if (strcmp(CMD_ARGV[0], "address") == 0)
1187 tracemode = ETMV1_TRACE_ADDR;
1188 else if (strcmp(CMD_ARGV[0], "all") == 0)
1189 tracemode = ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR;
1192 command_print(CMD_CTX, "invalid option '%s'", CMD_ARGV[0]);
1193 return ERROR_INVALID_ARGUMENTS;
1197 COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], context_id);
1201 tracemode |= ETMV1_CONTEXTID_NONE;
1204 tracemode |= ETMV1_CONTEXTID_8;
1207 tracemode |= ETMV1_CONTEXTID_16;
1210 tracemode |= ETMV1_CONTEXTID_32;
1213 command_print(CMD_CTX, "invalid option '%s'", CMD_ARGV[1]);
1214 return ERROR_INVALID_ARGUMENTS;
1217 bool etmv1_cycle_accurate;
1218 COMMAND_PARSE_ENABLE(CMD_ARGV[2], etmv1_cycle_accurate);
1219 if (etmv1_cycle_accurate)
1220 tracemode |= ETMV1_CYCLE_ACCURATE;
1222 bool etmv1_branch_output;
1223 COMMAND_PARSE_ENABLE(CMD_ARGV[3], etmv1_branch_output);
1224 tracemode |= ETMV1_BRANCH_OUTPUT;
1227 * - CPRT tracing (coprocessor register transfers)
1228 * - debug request (causes debug entry on trigger)
1229 * - stall on FIFOFULL (preventing tracedata lossage)
1236 COMMAND_HANDLER(handle_etm_tracemode_command)
1238 struct target *target = get_current_target(CMD_CTX);
1239 struct arm *arm = target_to_arm(target);
1240 struct etm_context *etm;
1243 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1249 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1253 etmv1_tracemode_t tracemode = etm->tracemode;
1260 CALL_COMMAND_HANDLER(handle_etm_tracemode_command_update, &tracemode);
1263 command_print(CMD_CTX, "usage: configure trace mode "
1264 "<none | data | address | all> "
1265 "<context id bits> <cycle accurate> <branch output>");
1270 * todo: fail if parameters were invalid for this hardware,
1271 * or couldn't be written; display actual hardware state...
1274 command_print(CMD_CTX, "current tracemode configuration:");
1276 switch (tracemode & ETMV1_TRACE_MASK)
1278 case ETMV1_TRACE_NONE:
1279 command_print(CMD_CTX, "data tracing: none");
1281 case ETMV1_TRACE_DATA:
1282 command_print(CMD_CTX, "data tracing: data only");
1284 case ETMV1_TRACE_ADDR:
1285 command_print(CMD_CTX, "data tracing: address only");
1287 case ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR:
1288 command_print(CMD_CTX, "data tracing: address and data");
1292 switch (tracemode & ETMV1_CONTEXTID_MASK)
1294 case ETMV1_CONTEXTID_NONE:
1295 command_print(CMD_CTX, "contextid tracing: none");
1297 case ETMV1_CONTEXTID_8:
1298 command_print(CMD_CTX, "contextid tracing: 8 bit");
1300 case ETMV1_CONTEXTID_16:
1301 command_print(CMD_CTX, "contextid tracing: 16 bit");
1303 case ETMV1_CONTEXTID_32:
1304 command_print(CMD_CTX, "contextid tracing: 32 bit");
1308 if (tracemode & ETMV1_CYCLE_ACCURATE)
1310 command_print(CMD_CTX, "cycle-accurate tracing enabled");
1314 command_print(CMD_CTX, "cycle-accurate tracing disabled");
1317 if (tracemode & ETMV1_BRANCH_OUTPUT)
1319 command_print(CMD_CTX, "full branch address output enabled");
1323 command_print(CMD_CTX, "full branch address output disabled");
1326 /* only update ETM_CTRL register if tracemode changed */
1327 if (etm->tracemode != tracemode)
1329 struct reg *etm_ctrl_reg;
1331 etm_ctrl_reg = etm_reg_lookup(etm, ETM_CTRL);
1335 etm_get_reg(etm_ctrl_reg);
1337 buf_set_u32(etm_ctrl_reg->value, 2, 2, tracemode & ETMV1_TRACE_MASK);
1338 buf_set_u32(etm_ctrl_reg->value, 14, 2, (tracemode & ETMV1_CONTEXTID_MASK) >> 4);
1339 buf_set_u32(etm_ctrl_reg->value, 12, 1, (tracemode & ETMV1_CYCLE_ACCURATE) >> 8);
1340 buf_set_u32(etm_ctrl_reg->value, 8, 1, (tracemode & ETMV1_BRANCH_OUTPUT) >> 9);
1341 etm_store_reg(etm_ctrl_reg);
1343 etm->tracemode = tracemode;
1345 /* invalidate old trace data */
1346 etm->capture_status = TRACE_IDLE;
1347 if (etm->trace_depth > 0)
1349 free(etm->trace_data);
1350 etm->trace_data = NULL;
1352 etm->trace_depth = 0;
1358 COMMAND_HANDLER(handle_etm_config_command)
1360 struct target *target;
1362 etm_portmode_t portmode = 0x0;
1363 struct etm_context *etm_ctx;
1367 return ERROR_COMMAND_SYNTAX_ERROR;
1369 target = get_target(CMD_ARGV[0]);
1372 LOG_ERROR("target '%s' not defined", CMD_ARGV[0]);
1376 arm = target_to_arm(target);
1378 command_print(CMD_CTX, "target '%s' is '%s'; not an ARM",
1379 target->cmd_name, target_get_name(target));
1383 /* FIXME for ETMv3.0 and above -- and we don't yet know what ETM
1384 * version we'll be using!! -- so we can't know how to validate
1385 * params yet. "etm config" should likely be *AFTER* hookup...
1387 * - Many more widths might be supported ... and we can easily
1388 * check whether our setting "took".
1390 * - The "clock" and "mode" bits are interpreted differently.
1391 * See ARM IHI 0014O table 2-17 for the old behavior, and
1392 * table 2-18 for the new. With ETB it's best to specify
1396 COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], port_width);
1399 /* before ETMv3.0 */
1401 portmode |= ETM_PORT_4BIT;
1404 portmode |= ETM_PORT_8BIT;
1407 portmode |= ETM_PORT_16BIT;
1409 /* ETMv3.0 and later*/
1411 portmode |= ETM_PORT_24BIT;
1414 portmode |= ETM_PORT_32BIT;
1417 portmode |= ETM_PORT_48BIT;
1420 portmode |= ETM_PORT_64BIT;
1423 portmode |= ETM_PORT_1BIT;
1426 portmode |= ETM_PORT_2BIT;
1429 command_print(CMD_CTX,
1430 "unsupported ETM port width '%s'", CMD_ARGV[1]);
1434 if (strcmp("normal", CMD_ARGV[2]) == 0)
1436 portmode |= ETM_PORT_NORMAL;
1438 else if (strcmp("multiplexed", CMD_ARGV[2]) == 0)
1440 portmode |= ETM_PORT_MUXED;
1442 else if (strcmp("demultiplexed", CMD_ARGV[2]) == 0)
1444 portmode |= ETM_PORT_DEMUXED;
1448 command_print(CMD_CTX, "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", CMD_ARGV[2]);
1452 if (strcmp("half", CMD_ARGV[3]) == 0)
1454 portmode |= ETM_PORT_HALF_CLOCK;
1456 else if (strcmp("full", CMD_ARGV[3]) == 0)
1458 portmode |= ETM_PORT_FULL_CLOCK;
1462 command_print(CMD_CTX, "unsupported ETM port clocking '%s', must be 'full' or 'half'", CMD_ARGV[3]);
1466 etm_ctx = calloc(1, sizeof(struct etm_context));
1468 LOG_DEBUG("out of memory");
1472 for (i = 0; etm_capture_drivers[i]; i++)
1474 if (strcmp(CMD_ARGV[4], etm_capture_drivers[i]->name) == 0)
1477 if ((retval = etm_capture_drivers[i]->register_commands(CMD_CTX)) != ERROR_OK)
1483 etm_ctx->capture_driver = etm_capture_drivers[i];
1489 if (!etm_capture_drivers[i])
1491 /* no supported capture driver found, don't register an ETM */
1493 LOG_ERROR("trace capture driver '%s' not found", CMD_ARGV[4]);
1497 etm_ctx->target = target;
1498 etm_ctx->trigger_percent = 50;
1499 etm_ctx->trace_data = NULL;
1500 etm_ctx->portmode = portmode;
1501 etm_ctx->core_state = ARMV4_5_STATE_ARM;
1505 return etm_register_user_commands(CMD_CTX);
1508 COMMAND_HANDLER(handle_etm_info_command)
1510 struct target *target;
1512 struct etm_context *etm;
1513 struct reg *etm_sys_config_reg;
1517 target = get_current_target(CMD_CTX);
1518 arm = target_to_arm(target);
1521 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1528 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1532 command_print(CMD_CTX, "ETM v%d.%d",
1533 etm->bcd_vers >> 4, etm->bcd_vers & 0xf);
1534 command_print(CMD_CTX, "pairs of address comparators: %i",
1535 (int) (etm->config >> 0) & 0x0f);
1536 command_print(CMD_CTX, "data comparators: %i",
1537 (int) (etm->config >> 4) & 0x0f);
1538 command_print(CMD_CTX, "memory map decoders: %i",
1539 (int) (etm->config >> 8) & 0x1f);
1540 command_print(CMD_CTX, "number of counters: %i",
1541 (int) (etm->config >> 13) & 0x07);
1542 command_print(CMD_CTX, "sequencer %spresent",
1543 (int) (etm->config & (1 << 16)) ? "" : "not ");
1544 command_print(CMD_CTX, "number of ext. inputs: %i",
1545 (int) (etm->config >> 17) & 0x07);
1546 command_print(CMD_CTX, "number of ext. outputs: %i",
1547 (int) (etm->config >> 20) & 0x07);
1548 command_print(CMD_CTX, "FIFO full %spresent",
1549 (int) (etm->config & (1 << 23)) ? "" : "not ");
1550 if (etm->bcd_vers < 0x20)
1551 command_print(CMD_CTX, "protocol version: %i",
1552 (int) (etm->config >> 28) & 0x07);
1554 command_print(CMD_CTX,
1555 "coprocessor and memory access %ssupported",
1556 (etm->config & (1 << 26)) ? "" : "not ");
1557 command_print(CMD_CTX, "trace start/stop %spresent",
1558 (etm->config & (1 << 26)) ? "" : "not ");
1559 command_print(CMD_CTX, "number of context comparators: %i",
1560 (int) (etm->config >> 24) & 0x03);
1563 /* SYS_CONFIG isn't present before ETMv1.2 */
1564 etm_sys_config_reg = etm_reg_lookup(etm, ETM_SYS_CONFIG);
1565 if (!etm_sys_config_reg)
1568 etm_get_reg(etm_sys_config_reg);
1569 config = buf_get_u32(etm_sys_config_reg->value, 0, 32);
1571 LOG_DEBUG("ETM SYS CONFIG %08x", (unsigned) config);
1573 max_port_size = config & 0x7;
1574 if (etm->bcd_vers >= 0x30)
1575 max_port_size |= (config >> 6) & 0x08;
1576 switch (max_port_size)
1578 /* before ETMv3.0 */
1588 /* ETMv3.0 and later*/
1608 LOG_ERROR("Illegal max_port_size");
1611 command_print(CMD_CTX, "max. port size: %i", max_port_size);
1613 if (etm->bcd_vers < 0x30) {
1614 command_print(CMD_CTX, "half-rate clocking %ssupported",
1615 (config & (1 << 3)) ? "" : "not ");
1616 command_print(CMD_CTX, "full-rate clocking %ssupported",
1617 (config & (1 << 4)) ? "" : "not ");
1618 command_print(CMD_CTX, "normal trace format %ssupported",
1619 (config & (1 << 5)) ? "" : "not ");
1620 command_print(CMD_CTX, "multiplex trace format %ssupported",
1621 (config & (1 << 6)) ? "" : "not ");
1622 command_print(CMD_CTX, "demultiplex trace format %ssupported",
1623 (config & (1 << 7)) ? "" : "not ");
1625 /* REVISIT show which size and format are selected ... */
1626 command_print(CMD_CTX, "current port size %ssupported",
1627 (config & (1 << 10)) ? "" : "not ");
1628 command_print(CMD_CTX, "current trace format %ssupported",
1629 (config & (1 << 11)) ? "" : "not ");
1631 if (etm->bcd_vers >= 0x21)
1632 command_print(CMD_CTX, "fetch comparisons %ssupported",
1633 (config & (1 << 17)) ? "not " : "");
1634 command_print(CMD_CTX, "FIFO full %ssupported",
1635 (config & (1 << 8)) ? "" : "not ");
1640 COMMAND_HANDLER(handle_etm_status_command)
1642 struct target *target;
1644 struct etm_context *etm;
1645 trace_status_t trace_status;
1647 target = get_current_target(CMD_CTX);
1648 arm = target_to_arm(target);
1651 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1658 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1663 if (etm->bcd_vers >= 0x11) {
1666 reg = etm_reg_lookup(etm, ETM_STATUS);
1669 if (etm_get_reg(reg) == ERROR_OK) {
1670 unsigned s = buf_get_u32(reg->value, 0, reg->size);
1672 command_print(CMD_CTX, "etm: %s%s%s%s",
1673 /* bit(1) == progbit */
1674 (etm->bcd_vers >= 0x12)
1676 ? "disabled" : "enabled")
1678 ((s & (1 << 3)) && etm->bcd_vers >= 0x31)
1679 ? " triggered" : "",
1680 ((s & (1 << 2)) && etm->bcd_vers >= 0x12)
1681 ? " start/stop" : "",
1682 ((s & (1 << 0)) && etm->bcd_vers >= 0x11)
1683 ? " untraced-overflow" : "");
1684 } /* else ignore and try showing trace port status */
1687 /* Trace Port Driver status */
1688 trace_status = etm->capture_driver->status(etm);
1689 if (trace_status == TRACE_IDLE)
1691 command_print(CMD_CTX, "%s: idle", etm->capture_driver->name);
1695 static char *completed = " completed";
1696 static char *running = " is running";
1697 static char *overflowed = ", overflowed";
1698 static char *triggered = ", triggered";
1700 command_print(CMD_CTX, "%s: trace collection%s%s%s",
1701 etm->capture_driver->name,
1702 (trace_status & TRACE_RUNNING) ? running : completed,
1703 (trace_status & TRACE_OVERFLOWED) ? overflowed : "",
1704 (trace_status & TRACE_TRIGGERED) ? triggered : "");
1706 if (etm->trace_depth > 0)
1708 command_print(CMD_CTX, "%i frames of trace data read",
1709 (int)(etm->trace_depth));
1716 COMMAND_HANDLER(handle_etm_image_command)
1718 struct target *target;
1720 struct etm_context *etm_ctx;
1724 command_print(CMD_CTX, "usage: etm image <file> [base address] [type]");
1728 target = get_current_target(CMD_CTX);
1729 arm = target_to_arm(target);
1732 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1739 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1745 image_close(etm_ctx->image);
1746 free(etm_ctx->image);
1747 command_print(CMD_CTX, "previously loaded image found and closed");
1750 etm_ctx->image = malloc(sizeof(struct image));
1751 etm_ctx->image->base_address_set = 0;
1752 etm_ctx->image->start_address_set = 0;
1754 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1757 etm_ctx->image->base_address_set = 1;
1758 COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], etm_ctx->image->base_address);
1762 etm_ctx->image->base_address_set = 0;
1765 if (image_open(etm_ctx->image, CMD_ARGV[0], (CMD_ARGC >= 3) ? CMD_ARGV[2] : NULL) != ERROR_OK)
1767 free(etm_ctx->image);
1768 etm_ctx->image = NULL;
1775 COMMAND_HANDLER(handle_etm_dump_command)
1778 struct target *target;
1780 struct etm_context *etm_ctx;
1785 command_print(CMD_CTX, "usage: etm dump <file>");
1789 target = get_current_target(CMD_CTX);
1790 arm = target_to_arm(target);
1793 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1800 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1804 if (etm_ctx->capture_driver->status == TRACE_IDLE)
1806 command_print(CMD_CTX, "trace capture wasn't enabled, no trace data captured");
1810 if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1812 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1813 command_print(CMD_CTX, "trace capture not completed");
1817 /* read the trace data if it wasn't read already */
1818 if (etm_ctx->trace_depth == 0)
1819 etm_ctx->capture_driver->read_trace(etm_ctx);
1821 if (fileio_open(&file, CMD_ARGV[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1826 fileio_write_u32(&file, etm_ctx->capture_status);
1827 fileio_write_u32(&file, etm_ctx->portmode);
1828 fileio_write_u32(&file, etm_ctx->tracemode);
1829 fileio_write_u32(&file, etm_ctx->trace_depth);
1831 for (i = 0; i < etm_ctx->trace_depth; i++)
1833 fileio_write_u32(&file, etm_ctx->trace_data[i].pipestat);
1834 fileio_write_u32(&file, etm_ctx->trace_data[i].packet);
1835 fileio_write_u32(&file, etm_ctx->trace_data[i].flags);
1838 fileio_close(&file);
1843 COMMAND_HANDLER(handle_etm_load_command)
1846 struct target *target;
1848 struct etm_context *etm_ctx;
1853 command_print(CMD_CTX, "usage: etm load <file>");
1857 target = get_current_target(CMD_CTX);
1858 arm = target_to_arm(target);
1861 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1868 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1872 if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1874 command_print(CMD_CTX, "trace capture running, stop first");
1878 if (fileio_open(&file, CMD_ARGV[0], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1885 command_print(CMD_CTX, "size isn't a multiple of 4, no valid trace data");
1886 fileio_close(&file);
1890 if (etm_ctx->trace_depth > 0)
1892 free(etm_ctx->trace_data);
1893 etm_ctx->trace_data = NULL;
1898 fileio_read_u32(&file, &tmp); etm_ctx->capture_status = tmp;
1899 fileio_read_u32(&file, &tmp); etm_ctx->portmode = tmp;
1900 fileio_read_u32(&file, &tmp); etm_ctx->tracemode = tmp;
1901 fileio_read_u32(&file, &etm_ctx->trace_depth);
1903 etm_ctx->trace_data = malloc(sizeof(struct etmv1_trace_data) * etm_ctx->trace_depth);
1904 if (etm_ctx->trace_data == NULL)
1906 command_print(CMD_CTX, "not enough memory to perform operation");
1907 fileio_close(&file);
1911 for (i = 0; i < etm_ctx->trace_depth; i++)
1913 uint32_t pipestat, packet, flags;
1914 fileio_read_u32(&file, &pipestat);
1915 fileio_read_u32(&file, &packet);
1916 fileio_read_u32(&file, &flags);
1917 etm_ctx->trace_data[i].pipestat = pipestat & 0xff;
1918 etm_ctx->trace_data[i].packet = packet & 0xffff;
1919 etm_ctx->trace_data[i].flags = flags;
1922 fileio_close(&file);
1927 COMMAND_HANDLER(handle_etm_trigger_percent_command)
1929 struct target *target;
1931 struct etm_context *etm_ctx;
1933 target = get_current_target(CMD_CTX);
1934 arm = target_to_arm(target);
1937 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1944 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1951 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], new_value);
1953 if ((new_value < 2) || (new_value > 100))
1955 command_print(CMD_CTX, "valid settings are 2%% to 100%%");
1959 etm_ctx->trigger_percent = new_value;
1963 command_print(CMD_CTX, "%i percent of the tracebuffer reserved for after the trigger", ((int)(etm_ctx->trigger_percent)));
1968 COMMAND_HANDLER(handle_etm_start_command)
1970 struct target *target;
1972 struct etm_context *etm_ctx;
1973 struct reg *etm_ctrl_reg;
1975 target = get_current_target(CMD_CTX);
1976 arm = target_to_arm(target);
1979 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1986 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1990 /* invalidate old tracing data */
1991 etm_ctx->capture_status = TRACE_IDLE;
1992 if (etm_ctx->trace_depth > 0)
1994 free(etm_ctx->trace_data);
1995 etm_ctx->trace_data = NULL;
1997 etm_ctx->trace_depth = 0;
1999 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
2003 etm_get_reg(etm_ctrl_reg);
2005 /* Clear programming bit (10), set port selection bit (11) */
2006 buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x2);
2008 etm_store_reg(etm_ctrl_reg);
2009 jtag_execute_queue();
2011 etm_ctx->capture_driver->start_capture(etm_ctx);
2016 COMMAND_HANDLER(handle_etm_stop_command)
2018 struct target *target;
2020 struct etm_context *etm_ctx;
2021 struct reg *etm_ctrl_reg;
2023 target = get_current_target(CMD_CTX);
2024 arm = target_to_arm(target);
2027 command_print(CMD_CTX, "ETM: current target isn't an ARM");
2034 command_print(CMD_CTX, "current target doesn't have an ETM configured");
2038 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
2042 etm_get_reg(etm_ctrl_reg);
2044 /* Set programming bit (10), clear port selection bit (11) */
2045 buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x1);
2047 etm_store_reg(etm_ctrl_reg);
2048 jtag_execute_queue();
2050 etm_ctx->capture_driver->stop_capture(etm_ctx);
2055 COMMAND_HANDLER(handle_etm_analyze_command)
2057 struct target *target;
2059 struct etm_context *etm_ctx;
2062 target = get_current_target(CMD_CTX);
2063 arm = target_to_arm(target);
2066 command_print(CMD_CTX, "ETM: current target isn't an ARM");
2073 command_print(CMD_CTX, "current target doesn't have an ETM configured");
2077 if ((retval = etmv1_analyze_trace(etm_ctx, CMD_CTX)) != ERROR_OK)
2081 case ERROR_ETM_ANALYSIS_FAILED:
2082 command_print(CMD_CTX, "further analysis failed (corrupted trace data or just end of data");
2084 case ERROR_TRACE_INSTRUCTION_UNAVAILABLE:
2085 command_print(CMD_CTX, "no instruction for current address available, analysis aborted");
2087 case ERROR_TRACE_IMAGE_UNAVAILABLE:
2088 command_print(CMD_CTX, "no image available for trace analysis");
2091 command_print(CMD_CTX, "unknown error: %i", retval);
2098 int etm_register_commands(struct command_context *cmd_ctx)
2100 etm_cmd = COMMAND_REGISTER(cmd_ctx, NULL, "etm", NULL, COMMAND_ANY, "Embedded Trace Macrocell");
2102 COMMAND_REGISTER(cmd_ctx, etm_cmd, "config", handle_etm_config_command,
2103 COMMAND_CONFIG, "etm config <target> <port_width> <port_mode> <clocking> <capture_driver>");
2108 static int etm_register_user_commands(struct command_context *cmd_ctx)
2110 COMMAND_REGISTER(cmd_ctx, etm_cmd, "tracemode", handle_etm_tracemode_command,
2111 COMMAND_EXEC, "configure/display trace mode: "
2112 "<none | data | address | all> "
2113 "<context_id_bits> <cycle_accurate> <branch_output>");
2115 COMMAND_REGISTER(cmd_ctx, etm_cmd, "info", handle_etm_info_command,
2116 COMMAND_EXEC, "display info about the current target's ETM");
2118 COMMAND_REGISTER(cmd_ctx, etm_cmd, "trigger_percent", handle_etm_trigger_percent_command,
2119 COMMAND_EXEC, "amount (<percent>) of trace buffer to be filled after the trigger occured");
2120 COMMAND_REGISTER(cmd_ctx, etm_cmd, "status", handle_etm_status_command,
2121 COMMAND_EXEC, "display current target's ETM status");
2122 COMMAND_REGISTER(cmd_ctx, etm_cmd, "start", handle_etm_start_command,
2123 COMMAND_EXEC, "start ETM trace collection");
2124 COMMAND_REGISTER(cmd_ctx, etm_cmd, "stop", handle_etm_stop_command,
2125 COMMAND_EXEC, "stop ETM trace collection");
2127 COMMAND_REGISTER(cmd_ctx, etm_cmd, "analyze", handle_etm_analyze_command,
2128 COMMAND_EXEC, "anaylze collected ETM trace");
2130 COMMAND_REGISTER(cmd_ctx, etm_cmd, "image", handle_etm_image_command,
2131 COMMAND_EXEC, "load image from <file> [base address]");
2133 COMMAND_REGISTER(cmd_ctx, etm_cmd, "dump", handle_etm_dump_command,
2134 COMMAND_EXEC, "dump captured trace data <file>");
2135 COMMAND_REGISTER(cmd_ctx, etm_cmd, "load", handle_etm_load_command,
2136 COMMAND_EXEC, "load trace data for analysis <file>");