git.sur5r.net Git - openocd/blob - src/target/etm.h

   1 /***************************************************************************
   2  *   Copyright (C) 2005, 2007 by Dominic Rath                              *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2007 by Vincent Palatin                                 *
   6  *   vincent.palatin_openocd@m4x.org                                       *
   7  *                                                                         *
   8  *   This program is free software; you can redistribute it and/or modify  *
   9  *   it under the terms of the GNU General Public License as published by  *
  10  *   the Free Software Foundation; either version 2 of the License, or     *
  11  *   (at your option) any later version.                                   *
  12  *                                                                         *
  13  *   This program is distributed in the hope that it will be useful,       *
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  16  *   GNU General Public License for more details.                          *
  17  *                                                                         *
  18  *   You should have received a copy of the GNU General Public License     *
  19  *   along with this program; if not, write to the                         *
  20  *   Free Software Foundation, Inc.,                                       *
  21  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  22  ***************************************************************************/
  23 #ifndef ETM_H
  24 #define ETM_H
  25
  26 #include "image.h"
  27 #include "trace.h"
  28 #include "target.h"
  29 #include "register.h"
  30 #include "arm_jtag.h"
  31
  32 #include "armv4_5.h"
  33
  34 /* ETM registers (V1.3 protocol) */
  35 enum
  36 {
  37         ETM_CTRL = 0x00,
  38         ETM_CONFIG = 0x01,
  39         ETM_TRIG_EVENT = 0x02,
  40         ETM_MMD_CTRL = 0x03,
  41         ETM_STATUS = 0x04,
  42         ETM_SYS_CONFIG = 0x05,
  43         ETM_TRACE_RESOURCE_CTRL = 0x06,
  44         ETM_TRACE_EN_CTRL2 = 0x07,
  45         ETM_TRACE_EN_EVENT = 0x08,
  46         ETM_TRACE_EN_CTRL1 = 0x09,
  47         ETM_FIFOFULL_REGION = 0x0a,
  48         ETM_FIFOFULL_LEVEL = 0x0b,
  49         ETM_VIEWDATA_EVENT = 0x0c,
  50         ETM_VIEWDATA_CTRL1 = 0x0d,
  51         ETM_VIEWDATA_CTRL2 = 0x0e,
  52         ETM_VIEWDATA_CTRL3 = 0x0f,
  53         ETM_ADDR_COMPARATOR_VALUE = 0x10,
  54         ETM_ADDR_ACCESS_TYPE = 0x20,
  55         ETM_DATA_COMPARATOR_VALUE = 0x30,
  56         ETM_DATA_COMPARATOR_MASK = 0x40,
  57         ETM_COUNTER_INITAL_VALUE = 0x50,
  58         ETM_COUNTER_ENABLE = 0x54,
  59         ETM_COUNTER_RELOAD_VALUE = 0x58,
  60         ETM_COUNTER_VALUE = 0x5c,
  61         ETM_SEQUENCER_CTRL = 0x60,
  62         ETM_SEQUENCER_STATE = 0x67,
  63         ETM_EXTERNAL_OUTPUT = 0x68,
  64         ETM_CONTEXTID_COMPARATOR_VALUE = 0x6c,
  65         ETM_CONTEXTID_COMPARATOR_MASK = 0x6f,
  66 };
  67
  68 typedef struct etm_reg_s
  69 {
  70         int addr;
  71         arm_jtag_t *jtag_info;
  72 } etm_reg_t;
  73
  74 typedef enum
  75 {
  76         /* Port width */
  77         ETM_PORT_4BIT           = 0x00,
  78         ETM_PORT_8BIT           = 0x10,
  79         ETM_PORT_16BIT          = 0x20,
  80         ETM_PORT_WIDTH_MASK     = 0x70,
  81         /* Port modes */
  82         ETM_PORT_NORMAL    = 0x00000,
  83         ETM_PORT_MUXED     = 0x10000,
  84         ETM_PORT_DEMUXED   = 0x20000,
  85         ETM_PORT_MODE_MASK = 0x30000,
  86         /* Clocking modes */
  87         ETM_PORT_FULL_CLOCK = 0x0000,
  88         ETM_PORT_HALF_CLOCK = 0x1000,
  89         ETM_PORT_CLOCK_MASK = 0x1000,
  90 } etm_portmode_t;
  91
  92 typedef enum
  93 {
  94         /* Data trace */
  95         ETMV1_TRACE_NONE         = 0x00,
  96         ETMV1_TRACE_DATA     = 0x01,
  97         ETMV1_TRACE_ADDR     = 0x02,
  98         ETMV1_TRACE_MASK     = 0x03,
  99         /* ContextID */
 100         ETMV1_CONTEXTID_NONE = 0x00,
 101         ETMV1_CONTEXTID_8    = 0x10,
 102         ETMV1_CONTEXTID_16   = 0x20,
 103         ETMV1_CONTEXTID_32   = 0x30,
 104         ETMV1_CONTEXTID_MASK = 0x30,
 105         /* Misc */
 106         ETMV1_CYCLE_ACCURATE = 0x100,
 107         ETMV1_BRANCH_OUTPUT = 0x200
 108 } etmv1_tracemode_t;
 109
 110 /* forward-declare ETM context */
 111 struct etm_context_s;
 112
 113 typedef struct etm_capture_driver_s
 114 {
 115         char *name;
 116         int (*register_commands)(struct command_context_s *cmd_ctx);
 117         int (*init)(struct etm_context_s *etm_ctx);
 118         trace_status_t (*status)(struct etm_context_s *etm_ctx);
 119         int (*read_trace)(struct etm_context_s *etm_ctx);
 120         int (*start_capture)(struct etm_context_s *etm_ctx);
 121         int (*stop_capture)(struct etm_context_s *etm_ctx);
 122 } etm_capture_driver_t;
 123
 124 enum
 125 {
 126         ETMV1_TRACESYNC_CYCLE = 0x1,
 127         ETMV1_TRIGGER_CYCLE = 0x2,
 128 };
 129
 130 typedef struct etmv1_trace_data_s
 131 {
 132         u8 pipestat;    /* bits 0-2 pipeline status */
 133         u16 packet;             /* packet data (4, 8 or 16 bit) */
 134         int flags;              /* ETMV1_TRACESYNC_CYCLE, ETMV1_TRIGGER_CYCLE */
 135 } etmv1_trace_data_t;
 136
 137 /* describe a trace context
 138  * if support for ETMv2 or ETMv3 is to be implemented,
 139  * this will have to be split into version independent elements
 140  * and a version specific part
 141  */
 142 typedef struct etm_context_s
 143 {
 144         target_t *target;                               /* target this ETM is connected to */
 145         reg_cache_t *reg_cache;                 /* ETM register cache */
 146         etm_capture_driver_t *capture_driver;   /* driver used to access ETM data */
 147         void *capture_driver_priv;              /* capture driver private data */
 148         u32 trigger_percent;                    /* percent of trace buffer to be filled after the trigger */
 149         trace_status_t capture_status;  /* current state of capture run */
 150         etmv1_trace_data_t *trace_data; /* trace data */
 151         u32 trace_depth;                                /* number of trace cycles to be analyzed, 0 if no trace data available */
 152         etm_portmode_t portmode;                /* normal, multiplexed or demultiplexed */
 153         etmv1_tracemode_t tracemode;    /* type of information the trace contains (data, addres, contextID, ...) */
 154         armv4_5_state_t core_state;             /* current core state (ARM, Thumb, Jazelle) */
 155         image_t *image;                                 /* source for target opcodes */
 156         u32 pipe_index;                                 /* current trace cycle */
 157         u32 data_index;                                 /* cycle holding next data packet */
 158         int data_half;                                  /* port half on a 16 bit port */
 159         u32 current_pc;                                 /* current program counter */
 160         u32 pc_ok;                                              /* full PC has been acquired */
 161         u32 last_branch;                                /* last branch address output */
 162         u32 last_branch_reason;                 /* branch reason code for the last branch encountered */
 163         u32 last_ptr;                                   /* address of the last data access */
 164         u32 ptr_ok;                                             /* whether last_ptr is valid */
 165         u32 context_id;                                 /* context ID of the code being traced */
 166         u32 last_instruction;                   /* index of last instruction executed (to calculate cycle timings) */
 167 } etm_context_t;
 168
 169 /* PIPESTAT values */
 170 typedef enum
 171 {
 172         STAT_IE = 0x0,
 173         STAT_ID = 0x1,
 174         STAT_IN = 0x2,
 175         STAT_WT = 0x3,
 176         STAT_BE = 0x4,
 177         STAT_BD = 0x5,
 178         STAT_TR = 0x6,
 179         STAT_TD = 0x7
 180 } etmv1_pipestat_t;
 181
 182 /* branch reason values */
 183 typedef enum
 184 {
 185         BR_NORMAL  = 0x0, /* Normal PC change : periodic synchro (ETMv1.1) */
 186         BR_ENABLE  = 0x1, /* Trace has been enabled */
 187         BR_RESTART = 0x2, /* Trace restarted after a FIFO overflow */
 188         BR_NODEBUG = 0x3, /* ARM has exited for debug state */
 189         BR_PERIOD  = 0x4, /* Peridioc synchronization point (ETM>=v1.2)*/
 190         BR_RSVD5   = 0x5, /* reserved */
 191         BR_RSVD6   = 0x6, /* reserved */
 192         BR_RSVD7   = 0x7, /* reserved */
 193 } etmv1_branch_reason_t;
 194
 195 extern char *etmv1v1_branch_reason_strings[];
 196
 197 extern reg_cache_t* etm_build_reg_cache(target_t *target, arm_jtag_t *jtag_info, etm_context_t *etm_ctx);
 198 extern int etm_read_reg(reg_t *reg);
 199 extern int etm_write_reg(reg_t *reg, u32 value);
 200 extern int etm_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask);
 201 extern int etm_store_reg(reg_t *reg);
 202 extern int etm_set_reg(reg_t *reg, u32 value);
 203 extern int etm_set_reg_w_exec(reg_t *reg, u8 *buf);
 204 extern int etm_setup(target_t *target);
 205
 206 int etm_register_commands(struct command_context_s *cmd_ctx);
 207 int etm_register_user_commands(struct command_context_s *cmd_ctx);
 208 extern etm_context_t* etm_create_context(etm_portmode_t portmode, char *capture_driver_name);
 209
 210 #define ERROR_ETM_INVALID_DRIVER        (-1300)
 211 #define ERROR_ETM_PORTMODE_NOT_SUPPORTED        (-1301)
 212 #define ERROR_ETM_CAPTURE_INIT_FAILED   (-1302)
 213 #define ERROR_ETM_ANALYSIS_FAILED       (-1303)
 214
 215 #endif /* ETM_H */