1 /***************************************************************************
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2 * Copyright (C) 2005, 2007 by Dominic Rath *
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3 * Dominic.Rath@gmx.de *
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5 * Copyright (C) 2007 by Vincent Palatin *
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6 * vincent.palatin_openocd@m4x.org *
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8 * This program is free software; you can redistribute it and/or modify *
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9 * it under the terms of the GNU General Public License as published by *
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10 * the Free Software Foundation; either version 2 of the License, or *
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11 * (at your option) any later version. *
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13 * This program is distributed in the hope that it will be useful, *
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14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
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15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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16 * GNU General Public License for more details. *
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18 * You should have received a copy of the GNU General Public License *
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19 * along with this program; if not, write to the *
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20 * Free Software Foundation, Inc., *
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21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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22 ***************************************************************************/
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29 #include "register.h"
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30 #include "arm_jtag.h"
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32 #include "armv4_5.h"
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34 /* ETM registers (V1.3 protocol) */
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39 ETM_TRIG_EVENT = 0x02,
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40 ETM_MMD_CTRL = 0x03,
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42 ETM_SYS_CONFIG = 0x05,
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43 ETM_TRACE_RESOURCE_CTRL = 0x06,
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44 ETM_TRACE_EN_CTRL2 = 0x07,
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45 ETM_TRACE_EN_EVENT = 0x08,
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46 ETM_TRACE_EN_CTRL1 = 0x09,
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47 ETM_FIFOFULL_REGION = 0x0a,
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48 ETM_FIFOFULL_LEVEL = 0x0b,
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49 ETM_VIEWDATA_EVENT = 0x0c,
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50 ETM_VIEWDATA_CTRL1 = 0x0d,
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51 ETM_VIEWDATA_CTRL2 = 0x0e,
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52 ETM_VIEWDATA_CTRL3 = 0x0f,
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53 ETM_ADDR_COMPARATOR_VALUE = 0x10,
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54 ETM_ADDR_ACCESS_TYPE = 0x20,
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55 ETM_DATA_COMPARATOR_VALUE = 0x30,
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56 ETM_DATA_COMPARATOR_MASK = 0x40,
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57 ETM_COUNTER_INITAL_VALUE = 0x50,
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58 ETM_COUNTER_ENABLE = 0x54,
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59 ETM_COUNTER_RELOAD_VALUE = 0x58,
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60 ETM_COUNTER_VALUE = 0x5c,
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61 ETM_SEQUENCER_CTRL = 0x60,
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62 ETM_SEQUENCER_STATE = 0x67,
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63 ETM_EXTERNAL_OUTPUT = 0x68,
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64 ETM_CONTEXTID_COMPARATOR_VALUE = 0x6c,
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65 ETM_CONTEXTID_COMPARATOR_MASK = 0x6f,
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68 typedef struct etm_reg_s
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71 arm_jtag_t *jtag_info;
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77 ETM_PORT_4BIT = 0x00,
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78 ETM_PORT_8BIT = 0x10,
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79 ETM_PORT_16BIT = 0x20,
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80 ETM_PORT_WIDTH_MASK = 0x70,
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82 ETM_PORT_NORMAL = 0x00000,
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83 ETM_PORT_MUXED = 0x10000,
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84 ETM_PORT_DEMUXED = 0x20000,
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85 ETM_PORT_MODE_MASK = 0x30000,
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86 /* Clocking modes */
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87 ETM_PORT_FULL_CLOCK = 0x0000,
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88 ETM_PORT_HALF_CLOCK = 0x1000,
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89 ETM_PORT_CLOCK_MASK = 0x1000,
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95 ETMV1_TRACE_NONE = 0x00,
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96 ETMV1_TRACE_DATA = 0x01,
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97 ETMV1_TRACE_ADDR = 0x02,
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98 ETMV1_TRACE_MASK = 0x03,
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100 ETMV1_CONTEXTID_NONE = 0x00,
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101 ETMV1_CONTEXTID_8 = 0x10,
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102 ETMV1_CONTEXTID_16 = 0x20,
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103 ETMV1_CONTEXTID_32 = 0x30,
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104 ETMV1_CONTEXTID_MASK = 0x30,
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106 ETMV1_CYCLE_ACCURATE = 0x100,
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107 ETMV1_BRANCH_OUTPUT = 0x200
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108 } etmv1_tracemode_t;
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110 /* forward-declare ETM context */
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111 struct etm_context_s;
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113 typedef struct etm_capture_driver_s
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116 int (*register_commands)(struct command_context_s *cmd_ctx);
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117 int (*init)(struct etm_context_s *etm_ctx);
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118 trace_status_t (*status)(struct etm_context_s *etm_ctx);
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119 int (*read_trace)(struct etm_context_s *etm_ctx);
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120 int (*start_capture)(struct etm_context_s *etm_ctx);
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121 int (*stop_capture)(struct etm_context_s *etm_ctx);
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122 } etm_capture_driver_t;
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126 ETMV1_TRACESYNC_CYCLE = 0x1,
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127 ETMV1_TRIGGER_CYCLE = 0x2,
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130 typedef struct etmv1_trace_data_s
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132 u8 pipestat; /* bits 0-2 pipeline status */
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133 u16 packet; /* packet data (4, 8 or 16 bit) */
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134 int flags; /* ETMV1_TRACESYNC_CYCLE, ETMV1_TRIGGER_CYCLE */
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135 } etmv1_trace_data_t;
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137 /* describe a trace context
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138 * if support for ETMv2 or ETMv3 is to be implemented,
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139 * this will have to be split into version independent elements
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140 * and a version specific part
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142 typedef struct etm_context_s
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144 target_t *target; /* target this ETM is connected to */
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145 reg_cache_t *reg_cache; /* ETM register cache */
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146 etm_capture_driver_t *capture_driver; /* driver used to access ETM data */
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147 void *capture_driver_priv; /* capture driver private data */
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148 u32 trigger_percent; /* percent of trace buffer to be filled after the trigger */
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149 trace_status_t capture_status; /* current state of capture run */
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150 etmv1_trace_data_t *trace_data; /* trace data */
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151 u32 trace_depth; /* number of trace cycles to be analyzed, 0 if no trace data available */
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152 etm_portmode_t portmode; /* normal, multiplexed or demultiplexed */
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153 etmv1_tracemode_t tracemode; /* type of information the trace contains (data, addres, contextID, ...) */
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154 armv4_5_state_t core_state; /* current core state (ARM, Thumb, Jazelle) */
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155 image_t *image; /* source for target opcodes */
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156 u32 pipe_index; /* current trace cycle */
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157 u32 data_index; /* cycle holding next data packet */
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158 int data_half; /* port half on a 16 bit port */
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159 u32 current_pc; /* current program counter */
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160 u32 pc_ok; /* full PC has been acquired */
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161 u32 last_branch; /* last branch address output */
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162 u32 last_branch_reason; /* branch reason code for the last branch encountered */
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163 u32 last_ptr; /* address of the last data access */
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164 u32 ptr_ok; /* whether last_ptr is valid */
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165 u32 context_id; /* context ID of the code being traced */
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166 u32 last_instruction; /* index of last instruction executed (to calculate cycle timings) */
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169 /* PIPESTAT values */
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180 } etmv1_pipestat_t;
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182 /* branch reason values */
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185 BR_NORMAL = 0x0, /* Normal PC change : periodic synchro (ETMv1.1) */
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186 BR_ENABLE = 0x1, /* Trace has been enabled */
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187 BR_RESTART = 0x2, /* Trace restarted after a FIFO overflow */
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188 BR_NODEBUG = 0x3, /* ARM has exited for debug state */
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189 BR_PERIOD = 0x4, /* Peridioc synchronization point (ETM>=v1.2)*/
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190 BR_RSVD5 = 0x5, /* reserved */
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191 BR_RSVD6 = 0x6, /* reserved */
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192 BR_RSVD7 = 0x7, /* reserved */
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193 } etmv1_branch_reason_t;
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195 extern char *etmv1v1_branch_reason_strings[];
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197 extern reg_cache_t* etm_build_reg_cache(target_t *target, arm_jtag_t *jtag_info, etm_context_t *etm_ctx);
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198 extern int etm_read_reg(reg_t *reg);
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199 extern int etm_write_reg(reg_t *reg, u32 value);
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200 extern int etm_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask);
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201 extern int etm_store_reg(reg_t *reg);
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202 extern int etm_set_reg(reg_t *reg, u32 value);
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203 extern int etm_set_reg_w_exec(reg_t *reg, u8 *buf);
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205 int etm_register_commands(struct command_context_s *cmd_ctx);
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206 int etm_register_user_commands(struct command_context_s *cmd_ctx);
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207 extern etm_context_t* etm_create_context(etm_portmode_t portmode, char *capture_driver_name);
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209 #define ERROR_ETM_INVALID_DRIVER (-1300)
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210 #define ERROR_ETM_PORTMODE_NOT_SUPPORTED (-1301)
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211 #define ERROR_ETM_CAPTURE_INIT_FAILED (-1302)
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