1 mww 0x90600104 0x33313333
\r
2 mww 0xA0700000 0x00000001 # Enable the memory controller.
\r
3 mww 0xA0700024 0x00000006 # Set the refresh counter 6
\r
4 mww 0xA0700028 0x00000001 #
\r
5 mww 0xA0700030 0x00000001 # Set the precharge period
\r
6 mww 0xA0700034 0x00000004 # Active to precharge command period is 16 clock cycles
\r
7 mww 0xA070003C 0x00000001 # tAPR
\r
8 mww 0xA0700040 0x00000005 # tDAL
\r
9 mww 0xA0700044 0x00000001 # tWR
\r
10 mww 0xA0700048 0x00000006 # tRC 32 clock cycles
\r
11 mww 0xA070004C 0x00000006 # tRFC 32 clock cycles
\r
12 mww 0xA0700054 0x00000001 # tRRD
\r
13 mww 0xA0700058 0x00000001 # tMRD
\r
14 mww 0xA0700100 0x00004280 # Dynamic Config 0 (cs4)
\r
15 mww 0xA0700120 0x00004280 # Dynamic Config 1 (cs5)
\r
16 mww 0xA0700140 0x00004280 # Dynamic Config 2 (cs6)
\r
17 mww 0xA0700160 0x00004280 # Dynamic Config 3 (cs7)
\r
19 mww 0xA0700104 0x00000203 # CAS latency is 2 at 100 MHz
\r
20 mww 0xA0700124 0x00000203 # CAS latency is 2 at 100 MHz
\r
21 mww 0xA0700144 0x00000203 # CAS latency is 2 at 100 MHz
\r
22 mww 0xA0700164 0x00000203 # CAS latency is 2 at 100 MHz
\r
24 mww 0xA0700020 0x00000103 # issue SDRAM PALL command
\r
26 mww 0xA0700024 0x00000001 # Set the refresh counter to be as small as possible
\r
28 # Add some dummy writes to give the SDRAM time to settle, it needs two
\r
29 # AHB clock cycles, here we poke in the debugger flag, this lets
\r
30 # the software know that we are in the debugger
\r
31 mww 0xA0900000 0x00000002
\r
32 mww 0xA0900000 0x00000002
\r
33 mww 0xA0900000 0x00000002
\r
34 mww 0xA0900000 0x00000002
\r
35 mww 0xA0900000 0x00000002
\r
43 mww 0xA0700024 0x00000030 # Set the refresh counter to 30
\r
44 mww 0xA0700020 0x00000083 # Issue SDRAM MODE command
\r
46 # Next we perform a read of RAM.
\r
49 # mw 0x00022000:P, r3 # 22000 for cas2 latency, 32000 for cas 3
\r
51 mww 0xA0700020 0x00000003 # issue SDRAM NORMAL command
\r
52 mww 0xA0700100 0x00084280 # Enable buffer access
\r
53 mww 0xA0700120 0x00084280 # Enable buffer access
\r
54 mww 0xA0700140 0x00084280 # Enable buffer access
\r
55 mww 0xA0700160 0x00084280 # Enable buffer access
\r
57 #Set byte lane state (static mem 1)"
\r
58 mww 0xA0700220, 0x00000082
\r
60 mww 0xA09001F8, 0x50000000
\r
62 mww 0xA09001FC, 0xFF000001
\r
63 mww 0xA0700028, 0x00000001
\r
65 # RAMAddr = 0x00020000
\r
66 # RAMSize = 0x00004000
\r
68 # Set the processor mode
\r