1 /***************************************************************************
2 * Copyright (C) 2008 by Marvell Semiconductors, Inc. *
3 * Written by Nicolas Pitre <nico@marvell.com> *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
22 * Marvell Feroceon (88F5182, 88F5281) support.
24 * The Feroceon core mimics the ARM926 ICE interface with the following
27 * - the MOE (method of entry) reporting is not implemented
29 * - breakpoint/watchpoint comparator #1 is seemingly not implemented
31 * - due to a different pipeline implementation, some injected debug
32 * instruction sequences have to be somewhat different
36 * - asserting DBGRQ doesn't work if target is looping on the undef vector
38 * - the EICE version signature in the COMMS_CTL reg is next to the flow bits
39 * not at the top, and rather meaningless due to existing discrepencies
41 * - the DCC channel is half duplex (only one FIFO for both directions) with
42 * seemingly no proper flow control.
49 #include "arm926ejs.h"
52 #include "arm_simulator.h"
57 int feroceon_examine(struct command_context_s *cmd_ctx, struct target_s *target);
58 int feroceon_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
59 int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer);
60 int feroceon_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
63 target_type_t feroceon_target =
68 .arch_state = arm926ejs_arch_state,
70 .target_request_data = arm7_9_target_request_data,
73 .resume = arm7_9_resume,
76 .assert_reset = arm7_9_assert_reset,
77 .deassert_reset = arm7_9_deassert_reset,
78 .soft_reset_halt = arm926ejs_soft_reset_halt,
80 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
82 .read_memory = arm7_9_read_memory,
83 .write_memory = arm926ejs_write_memory,
84 .bulk_write_memory = feroceon_bulk_write_memory,
85 .checksum_memory = arm7_9_checksum_memory,
86 .blank_check_memory = arm7_9_blank_check_memory,
88 .run_algorithm = armv4_5_run_algorithm,
90 .add_breakpoint = arm7_9_add_breakpoint,
91 .remove_breakpoint = arm7_9_remove_breakpoint,
92 .add_watchpoint = arm7_9_add_watchpoint,
93 .remove_watchpoint = arm7_9_remove_watchpoint,
95 .register_commands = arm926ejs_register_commands,
96 .target_command = feroceon_target_command,
97 .init_target = feroceon_init_target,
98 .examine = feroceon_examine,
103 int feroceon_dummy_clock_out(arm_jtag_t *jtag_info, u32 instr)
105 scan_field_t fields[3];
108 u8 sysspeed_buf = 0x0;
111 buf_set_u32(out_buf, 0, 32, 0);
113 buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32));
115 jtag_add_end_state(TAP_PD);
116 arm_jtag_scann(jtag_info, 0x1);
118 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
120 fields[0].device = jtag_info->chain_pos;
121 fields[0].num_bits = 32;
122 fields[0].out_value = out_buf;
123 fields[0].out_mask = NULL;
124 fields[0].in_value = NULL;
125 fields[0].in_handler = NULL;
126 fields[0].in_handler_priv = NULL;
127 fields[0].in_check_value = NULL;
128 fields[0].in_check_mask = NULL;
130 fields[1].device = jtag_info->chain_pos;
131 fields[1].num_bits = 3;
132 fields[1].out_value = &sysspeed_buf;
133 fields[1].out_mask = NULL;
134 fields[1].in_value = NULL;
135 fields[1].in_check_value = NULL;
136 fields[1].in_check_mask = NULL;
137 fields[1].in_handler = NULL;
138 fields[1].in_handler_priv = NULL;
140 fields[2].device = jtag_info->chain_pos;
141 fields[2].num_bits = 32;
142 fields[2].out_value = instr_buf;
143 fields[2].out_mask = NULL;
144 fields[2].in_value = NULL;
145 fields[2].in_check_value = NULL;
146 fields[2].in_check_mask = NULL;
147 fields[2].in_handler = NULL;
148 fields[2].in_handler_priv = NULL;
150 jtag_add_dr_scan(3, fields, -1);
152 /* no jtag_add_runtest(0, -1) here */
157 void feroceon_change_to_arm(target_t *target, u32 *r0, u32 *pc)
159 armv4_5_common_t *armv4_5 = target->arch_info;
160 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
161 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
164 * save r0 before using it and put system in ARM state
165 * to allow common handling of ARM and THUMB debugging
168 feroceon_dummy_clock_out(jtag_info, ARMV4_5_T_NOP);
169 feroceon_dummy_clock_out(jtag_info, ARMV4_5_T_NOP);
170 feroceon_dummy_clock_out(jtag_info, ARMV4_5_T_NOP);
172 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
173 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
174 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
175 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, r0, 0);
176 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
177 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
179 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), 0, NULL, 0);
180 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
181 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
182 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
183 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, pc, 0);
184 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
185 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
187 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_BX(15), 0, NULL, 0);
188 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
189 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
190 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
191 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
193 jtag_execute_queue();
196 * fix program counter:
197 * MOV R0, PC was the 7th instruction (+12)
198 * reading PC in Thumb state gives address of instruction + 4
203 void feroceon_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
206 armv4_5_common_t *armv4_5 = target->arch_info;
207 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
208 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
210 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
211 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
212 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
214 for (i = 0; i <= 15; i++)
216 arm9tdmi_clock_data_in(jtag_info, core_regs[i]);
218 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
219 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
222 void feroceon_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size)
225 armv4_5_common_t *armv4_5 = target->arch_info;
226 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
227 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
228 int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
229 u32 *buf_u32 = buffer;
230 u16 *buf_u16 = buffer;
233 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
234 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
235 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
237 for (i = 0; i <= 15; i++)
239 if (mask & (1 << i)) {
243 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);
246 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be);
249 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be);
255 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
256 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
259 void feroceon_read_xpsr(target_t *target, u32 *xpsr, int spsr)
261 armv4_5_common_t *armv4_5 = target->arch_info;
262 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
263 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
265 arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
266 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
267 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
268 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
269 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
270 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
271 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
273 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, 1, 0, 0), 0, NULL, 0);
274 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
275 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
276 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, xpsr, 0);
278 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
279 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
282 void feroceon_write_xpsr(target_t *target, u32 xpsr, int spsr)
284 armv4_5_common_t *armv4_5 = target->arch_info;
285 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
286 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
288 LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
290 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0, NULL, 0);
291 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
292 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
293 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
294 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
295 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
296 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
298 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff00) >> 8, 0xc, 2, spsr), 0, NULL, 0);
299 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
300 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
301 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
302 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
303 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
304 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
306 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff0000) >> 16, 0x8, 4, spsr), 0, NULL, 0);
307 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
308 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
309 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
310 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
311 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
312 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
314 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff000000) >> 24, 0x4, 8, spsr), 0, NULL, 0);
315 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
316 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
317 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
318 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
319 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
320 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
323 void feroceon_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr)
325 armv4_5_common_t *armv4_5 = target->arch_info;
326 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
327 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
329 LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
331 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), 0, NULL, 0);
332 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
333 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
334 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
335 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
336 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
337 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
340 void feroceon_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
343 armv4_5_common_t *armv4_5 = target->arch_info;
344 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
345 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
347 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
348 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
349 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
351 for (i = 0; i <= 15; i++)
353 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, core_regs[i], NULL, 0);
355 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
356 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
357 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
360 void feroceon_branch_resume(target_t *target)
362 armv4_5_common_t *armv4_5 = target->arch_info;
363 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
364 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
366 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
367 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
368 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
369 arm9tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffff9, 0), 0, NULL, 0);
370 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
372 arm7_9->need_bypass_before_restart = 1;
375 void feroceon_branch_resume_thumb(target_t *target)
379 armv4_5_common_t *armv4_5 = target->arch_info;
380 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
381 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
382 u32 r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
383 u32 pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
385 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
386 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
387 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
388 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
390 arm9tdmi_clock_out(jtag_info, 0xE28F0001, 0, NULL, 0); // add r0,pc,#1
391 arm9tdmi_clock_out(jtag_info, ARMV4_5_BX(0), 0, NULL, 0);
392 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
393 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
395 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDMIA(0, 0x1), 0, NULL, 0);
396 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
397 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
399 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, pc, NULL, 0);
400 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
401 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
404 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7e9 + pc), 0, NULL, 0);
405 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 1);
407 arm7_9->need_bypass_before_restart = 1;
410 int feroceon_read_cp15(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 *value)
412 armv4_5_common_t *armv4_5 = target->arch_info;
413 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
414 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
417 arm9tdmi_clock_out(jtag_info, ARMV4_5_MRC(15, op1, 0, CRn, CRm, op2), 0, NULL, 0);
418 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
419 err = arm7_9_execute_sys_speed(target);
423 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, 1, 0, 0), 0, NULL, 0);
424 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
425 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
426 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, value, 0);
427 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
428 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
429 return jtag_execute_queue();
432 int feroceon_write_cp15(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 value)
434 armv4_5_common_t *armv4_5 = target->arch_info;
435 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
436 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
438 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 1, 0, 0), 0, NULL, 0);
439 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
440 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
441 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, value, NULL, 0);
442 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
443 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
444 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
446 arm9tdmi_clock_out(jtag_info, ARMV4_5_MCR(15, op1, 0, CRn, CRm, op2), 0, NULL, 0);
447 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
448 return arm7_9_execute_sys_speed(target);
451 void feroceon_set_dbgrq(target_t *target)
453 armv4_5_common_t *armv4_5 = target->arch_info;
454 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
455 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
457 buf_set_u32(dbg_ctrl->value, 0, 8, 2);
458 embeddedice_store_reg(dbg_ctrl);
461 void feroceon_enable_single_step(target_t *target)
463 armv4_5_common_t *armv4_5 = target->arch_info;
464 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
467 /* calculate PC of next instruction */
468 if (arm_simulate_step(target, &next_pc) != ERROR_OK)
470 u32 current_pc, current_opcode;
471 current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
472 target_read_u32(target, current_pc, ¤t_opcode);
473 LOG_ERROR("BUG: couldn't calculate PC of next instruction, "
474 "current opcode is 0x%8.8x", current_opcode);
475 next_pc = current_pc;
477 arm7_9_restore_context(target);
479 /* set a breakpoint there */
480 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], next_pc);
481 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0);
482 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
483 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
484 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
487 void feroceon_disable_single_step(target_t *target)
489 armv4_5_common_t *armv4_5 = target->arch_info;
490 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
492 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE]);
493 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
494 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
495 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
496 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
499 int feroceon_examine_debug_reason(target_t *target)
501 /* the MOE is not implemented */
502 if (target->debug_reason != DBG_REASON_SINGLESTEP)
504 target->debug_reason = DBG_REASON_DBGRQ;
510 int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
512 armv4_5_common_t *armv4_5 = target->arch_info;
513 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
514 enum armv4_5_state core_state = armv4_5->core_state;
515 u32 x, flip, shift, save[7];
519 * We can't use the dcc flow control bits, so let's transfer data
520 * with 31 bits and flip the MSB each time a new data word is sent.
522 static u32 dcc_code[] =
524 0xee115e10, /* 3: mrc p14, 0, r5, c1, c0, 0 */
525 0xe3a0301e, /* 1: mov r3, #30 */
526 0xe3a04002, /* mov r4, #2 */
527 0xee111e10, /* 2: mrc p14, 0, r1, c1, c0, 0 */
528 0xe1310005, /* teq r1, r5 */
529 0x0afffffc, /* beq 1b */
530 0xe1a05001, /* mov r5, r1 */
531 0xe1a01081, /* mov r1, r1, lsl #1 */
532 0xee112e10, /* 3: mrc p14, 0, r2, c1, c0, 0 */
533 0xe1320005, /* teq r2, r5 */
534 0x0afffffc, /* beq 3b */
535 0xe1a05002, /* mov r5, r2 */
536 0xe3c22102, /* bic r2, r2, #0x80000000 */
537 0xe1811332, /* orr r1, r1, r2, lsr r3 */
538 0xe2533001, /* subs r3, r3, #1 */
539 0xe4801004, /* str r1, [r0], #4 */
540 0xe1a01412, /* mov r1, r2, lsl r4 */
541 0xe2844001, /* add r4, r4, #1 */
542 0x4affffed, /* bmi 1b */
543 0xeafffff3, /* b 3b */
546 int dcc_size = sizeof(dcc_code);
548 if (!arm7_9->dcc_downloads)
549 return target->type->write_memory(target, address, 4, count, buffer);
551 /* regrab previously allocated working_area, or allocate a new one */
552 if (!arm7_9->dcc_working_area)
554 u8 dcc_code_buf[dcc_size];
556 /* make sure we have a working area */
557 if (target_alloc_working_area(target, dcc_size, &arm7_9->dcc_working_area) != ERROR_OK)
559 LOG_INFO("no working area available, falling back to memory writes");
560 return target->type->write_memory(target, address, 4, count, buffer);
563 /* copy target instructions to target endianness */
564 for (i = 0; i < dcc_size/4; i++)
565 target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
567 /* write DCC code to working area */
568 target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, dcc_size, dcc_code_buf);
571 /* backup clobbered processor state */
572 for (i = 0; i <= 5; i++)
573 save[i] = buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32);
574 save[i] = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
576 /* set up target address in r0 */
577 buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, address);
578 armv4_5->core_cache->reg_list[0].valid = 1;
579 armv4_5->core_cache->reg_list[0].dirty = 1;
580 armv4_5->core_state = ARMV4_5_STATE_ARM;
582 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], 0);
583 arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1);
589 for (i = 0; i < count; i++)
591 u32 y = target_buffer_get_u32(target, buffer);
592 u32 z = (x >> 1) | (y >> shift) | (flip ^= 0x80000000);
593 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], z);
594 x = y << (32 - shift);
595 if (++shift >= 32 || i + 1 >= count)
597 z = (x >> 1) | (flip ^= 0x80000000);
598 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], z);
606 while (target->state != TARGET_HALTED)
609 /* restore target state */
610 for (i = 0; i <= 5; i++)
612 buf_set_u32(armv4_5->core_cache->reg_list[i].value, 0, 32, save[i]);
613 armv4_5->core_cache->reg_list[i].valid = 1;
614 armv4_5->core_cache->reg_list[i].dirty = 1;
616 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, save[i]);
617 armv4_5->core_cache->reg_list[15].valid = 1;
618 armv4_5->core_cache->reg_list[15].dirty = 1;
619 armv4_5->core_state = core_state;
624 int feroceon_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
626 arm9tdmi_init_target(cmd_ctx, target);
635 int feroceon_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
638 char *variant = NULL;
639 armv4_5_common_t *armv4_5;
640 arm7_9_common_t *arm7_9;
641 arm926ejs_common_t *arm926ejs = malloc(sizeof(arm926ejs_common_t));
642 memset(arm926ejs, 0, sizeof(*arm926ejs));
646 LOG_ERROR("'target arm926ejs' requires at least one additional argument");
650 chain_pos = strtoul(args[3], NULL, 0);
655 LOG_DEBUG("chain_pos: %i, variant: %s", chain_pos, variant);
657 arm926ejs_init_arch_info(target, arm926ejs, chain_pos, variant);
659 armv4_5 = target->arch_info;
660 arm7_9 = armv4_5->arch_info;
662 /* override some insn sequence functions */
663 arm7_9->change_to_arm = feroceon_change_to_arm;
664 arm7_9->read_core_regs = feroceon_read_core_regs;
665 arm7_9->read_core_regs_target_buffer = feroceon_read_core_regs_target_buffer;
666 arm7_9->read_xpsr = feroceon_read_xpsr;
667 arm7_9->write_xpsr = feroceon_write_xpsr;
668 arm7_9->write_xpsr_im8 = feroceon_write_xpsr_im8;
669 arm7_9->write_core_regs = feroceon_write_core_regs;
670 arm7_9->branch_resume = feroceon_branch_resume;
671 arm7_9->branch_resume_thumb = feroceon_branch_resume_thumb;
673 /* must be implemented with only one comparator */
674 arm7_9->enable_single_step = feroceon_enable_single_step;
675 arm7_9->disable_single_step = feroceon_disable_single_step;
677 /* MOE is not implemented */
678 arm7_9->examine_debug_reason = feroceon_examine_debug_reason;
680 /* the standard ARM926 methods don't always work (don't ask...) */
681 arm926ejs->read_cp15 = feroceon_read_cp15;
682 arm926ejs->write_cp15 = feroceon_write_cp15;
684 /* Note: asserting DBGRQ might not win over the undef exception.
685 If that happens then just use "arm7_9 dbgrq disable". */
686 arm7_9->use_dbgrq = 1;
687 arm7_9->set_special_dbgrq = feroceon_set_dbgrq;
689 /* only one working comparator */
690 arm7_9->wp_available = 1;
691 arm7_9->wp1_used = -1;
697 int feroceon_examine(struct command_context_s *cmd_ctx, struct target_s *target)
699 armv4_5_common_t *armv4_5;
700 arm7_9_common_t *arm7_9;
703 retval = arm9tdmi_examine(cmd_ctx, target);
704 if (retval!=ERROR_OK)
707 armv4_5 = target->arch_info;
708 arm7_9 = armv4_5->arch_info;
710 /* the COMMS_CTRL bits are all contiguous */
711 if (buf_get_u32(arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL].value, 2, 4) != 6)
712 LOG_ERROR("unexpected Feroceon EICE version signature");
714 arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].size = 6;
715 arm7_9->eice_cache->reg_list[EICE_DBG_STAT].size = 5;
716 arm7_9->has_monitor_mode = 1;
718 /* vector catch reg is not initialized on reset */
719 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0);
721 /* clear monitor mode, enable comparators */
722 embeddedice_read_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
723 jtag_execute_queue();
724 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 4, 1, 0);
725 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 5, 1, 0);
726 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);