git.sur5r.net Git - openocd/blob - src/target/hla_target.c

   1 /***************************************************************************
   2  *   Copyright (C) 2011 by Mathias Kuester                                 *
   3  *   Mathias Kuester <kesmtp@freenet.de>                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2011 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   This program is free software; you can redistribute it and/or modify  *
   9  *   it under the terms of the GNU General Public License as published by  *
  10  *   the Free Software Foundation; either version 2 of the License, or     *
  11  *   (at your option) any later version.                                   *
  12  *                                                                         *
  13  *   This program is distributed in the hope that it will be useful,       *
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  16  *   GNU General Public License for more details.                          *
  17  *                                                                         *
  18  *   You should have received a copy of the GNU General Public License     *
  19  *   along with this program; if not, write to the                         *
  20  *   Free Software Foundation, Inc.,                                       *
  21  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  22  ***************************************************************************/
  23
  24 #ifdef HAVE_CONFIG_H
  25 #include "config.h"
  26 #endif
  27
  28 #include "jtag/jtag.h"
  29 #include "jtag/hla/hla_transport.h"
  30 #include "jtag/hla/hla_interface.h"
  31 #include "jtag/hla/hla_layout.h"
  32 #include "register.h"
  33 #include "algorithm.h"
  34 #include "target.h"
  35 #include "breakpoints.h"
  36 #include "target_type.h"
  37 #include "armv7m.h"
  38 #include "cortex_m.h"
  39 #include "arm_semihosting.h"
  40
  41 #define ARMV7M_SCS_DCRSR        0xe000edf4
  42 #define ARMV7M_SCS_DCRDR        0xe000edf8
  43
  44 static inline struct hl_interface_s *target_to_adapter(struct target *target)
  45 {
  46         return target->tap->priv;
  47 }
  48
  49 static int adapter_load_core_reg_u32(struct target *target,
  50                 uint32_t num, uint32_t *value)
  51 {
  52         int retval;
  53         struct hl_interface_s *adapter = target_to_adapter(target);
  54
  55         LOG_DEBUG("%s", __func__);
  56
  57         /* NOTE:  we "know" here that the register identifiers used
  58          * in the v7m header match the Cortex-M3 Debug Core Register
  59          * Selector values for R0..R15, xPSR, MSP, and PSP.
  60          */
  61         switch (num) {
  62         case 0 ... 18:
  63                 /* read a normal core register */
  64                 retval = adapter->layout->api->read_reg(adapter->fd, num, value);
  65
  66                 if (retval != ERROR_OK) {
  67                         LOG_ERROR("JTAG failure %i", retval);
  68                         return ERROR_JTAG_DEVICE_ERROR;
  69                 }
  70                 LOG_DEBUG("load from core reg %i  value 0x%" PRIx32 "", (int)num, *value);
  71                 break;
  72
  73         case ARMV7M_FPSID:
  74         case ARMV7M_FPEXC:
  75                 *value = 0;
  76                 break;
  77
  78         case ARMV7M_FPSCR:
  79                 /* Floating-point Status and Registers */
  80                 retval = target_write_u32(target, ARMV7M_SCS_DCRSR, 33);
  81                 if (retval != ERROR_OK)
  82                         return retval;
  83                 retval = target_read_u32(target, ARMV7M_SCS_DCRDR, value);
  84                 if (retval != ERROR_OK)
  85                         return retval;
  86                 LOG_DEBUG("load from core reg %i  value 0x%" PRIx32 "", (int)num, *value);
  87                 break;
  88
  89         case ARMV7M_S0 ... ARMV7M_S31:
  90                 /* Floating-point Status and Registers */
  91                 retval = target_write_u32(target, ARMV7M_SCS_DCRSR, num-ARMV7M_S0+64);
  92                 if (retval != ERROR_OK)
  93                         return retval;
  94                 retval = target_read_u32(target, ARMV7M_SCS_DCRDR, value);
  95                 if (retval != ERROR_OK)
  96                         return retval;
  97                 LOG_DEBUG("load from core reg %i  value 0x%" PRIx32 "", (int)num, *value);
  98                 break;
  99
 100         case ARMV7M_D0 ... ARMV7M_D15:
 101                 value = 0;
 102                 break;
 103
 104         case ARMV7M_PRIMASK:
 105         case ARMV7M_BASEPRI:
 106         case ARMV7M_FAULTMASK:
 107         case ARMV7M_CONTROL:
 108                 /* Cortex-M3 packages these four registers as bitfields
 109                  * in one Debug Core register.  So say r0 and r2 docs;
 110                  * it was removed from r1 docs, but still works.
 111                  */
 112                 retval = adapter->layout->api->read_reg(adapter->fd, 20, value);
 113                 if (retval != ERROR_OK)
 114                         return retval;
 115
 116                 switch (num) {
 117                 case ARMV7M_PRIMASK:
 118                         *value = buf_get_u32((uint8_t *) value, 0, 1);
 119                         break;
 120
 121                 case ARMV7M_BASEPRI:
 122                         *value = buf_get_u32((uint8_t *) value, 8, 8);
 123                         break;
 124
 125                 case ARMV7M_FAULTMASK:
 126                         *value = buf_get_u32((uint8_t *) value, 16, 1);
 127                         break;
 128
 129                 case ARMV7M_CONTROL:
 130                         *value = buf_get_u32((uint8_t *) value, 24, 2);
 131                         break;
 132                 }
 133
 134                 LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "",
 135                           (int)num, *value);
 136                 break;
 137
 138         default:
 139                 return ERROR_COMMAND_SYNTAX_ERROR;
 140         }
 141
 142         return ERROR_OK;
 143 }
 144
 145 static int adapter_store_core_reg_u32(struct target *target,
 146                 uint32_t num, uint32_t value)
 147 {
 148         int retval;
 149         uint32_t reg;
 150         struct armv7m_common *armv7m = target_to_armv7m(target);
 151         struct hl_interface_s *adapter = target_to_adapter(target);
 152
 153         LOG_DEBUG("%s", __func__);
 154
 155 #ifdef ARMV7_GDB_HACKS
 156         /* If the LR register is being modified, make sure it will put us
 157          * in "thumb" mode, or an INVSTATE exception will occur. This is a
 158          * hack to deal with the fact that gdb will sometimes "forge"
 159          * return addresses, and doesn't set the LSB correctly (i.e., when
 160          * printing expressions containing function calls, it sets LR = 0.)
 161          * Valid exception return codes have bit 0 set too.
 162          */
 163         if (num == ARMV7M_R14)
 164                 value |= 0x01;
 165 #endif
 166
 167         /* NOTE:  we "know" here that the register identifiers used
 168          * in the v7m header match the Cortex-M3 Debug Core Register
 169          * Selector values for R0..R15, xPSR, MSP, and PSP.
 170          */
 171         switch (num) {
 172         case 0 ... 18:
 173                 retval = adapter->layout->api->write_reg(adapter->fd, num, value);
 174
 175                 if (retval != ERROR_OK) {
 176                         struct reg *r;
 177
 178                         LOG_ERROR("JTAG failure");
 179                         r = armv7m->arm.core_cache->reg_list + num;
 180                         r->dirty = r->valid;
 181                         return ERROR_JTAG_DEVICE_ERROR;
 182                 }
 183                 LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
 184                 break;
 185
 186         case ARMV7M_FPSID:
 187         case ARMV7M_FPEXC:
 188                 break;
 189
 190         case ARMV7M_FPSCR:
 191                 /* Floating-point Status and Registers */
 192                 retval = target_write_u32(target, ARMV7M_SCS_DCRDR, value);
 193                 if (retval != ERROR_OK)
 194                         return retval;
 195                 retval = target_write_u32(target, ARMV7M_SCS_DCRSR, 33 | (1<<16));
 196                 if (retval != ERROR_OK)
 197                         return retval;
 198                 LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
 199                 break;
 200
 201         case ARMV7M_S0 ... ARMV7M_S31:
 202                 /* Floating-point Status and Registers */
 203                 retval = target_write_u32(target, ARMV7M_SCS_DCRDR, value);
 204                 if (retval != ERROR_OK)
 205                         return retval;
 206                 retval = target_write_u32(target, ARMV7M_SCS_DCRSR, (num-ARMV7M_S0+64) | (1<<16));
 207                 if (retval != ERROR_OK)
 208                         return retval;
 209                 LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
 210                 break;
 211
 212         case ARMV7M_D0 ... ARMV7M_D15:
 213                 break;
 214
 215         case ARMV7M_PRIMASK:
 216         case ARMV7M_BASEPRI:
 217         case ARMV7M_FAULTMASK:
 218         case ARMV7M_CONTROL:
 219                 /* Cortex-M3 packages these four registers as bitfields
 220                  * in one Debug Core register.  So say r0 and r2 docs;
 221                  * it was removed from r1 docs, but still works.
 222                  */
 223
 224                 adapter->layout->api->read_reg(adapter->fd, 20, &reg);
 225
 226                 switch (num) {
 227                 case ARMV7M_PRIMASK:
 228                         buf_set_u32((uint8_t *) &reg, 0, 1, value);
 229                         break;
 230
 231                 case ARMV7M_BASEPRI:
 232                         buf_set_u32((uint8_t *) &reg, 8, 8, value);
 233                         break;
 234
 235                 case ARMV7M_FAULTMASK:
 236                         buf_set_u32((uint8_t *) &reg, 16, 1, value);
 237                         break;
 238
 239                 case ARMV7M_CONTROL:
 240                         buf_set_u32((uint8_t *) &reg, 24, 2, value);
 241                         break;
 242                 }
 243
 244                 adapter->layout->api->write_reg(adapter->fd, 20, reg);
 245
 246                 LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
 247                 break;
 248
 249         default:
 250                 return ERROR_COMMAND_SYNTAX_ERROR;
 251         }
 252
 253         return ERROR_OK;
 254 }
 255
 256 static int adapter_examine_debug_reason(struct target *target)
 257 {
 258         if ((target->debug_reason != DBG_REASON_DBGRQ)
 259                         && (target->debug_reason != DBG_REASON_SINGLESTEP)) {
 260                 target->debug_reason = DBG_REASON_BREAKPOINT;
 261         }
 262
 263         return ERROR_OK;
 264 }
 265
 266 static int adapter_init_arch_info(struct target *target,
 267                                        struct cortex_m3_common *cortex_m3,
 268                                        struct jtag_tap *tap)
 269 {
 270         struct armv7m_common *armv7m;
 271
 272         LOG_DEBUG("%s", __func__);
 273
 274         armv7m = &cortex_m3->armv7m;
 275         armv7m_init_arch_info(target, armv7m);
 276
 277         armv7m->load_core_reg_u32 = adapter_load_core_reg_u32;
 278         armv7m->store_core_reg_u32 = adapter_store_core_reg_u32;
 279
 280         armv7m->examine_debug_reason = adapter_examine_debug_reason;
 281         armv7m->stlink = true;
 282
 283         return ERROR_OK;
 284 }
 285
 286 static int adapter_init_target(struct command_context *cmd_ctx,
 287                                     struct target *target)
 288 {
 289         LOG_DEBUG("%s", __func__);
 290
 291         armv7m_build_reg_cache(target);
 292
 293         return ERROR_OK;
 294 }
 295
 296 static int adapter_target_create(struct target *target,
 297                 Jim_Interp *interp)
 298 {
 299         LOG_DEBUG("%s", __func__);
 300
 301         struct cortex_m3_common *cortex_m3 = calloc(1, sizeof(struct cortex_m3_common));
 302
 303         if (!cortex_m3)
 304                 return ERROR_COMMAND_SYNTAX_ERROR;
 305
 306         adapter_init_arch_info(target, cortex_m3, target->tap);
 307
 308         return ERROR_OK;
 309 }
 310
 311 static int adapter_load_context(struct target *target)
 312 {
 313         struct armv7m_common *armv7m = target_to_armv7m(target);
 314         int num_regs = armv7m->arm.core_cache->num_regs;
 315
 316         for (int i = 0; i < num_regs; i++) {
 317
 318                 struct reg *r = &armv7m->arm.core_cache->reg_list[i];
 319                 if (!r->valid)
 320                         armv7m->arm.read_core_reg(target, r, i, ARM_MODE_ANY);
 321         }
 322
 323         return ERROR_OK;
 324 }
 325
 326 static int adapter_debug_entry(struct target *target)
 327 {
 328         struct hl_interface_s *adapter = target_to_adapter(target);
 329         struct armv7m_common *armv7m = target_to_armv7m(target);
 330         struct arm *arm = &armv7m->arm;
 331         struct reg *r;
 332         uint32_t xPSR;
 333         int retval;
 334
 335         retval = armv7m->examine_debug_reason(target);
 336         if (retval != ERROR_OK)
 337                 return retval;
 338
 339         adapter_load_context(target);
 340
 341         /* make sure we clear the vector catch bit */
 342         adapter->layout->api->write_debug_reg(adapter->fd, DCB_DEMCR, TRCENA);
 343
 344         r = arm->core_cache->reg_list + ARMV7M_xPSR;
 345         xPSR = buf_get_u32(r->value, 0, 32);
 346
 347         /* Are we in an exception handler */
 348         if (xPSR & 0x1FF) {
 349                 armv7m->exception_number = (xPSR & 0x1FF);
 350
 351                 arm->core_mode = ARM_MODE_HANDLER;
 352                 arm->map = armv7m_msp_reg_map;
 353         } else {
 354                 unsigned control = buf_get_u32(arm->core_cache
 355                                 ->reg_list[ARMV7M_CONTROL].value, 0, 2);
 356
 357                 /* is this thread privileged? */
 358                 arm->core_mode = control & 1
 359                                 ? ARM_MODE_USER_THREAD
 360                                 : ARM_MODE_THREAD;
 361
 362                 /* which stack is it using? */
 363                 if (control & 2)
 364                         arm->map = armv7m_psp_reg_map;
 365                 else
 366                         arm->map = armv7m_msp_reg_map;
 367
 368                 armv7m->exception_number = 0;
 369         }
 370
 371         LOG_DEBUG("entered debug state in core mode: %s at PC 0x%08" PRIx32 ", target->state: %s",
 372                 arm_mode_name(arm->core_mode),
 373                 *(uint32_t *)(arm->pc->value),
 374                 target_state_name(target));
 375
 376         return retval;
 377 }
 378
 379 static int adapter_poll(struct target *target)
 380 {
 381         enum target_state state;
 382         struct hl_interface_s *adapter = target_to_adapter(target);
 383         struct armv7m_common *armv7m = target_to_armv7m(target);
 384         enum target_state prev_target_state = target->state;
 385
 386         state = adapter->layout->api->state(adapter->fd);
 387
 388         if (state == TARGET_UNKNOWN) {
 389                 LOG_ERROR("jtag status contains invalid mode value - communication failure");
 390                 return ERROR_TARGET_FAILURE;
 391         }
 392
 393         if (target->state == state)
 394                 return ERROR_OK;
 395
 396         if (state == TARGET_HALTED) {
 397                 target->state = state;
 398
 399                 int retval = adapter_debug_entry(target);
 400                 if (retval != ERROR_OK)
 401                         return retval;
 402
 403                 if (prev_target_state == TARGET_DEBUG_RUNNING) {
 404                         target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
 405                 } else {
 406                         if (arm_semihosting(target, &retval) != 0)
 407                                 return retval;
 408
 409                         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 410                 }
 411
 412                 LOG_DEBUG("halted: PC: 0x%08x", buf_get_u32(armv7m->arm.pc->value, 0, 32));
 413         }
 414
 415         return ERROR_OK;
 416 }
 417
 418 static int adapter_assert_reset(struct target *target)
 419 {
 420         int res = ERROR_OK;
 421         struct hl_interface_s *adapter = target_to_adapter(target);
 422         struct armv7m_common *armv7m = target_to_armv7m(target);
 423         bool use_srst_fallback = true;
 424
 425         LOG_DEBUG("%s", __func__);
 426
 427         enum reset_types jtag_reset_config = jtag_get_reset_config();
 428
 429         bool srst_asserted = false;
 430
 431         if ((jtag_reset_config & RESET_HAS_SRST) &&
 432             (jtag_reset_config & RESET_SRST_NO_GATING)) {
 433                 jtag_add_reset(0, 1);
 434                 res = adapter->layout->api->assert_srst(adapter->fd, 0);
 435                 srst_asserted = true;
 436         }
 437
 438         adapter->layout->api->write_debug_reg(adapter->fd, DCB_DHCSR, DBGKEY|C_DEBUGEN);
 439
 440         /* only set vector catch if halt is requested */
 441         if (target->reset_halt)
 442                 adapter->layout->api->write_debug_reg(adapter->fd, DCB_DEMCR, TRCENA|VC_CORERESET);
 443         else
 444                 adapter->layout->api->write_debug_reg(adapter->fd, DCB_DEMCR, TRCENA);
 445
 446         if (jtag_reset_config & RESET_HAS_SRST) {
 447                 if (!srst_asserted) {
 448                         jtag_add_reset(0, 1);
 449                         res = adapter->layout->api->assert_srst(adapter->fd, 0);
 450                 }
 451                 if (res == ERROR_COMMAND_NOTFOUND)
 452                         LOG_ERROR("Hardware srst not supported, falling back to software reset");
 453                 else if (res == ERROR_OK) {
 454                         /* hardware srst supported */
 455                         use_srst_fallback = false;
 456                 }
 457         }
 458
 459         if (use_srst_fallback) {
 460                 /* stlink v1 api does not support hardware srst, so we use a software reset fallback */
 461                 adapter->layout->api->write_debug_reg(adapter->fd, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_SYSRESETREQ);
 462         }
 463
 464         res = adapter->layout->api->reset(adapter->fd);
 465
 466         if (res != ERROR_OK)
 467                 return res;
 468
 469         /* registers are now invalid */
 470         register_cache_invalidate(armv7m->arm.core_cache);
 471
 472         if (target->reset_halt) {
 473                 target->state = TARGET_RESET;
 474                 target->debug_reason = DBG_REASON_DBGRQ;
 475         } else {
 476                 target->state = TARGET_HALTED;
 477         }
 478
 479         return ERROR_OK;
 480 }
 481
 482 static int adapter_deassert_reset(struct target *target)
 483 {
 484         int res;
 485         struct hl_interface_s *adapter = target_to_adapter(target);
 486
 487         enum reset_types jtag_reset_config = jtag_get_reset_config();
 488
 489         LOG_DEBUG("%s", __func__);
 490
 491         if (jtag_reset_config & RESET_HAS_SRST)
 492                 adapter->layout->api->assert_srst(adapter->fd, 1);
 493
 494         /* virtual deassert reset, we need it for the internal
 495          * jtag state machine
 496          */
 497         jtag_add_reset(0, 0);
 498
 499         if (!target->reset_halt) {
 500                 res = target_resume(target, 1, 0, 0, 0);
 501
 502                 if (res != ERROR_OK)
 503                         return res;
 504         }
 505
 506         return ERROR_OK;
 507 }
 508
 509 static int adapter_soft_reset_halt(struct target *target)
 510 {
 511         LOG_DEBUG("%s", __func__);
 512         return ERROR_OK;
 513 }
 514
 515 static int adapter_halt(struct target *target)
 516 {
 517         int res;
 518         struct hl_interface_s *adapter = target_to_adapter(target);
 519
 520         LOG_DEBUG("%s", __func__);
 521
 522         if (target->state == TARGET_HALTED) {
 523                 LOG_DEBUG("target was already halted");
 524                 return ERROR_OK;
 525         }
 526
 527         if (target->state == TARGET_UNKNOWN)
 528                 LOG_WARNING("target was in unknown state when halt was requested");
 529
 530         res = adapter->layout->api->halt(adapter->fd);
 531
 532         if (res != ERROR_OK)
 533                 return res;
 534
 535         target->debug_reason = DBG_REASON_DBGRQ;
 536
 537         return ERROR_OK;
 538 }
 539
 540 static int adapter_resume(struct target *target, int current,
 541                 uint32_t address, int handle_breakpoints,
 542                 int debug_execution)
 543 {
 544         int res;
 545         struct hl_interface_s *adapter = target_to_adapter(target);
 546         struct armv7m_common *armv7m = target_to_armv7m(target);
 547         uint32_t resume_pc;
 548         struct breakpoint *breakpoint = NULL;
 549         struct reg *pc;
 550
 551         LOG_DEBUG("%s %d 0x%08x %d %d", __func__, current, address,
 552                         handle_breakpoints, debug_execution);
 553
 554         if (target->state != TARGET_HALTED) {
 555                 LOG_WARNING("target not halted");
 556                 return ERROR_TARGET_NOT_HALTED;
 557         }
 558
 559         if (!debug_execution) {
 560                 target_free_all_working_areas(target);
 561                 cortex_m3_enable_breakpoints(target);
 562                 cortex_m3_enable_watchpoints(target);
 563         }
 564
 565         pc = armv7m->arm.pc;
 566         if (!current) {
 567                 buf_set_u32(pc->value, 0, 32, address);
 568                 pc->dirty = true;
 569                 pc->valid = true;
 570         }
 571
 572         if (!breakpoint_find(target, buf_get_u32(pc->value, 0, 32))
 573                         && !debug_execution) {
 574                 armv7m_maybe_skip_bkpt_inst(target, NULL);
 575         }
 576
 577         resume_pc = buf_get_u32(pc->value, 0, 32);
 578
 579         /* write any user vector flags */
 580         res = target_write_u32(target, DCB_DEMCR, TRCENA | armv7m->demcr);
 581         if (res != ERROR_OK)
 582                 return res;
 583
 584         armv7m_restore_context(target);
 585
 586         /* registers are now invalid */
 587         register_cache_invalidate(armv7m->arm.core_cache);
 588
 589         /* the front-end may request us not to handle breakpoints */
 590         if (handle_breakpoints) {
 591                 /* Single step past breakpoint at current address */
 592                 breakpoint = breakpoint_find(target, resume_pc);
 593                 if (breakpoint) {
 594                         LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %d)",
 595                                         breakpoint->address,
 596                                         breakpoint->unique_id);
 597                         cortex_m3_unset_breakpoint(target, breakpoint);
 598
 599                         res = adapter->layout->api->step(adapter->fd);
 600
 601                         if (res != ERROR_OK)
 602                                 return res;
 603
 604                         cortex_m3_set_breakpoint(target, breakpoint);
 605                 }
 606         }
 607
 608         res = adapter->layout->api->run(adapter->fd);
 609
 610         if (res != ERROR_OK)
 611                 return res;
 612
 613         target->debug_reason = DBG_REASON_NOTHALTED;
 614
 615         if (!debug_execution) {
 616                 target->state = TARGET_RUNNING;
 617                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 618         } else {
 619                 target->state = TARGET_DEBUG_RUNNING;
 620                 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
 621         }
 622
 623         return ERROR_OK;
 624 }
 625
 626 static int adapter_step(struct target *target, int current,
 627                 uint32_t address, int handle_breakpoints)
 628 {
 629         int res;
 630         struct hl_interface_s *adapter = target_to_adapter(target);
 631         struct armv7m_common *armv7m = target_to_armv7m(target);
 632         struct breakpoint *breakpoint = NULL;
 633         struct reg *pc = armv7m->arm.pc;
 634         bool bkpt_inst_found = false;
 635
 636         LOG_DEBUG("%s", __func__);
 637
 638         if (target->state != TARGET_HALTED) {
 639                 LOG_WARNING("target not halted");
 640                 return ERROR_TARGET_NOT_HALTED;
 641         }
 642
 643         if (!current) {
 644                 buf_set_u32(pc->value, 0, 32, address);
 645                 pc->dirty = true;
 646                 pc->valid = true;
 647         }
 648
 649         uint32_t pc_value = buf_get_u32(pc->value, 0, 32);
 650
 651         /* the front-end may request us not to handle breakpoints */
 652         if (handle_breakpoints) {
 653                 breakpoint = breakpoint_find(target, pc_value);
 654                 if (breakpoint)
 655                         cortex_m3_unset_breakpoint(target, breakpoint);
 656         }
 657
 658         armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found);
 659
 660         target->debug_reason = DBG_REASON_SINGLESTEP;
 661
 662         armv7m_restore_context(target);
 663
 664         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 665
 666         res = adapter->layout->api->step(adapter->fd);
 667
 668         if (res != ERROR_OK)
 669                 return res;
 670
 671         /* registers are now invalid */
 672         register_cache_invalidate(armv7m->arm.core_cache);
 673
 674         if (breakpoint)
 675                 cortex_m3_set_breakpoint(target, breakpoint);
 676
 677         adapter_debug_entry(target);
 678         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 679
 680         LOG_INFO("halted: PC: 0x%08x", buf_get_u32(armv7m->arm.pc->value, 0, 32));
 681
 682         return ERROR_OK;
 683 }
 684
 685 static int adapter_read_memory(struct target *target, uint32_t address,
 686                 uint32_t size, uint32_t count,
 687                 uint8_t *buffer)
 688 {
 689         struct hl_interface_s *adapter = target_to_adapter(target);
 690         int res;
 691         uint32_t buffer_threshold = (adapter->param.max_buffer / 4);
 692         uint32_t addr_increment = 4;
 693         uint32_t c;
 694
 695         if (!count || !buffer)
 696                 return ERROR_COMMAND_SYNTAX_ERROR;
 697
 698         LOG_DEBUG("%s 0x%08x %d %d", __func__, address, size, count);
 699
 700         /* prepare byte count, buffer threshold
 701          * and address increment for none 32bit access
 702          */
 703         if (size != 4) {
 704                 count *= size;
 705                 buffer_threshold = (adapter->param.max_buffer / 4) / 2;
 706                 addr_increment = 1;
 707         }
 708
 709         while (count) {
 710                 if (count > buffer_threshold)
 711                         c = buffer_threshold;
 712                 else
 713                         c = count;
 714
 715                 if (size != 4)
 716                         res = adapter->layout->api->read_mem8(adapter->fd,
 717                                         address, c, buffer);
 718                 else
 719                         res = adapter->layout->api->read_mem32(adapter->fd,
 720                                         address, c, buffer);
 721
 722                 if (res != ERROR_OK)
 723                         return res;
 724
 725                 address += (c * addr_increment);
 726                 buffer += (c * addr_increment);
 727                 count -= c;
 728         }
 729
 730         return ERROR_OK;
 731 }
 732
 733 static int adapter_write_memory(struct target *target, uint32_t address,
 734                 uint32_t size, uint32_t count,
 735                 const uint8_t *buffer)
 736 {
 737         struct hl_interface_s *adapter = target_to_adapter(target);
 738         int res;
 739         uint32_t buffer_threshold = (adapter->param.max_buffer / 4);
 740         uint32_t addr_increment = 4;
 741         uint32_t c;
 742
 743         if (!count || !buffer)
 744                 return ERROR_COMMAND_SYNTAX_ERROR;
 745
 746         LOG_DEBUG("%s 0x%08x %d %d", __func__, address, size, count);
 747
 748         /* prepare byte count, buffer threshold
 749          * and address increment for none 32bit access
 750          */
 751         if (size != 4) {
 752                 count *= size;
 753                 buffer_threshold = (adapter->param.max_buffer / 4) / 2;
 754                 addr_increment = 1;
 755         }
 756
 757         while (count) {
 758                 if (count > buffer_threshold)
 759                         c = buffer_threshold;
 760                 else
 761                         c = count;
 762
 763                 if (size != 4)
 764                         res = adapter->layout->api->write_mem8(adapter->fd,
 765                                         address, c, buffer);
 766                 else
 767                         res = adapter->layout->api->write_mem32(adapter->fd,
 768                                         address, c, buffer);
 769
 770                 if (res != ERROR_OK)
 771                         return res;
 772
 773                 address += (c * addr_increment);
 774                 buffer += (c * addr_increment);
 775                 count -= c;
 776         }
 777
 778         return ERROR_OK;
 779 }
 780
 781 static const struct command_registration adapter_command_handlers[] = {
 782         {
 783                 .chain = arm_command_handlers,
 784         },
 785         COMMAND_REGISTRATION_DONE
 786 };
 787
 788 struct target_type hla_target = {
 789         .name = "hla_target",
 790         .deprecated_name = "stm32_stlink",
 791
 792         .init_target = adapter_init_target,
 793         .target_create = adapter_target_create,
 794         .examine = cortex_m3_examine,
 795         .commands = adapter_command_handlers,
 796
 797         .poll = adapter_poll,
 798         .arch_state = armv7m_arch_state,
 799
 800         .assert_reset = adapter_assert_reset,
 801         .deassert_reset = adapter_deassert_reset,
 802         .soft_reset_halt = adapter_soft_reset_halt,
 803
 804         .halt = adapter_halt,
 805         .resume = adapter_resume,
 806         .step = adapter_step,
 807
 808         .get_gdb_reg_list = armv7m_get_gdb_reg_list,
 809
 810         .read_memory = adapter_read_memory,
 811         .write_memory = adapter_write_memory,
 812         .checksum_memory = armv7m_checksum_memory,
 813         .blank_check_memory = armv7m_blank_check_memory,
 814
 815         .run_algorithm = armv7m_run_algorithm,
 816         .start_algorithm = armv7m_start_algorithm,
 817         .wait_algorithm = armv7m_wait_algorithm,
 818
 819         .add_breakpoint = cortex_m3_add_breakpoint,
 820         .remove_breakpoint = cortex_m3_remove_breakpoint,
 821         .add_watchpoint = cortex_m3_add_watchpoint,
 822         .remove_watchpoint = cortex_m3_remove_watchpoint,
 823 };