1 /***************************************************************************
2 * Copyright (C) 2008 by John McCarthy *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2008 by David T.L. Wong *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
18 * GNU General Public License for more details. *
20 * You should have received a copy of the GNU General Public License *
21 * along with this program; if not, write to the *
22 * Free Software Foundation, Inc., *
23 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
24 ***************************************************************************/
32 #include "mips32_dmaacc.h"
35 * The following logic shamelessly cloned from HairyDairyMaid's wrt54g_debrick
36 * to support the Broadcom BCM5352 SoC in the Linksys WRT54GL wireless router
37 * (and any others that support EJTAG DMA transfers).
38 * Note: This only supports memory read/write. Since the BCM5352 doesn't
39 * appear to support PRACC accesses, all debug functions except halt
40 * do not work. Still, this does allow erasing/writing flash as well as
41 * displaying/modifying memory and memory mapped registers.
44 static int ejtag_dma_read(mips_ejtag_t *ejtag_info, u32 addr, u32 *data)
48 int retries = RETRY_ATTEMPTS;
54 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
55 mips_ejtag_drscan_32(ejtag_info, &v);
57 /* Initiate DMA Read & set DSTRT */
58 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
59 ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
60 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
62 /* Wait for DSTRT to Clear */
64 ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
65 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
66 } while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
69 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
70 mips_ejtag_drscan_32(ejtag_info, data);
72 /* Clear DMA & Check DERR */
73 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
74 ejtag_ctrl = ejtag_info->ejtag_ctrl;
75 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
76 if (ejtag_ctrl & EJTAG_CTRL_DERR)
79 LOG_ERROR("DMA Read Addr = %08x Data = ERROR ON READ (retrying)\n", addr);
80 goto begin_ejtag_dma_read;
83 LOG_ERROR("DMA Read Addr = %08x Data = ERROR ON READ\n", addr);
84 return ERROR_JTAG_DEVICE_ERROR;
90 static int ejtag_dma_read_h(mips_ejtag_t *ejtag_info, u32 addr, u16 *data)
94 int retries = RETRY_ATTEMPTS;
96 begin_ejtag_dma_read_h:
100 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
101 mips_ejtag_drscan_32(ejtag_info, &v);
103 /* Initiate DMA Read & set DSTRT */
104 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
105 ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
106 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
108 /* Wait for DSTRT to Clear */
110 ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
111 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
112 } while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
115 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
116 mips_ejtag_drscan_32(ejtag_info, &v);
118 /* Clear DMA & Check DERR */
119 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
120 ejtag_ctrl = ejtag_info->ejtag_ctrl;
121 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
122 if (ejtag_ctrl & EJTAG_CTRL_DERR)
125 LOG_ERROR("DMA Read Addr = %08x Data = ERROR ON READ (retrying)\n", addr);
126 goto begin_ejtag_dma_read_h;
129 LOG_ERROR("DMA Read Addr = %08x Data = ERROR ON READ\n", addr);
130 return ERROR_JTAG_DEVICE_ERROR;
133 /* Handle the bigendian/littleendian */
135 *data = (v >> 16) & 0xffff;
137 *data = (v & 0x0000ffff);
142 static int ejtag_dma_read_b(mips_ejtag_t *ejtag_info, u32 addr, u8 *data)
146 int retries = RETRY_ATTEMPTS;
148 begin_ejtag_dma_read_b:
152 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
153 mips_ejtag_drscan_32(ejtag_info, &v);
155 /* Initiate DMA Read & set DSTRT */
156 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
157 ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
158 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
160 /* Wait for DSTRT to Clear */
162 ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
163 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
164 } while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
167 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
168 mips_ejtag_drscan_32(ejtag_info, &v);
170 /* Clear DMA & Check DERR */
171 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
172 ejtag_ctrl = ejtag_info->ejtag_ctrl;
173 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
174 if (ejtag_ctrl & EJTAG_CTRL_DERR)
177 LOG_ERROR("DMA Read Addr = %08x Data = ERROR ON READ (retrying)\n", addr);
178 goto begin_ejtag_dma_read_b;
181 LOG_ERROR("DMA Read Addr = %08x Data = ERROR ON READ\n", addr);
182 return ERROR_JTAG_DEVICE_ERROR;
185 /* Handle the bigendian/littleendian */
186 switch (addr & 0x3) {
191 *data = (v >> 8) & 0xff;
194 *data = (v >> 16) & 0xff;
197 *data = (v >> 24) & 0xff;
204 static int ejtag_dma_write(mips_ejtag_t *ejtag_info, u32 addr, u32 data)
208 int retries = RETRY_ATTEMPTS;
210 begin_ejtag_dma_write:
214 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
215 mips_ejtag_drscan_32(ejtag_info, &v);
219 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
220 mips_ejtag_drscan_32(ejtag_info, &v);
222 /* Initiate DMA Write & set DSTRT */
223 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
224 ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
225 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
227 /* Wait for DSTRT to Clear */
229 ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
230 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
231 } while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
233 /* Clear DMA & Check DERR */
234 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
235 ejtag_ctrl = ejtag_info->ejtag_ctrl;
236 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
237 if (ejtag_ctrl & EJTAG_CTRL_DERR)
240 LOG_ERROR("DMA Write Addr = %08x Data = ERROR ON WRITE (retrying)\n", addr);
241 goto begin_ejtag_dma_write;
244 LOG_ERROR("DMA Write Addr = %08x Data = ERROR ON WRITE\n", addr);
245 return ERROR_JTAG_DEVICE_ERROR;
251 static int ejtag_dma_write_h(mips_ejtag_t *ejtag_info, u32 addr, u32 data)
255 int retries = RETRY_ATTEMPTS;
257 /* Handle the bigendian/littleendian */
261 begin_ejtag_dma_write_h:
265 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
266 mips_ejtag_drscan_32(ejtag_info, &v);
270 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
271 mips_ejtag_drscan_32(ejtag_info, &v);
273 /* Initiate DMA Write & set DSTRT */
274 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
275 ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
276 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
278 /* Wait for DSTRT to Clear */
280 ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
281 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
282 } while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
284 /* Clear DMA & Check DERR */
285 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
286 ejtag_ctrl = ejtag_info->ejtag_ctrl;
287 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
288 if (ejtag_ctrl & EJTAG_CTRL_DERR)
291 LOG_ERROR("DMA Write Addr = %08x Data = ERROR ON WRITE (retrying)\n", addr);
292 goto begin_ejtag_dma_write_h;
295 LOG_ERROR("DMA Write Addr = %08x Data = ERROR ON WRITE\n", addr);
296 return ERROR_JTAG_DEVICE_ERROR;
302 static int ejtag_dma_write_b(mips_ejtag_t *ejtag_info, u32 addr, u32 data)
306 int retries = RETRY_ATTEMPTS;
308 /* Handle the bigendian/littleendian */
313 begin_ejtag_dma_write_b:
317 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
318 mips_ejtag_drscan_32(ejtag_info, &v);
322 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
323 mips_ejtag_drscan_32(ejtag_info, &v);
325 /* Initiate DMA Write & set DSTRT */
326 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
327 ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
328 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
330 /* Wait for DSTRT to Clear */
332 ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
333 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
334 } while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
336 /* Clear DMA & Check DERR */
337 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
338 ejtag_ctrl = ejtag_info->ejtag_ctrl;
339 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
340 if (ejtag_ctrl & EJTAG_CTRL_DERR)
343 LOG_ERROR("DMA Write Addr = %08x Data = ERROR ON WRITE (retrying)\n", addr);
344 goto begin_ejtag_dma_write_b;
347 LOG_ERROR("DMA Write Addr = %08x Data = ERROR ON WRITE\n", addr);
348 return ERROR_JTAG_DEVICE_ERROR;
354 int mips32_dmaacc_read_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf)
359 return mips32_dmaacc_read_mem8(ejtag_info, addr, count, (u8*)buf);
361 return mips32_dmaacc_read_mem16(ejtag_info, addr, count, (u16*)buf);
363 return mips32_dmaacc_read_mem32(ejtag_info, addr, count, (u32*)buf);
369 int mips32_dmaacc_read_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32 *buf)
374 for (i=0; i<count; i++) {
375 if ((retval = ejtag_dma_read(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK)
382 int mips32_dmaacc_read_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 *buf)
387 for (i=0; i<count; i++) {
388 if ((retval = ejtag_dma_read_h(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK)
395 int mips32_dmaacc_read_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, u8 *buf)
400 for (i=0; i<count; i++) {
401 if ((retval = ejtag_dma_read_b(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK)
408 int mips32_dmaacc_write_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf)
413 return mips32_dmaacc_write_mem8(ejtag_info, addr, count, (u8*)buf);
415 return mips32_dmaacc_write_mem16(ejtag_info, addr, count,(u16*)buf);
417 return mips32_dmaacc_write_mem32(ejtag_info, addr, count, (u32*)buf);
423 int mips32_dmaacc_write_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32 *buf)
428 for (i=0; i<count; i++) {
429 if ((retval = ejtag_dma_write(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK)
436 int mips32_dmaacc_write_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 *buf)
441 for (i=0; i<count; i++) {
442 if ((retval = ejtag_dma_write_h(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK)
449 int mips32_dmaacc_write_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, u8 *buf)
454 for (i=0; i<count; i++) {
455 if ((retval = ejtag_dma_write_b(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK)