1 /***************************************************************************
2 * Copyright (C) 2008 by John McCarthy *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2008 by David T.L. Wong *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
18 * GNU General Public License for more details. *
20 * You should have received a copy of the GNU General Public License *
21 * along with this program; if not, write to the *
22 * Free Software Foundation, Inc., *
23 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
24 ***************************************************************************/
30 #include "mips32_dmaacc.h"
31 #include <helper/time_support.h>
33 static int mips32_dmaacc_read_mem8(struct mips_ejtag *ejtag_info,
34 uint32_t addr, int count, uint8_t *buf);
35 static int mips32_dmaacc_read_mem16(struct mips_ejtag *ejtag_info,
36 uint32_t addr, int count, uint16_t *buf);
37 static int mips32_dmaacc_read_mem32(struct mips_ejtag *ejtag_info,
38 uint32_t addr, int count, uint32_t *buf);
40 static int mips32_dmaacc_write_mem8(struct mips_ejtag *ejtag_info,
41 uint32_t addr, int count, const uint8_t *buf);
42 static int mips32_dmaacc_write_mem16(struct mips_ejtag *ejtag_info,
43 uint32_t addr, int count, const uint16_t *buf);
44 static int mips32_dmaacc_write_mem32(struct mips_ejtag *ejtag_info,
45 uint32_t addr, int count, const uint32_t *buf);
48 * The following logic shamelessly cloned from HairyDairyMaid's wrt54g_debrick
49 * to support the Broadcom BCM5352 SoC in the Linksys WRT54GL wireless router
50 * (and any others that support EJTAG DMA transfers).
51 * Note: This only supports memory read/write. Since the BCM5352 doesn't
52 * appear to support PRACC accesses, all debug functions except halt
53 * do not work. Still, this does allow erasing/writing flash as well as
54 * displaying/modifying memory and memory mapped registers.
57 static int ejtag_dma_dstrt_poll(struct mips_ejtag *ejtag_info)
60 int64_t start = timeval_ms();
63 if (timeval_ms() - start > 1000) {
64 LOG_ERROR("DMA time out");
67 ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
68 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
69 } while (ejtag_ctrl & EJTAG_CTRL_DSTRT);
73 static int ejtag_dma_read(struct mips_ejtag *ejtag_info, uint32_t addr, uint32_t *data)
77 int retries = RETRY_ATTEMPTS;
83 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
84 mips_ejtag_drscan_32(ejtag_info, &v);
86 /* Initiate DMA Read & set DSTRT */
87 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
88 ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
89 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
91 /* Wait for DSTRT to Clear */
92 ejtag_dma_dstrt_poll(ejtag_info);
95 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
96 mips_ejtag_drscan_32(ejtag_info, data);
98 /* Clear DMA & Check DERR */
99 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
100 ejtag_ctrl = ejtag_info->ejtag_ctrl;
101 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
102 if (ejtag_ctrl & EJTAG_CTRL_DERR) {
104 LOG_ERROR("DMA Read Addr = %08" PRIx32 " Data = ERROR ON READ (retrying)", addr);
105 goto begin_ejtag_dma_read;
107 LOG_ERROR("DMA Read Addr = %08" PRIx32 " Data = ERROR ON READ", addr);
108 return ERROR_JTAG_DEVICE_ERROR;
114 static int ejtag_dma_read_h(struct mips_ejtag *ejtag_info, uint32_t addr, uint16_t *data)
118 int retries = RETRY_ATTEMPTS;
120 begin_ejtag_dma_read_h:
124 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
125 mips_ejtag_drscan_32(ejtag_info, &v);
127 /* Initiate DMA Read & set DSTRT */
128 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
129 ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_HALFWORD |
130 EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
131 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
133 /* Wait for DSTRT to Clear */
134 ejtag_dma_dstrt_poll(ejtag_info);
137 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
138 mips_ejtag_drscan_32(ejtag_info, &v);
140 /* Clear DMA & Check DERR */
141 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
142 ejtag_ctrl = ejtag_info->ejtag_ctrl;
143 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
144 if (ejtag_ctrl & EJTAG_CTRL_DERR) {
146 LOG_ERROR("DMA Read Addr = %08" PRIx32 " Data = ERROR ON READ (retrying)", addr);
147 goto begin_ejtag_dma_read_h;
149 LOG_ERROR("DMA Read Addr = %08" PRIx32 " Data = ERROR ON READ", addr);
150 return ERROR_JTAG_DEVICE_ERROR;
153 /* Handle the bigendian/littleendian */
155 *data = (v >> 16) & 0xffff;
157 *data = (v & 0x0000ffff);
162 static int ejtag_dma_read_b(struct mips_ejtag *ejtag_info, uint32_t addr, uint8_t *data)
166 int retries = RETRY_ATTEMPTS;
168 begin_ejtag_dma_read_b:
172 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
173 mips_ejtag_drscan_32(ejtag_info, &v);
175 /* Initiate DMA Read & set DSTRT */
176 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
177 ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
178 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
180 /* Wait for DSTRT to Clear */
181 ejtag_dma_dstrt_poll(ejtag_info);
184 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
185 mips_ejtag_drscan_32(ejtag_info, &v);
187 /* Clear DMA & Check DERR */
188 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
189 ejtag_ctrl = ejtag_info->ejtag_ctrl;
190 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
191 if (ejtag_ctrl & EJTAG_CTRL_DERR) {
193 LOG_ERROR("DMA Read Addr = %08" PRIx32 " Data = ERROR ON READ (retrying)", addr);
194 goto begin_ejtag_dma_read_b;
196 LOG_ERROR("DMA Read Addr = %08" PRIx32 " Data = ERROR ON READ", addr);
197 return ERROR_JTAG_DEVICE_ERROR;
200 /* Handle the bigendian/littleendian */
201 switch (addr & 0x3) {
206 *data = (v >> 8) & 0xff;
209 *data = (v >> 16) & 0xff;
212 *data = (v >> 24) & 0xff;
219 static int ejtag_dma_write(struct mips_ejtag *ejtag_info, uint32_t addr, uint32_t data)
223 int retries = RETRY_ATTEMPTS;
225 begin_ejtag_dma_write:
229 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
230 mips_ejtag_drscan_32(ejtag_info, &v);
234 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
235 mips_ejtag_drscan_32(ejtag_info, &v);
237 /* Initiate DMA Write & set DSTRT */
238 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
239 ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
240 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
242 /* Wait for DSTRT to Clear */
243 ejtag_dma_dstrt_poll(ejtag_info);
245 /* Clear DMA & Check DERR */
246 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
247 ejtag_ctrl = ejtag_info->ejtag_ctrl;
248 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
249 if (ejtag_ctrl & EJTAG_CTRL_DERR) {
251 LOG_ERROR("DMA Write Addr = %08" PRIx32 " Data = ERROR ON WRITE (retrying)", addr);
252 goto begin_ejtag_dma_write;
254 LOG_ERROR("DMA Write Addr = %08" PRIx32 " Data = ERROR ON WRITE", addr);
255 return ERROR_JTAG_DEVICE_ERROR;
261 static int ejtag_dma_write_h(struct mips_ejtag *ejtag_info, uint32_t addr, uint32_t data)
265 int retries = RETRY_ATTEMPTS;
267 /* Handle the bigendian/littleendian */
271 begin_ejtag_dma_write_h:
275 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
276 mips_ejtag_drscan_32(ejtag_info, &v);
280 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
281 mips_ejtag_drscan_32(ejtag_info, &v);
283 /* Initiate DMA Write & set DSTRT */
284 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
285 ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
286 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
288 /* Wait for DSTRT to Clear */
289 ejtag_dma_dstrt_poll(ejtag_info);
291 /* Clear DMA & Check DERR */
292 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
293 ejtag_ctrl = ejtag_info->ejtag_ctrl;
294 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
295 if (ejtag_ctrl & EJTAG_CTRL_DERR) {
297 LOG_ERROR("DMA Write Addr = %08" PRIx32 " Data = ERROR ON WRITE (retrying)", addr);
298 goto begin_ejtag_dma_write_h;
300 LOG_ERROR("DMA Write Addr = %08" PRIx32 " Data = ERROR ON WRITE", addr);
301 return ERROR_JTAG_DEVICE_ERROR;
307 static int ejtag_dma_write_b(struct mips_ejtag *ejtag_info, uint32_t addr, uint32_t data)
311 int retries = RETRY_ATTEMPTS;
313 /* Handle the bigendian/littleendian */
318 begin_ejtag_dma_write_b:
322 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
323 mips_ejtag_drscan_32(ejtag_info, &v);
327 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
328 mips_ejtag_drscan_32(ejtag_info, &v);
330 /* Initiate DMA Write & set DSTRT */
331 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
332 ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
333 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
335 /* Wait for DSTRT to Clear */
336 ejtag_dma_dstrt_poll(ejtag_info);
338 /* Clear DMA & Check DERR */
339 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
340 ejtag_ctrl = ejtag_info->ejtag_ctrl;
341 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
342 if (ejtag_ctrl & EJTAG_CTRL_DERR) {
344 LOG_ERROR("DMA Write Addr = %08" PRIx32 " Data = ERROR ON WRITE (retrying)", addr);
345 goto begin_ejtag_dma_write_b;
347 LOG_ERROR("DMA Write Addr = %08" PRIx32 " Data = ERROR ON WRITE", addr);
348 return ERROR_JTAG_DEVICE_ERROR;
354 int mips32_dmaacc_read_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int size, int count, void *buf)
358 return mips32_dmaacc_read_mem8(ejtag_info, addr, count, (uint8_t *)buf);
360 return mips32_dmaacc_read_mem16(ejtag_info, addr, count, (uint16_t *)buf);
362 return mips32_dmaacc_read_mem32(ejtag_info, addr, count, (uint32_t *)buf);
368 static int mips32_dmaacc_read_mem32(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint32_t *buf)
373 for (i = 0; i < count; i++) {
374 retval = ejtag_dma_read(ejtag_info, addr + i * sizeof(*buf), &buf[i]);
375 if (retval != ERROR_OK)
382 static int mips32_dmaacc_read_mem16(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint16_t *buf)
387 for (i = 0; i < count; i++) {
388 retval = ejtag_dma_read_h(ejtag_info, addr + i * sizeof(*buf), &buf[i]);
389 if (retval != ERROR_OK)
396 static int mips32_dmaacc_read_mem8(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint8_t *buf)
401 for (i = 0; i < count; i++) {
402 retval = ejtag_dma_read_b(ejtag_info, addr + i * sizeof(*buf), &buf[i]);
403 if (retval != ERROR_OK)
410 int mips32_dmaacc_write_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int size, int count, const void *buf)
414 return mips32_dmaacc_write_mem8(ejtag_info, addr, count, buf);
416 return mips32_dmaacc_write_mem16(ejtag_info, addr, count, buf);
418 return mips32_dmaacc_write_mem32(ejtag_info, addr, count, buf);
424 static int mips32_dmaacc_write_mem32(struct mips_ejtag *ejtag_info, uint32_t addr, int count, const uint32_t *buf)
429 for (i = 0; i < count; i++) {
430 retval = ejtag_dma_write(ejtag_info, addr + i * sizeof(*buf), buf[i]);
431 if (retval != ERROR_OK)
438 static int mips32_dmaacc_write_mem16(struct mips_ejtag *ejtag_info, uint32_t addr, int count, const uint16_t *buf)
443 for (i = 0; i < count; i++) {
444 retval = ejtag_dma_write_h(ejtag_info, addr + i * sizeof(*buf), buf[i]);
445 if (retval != ERROR_OK)
452 static int mips32_dmaacc_write_mem8(struct mips_ejtag *ejtag_info, uint32_t addr, int count, const uint8_t *buf)
457 for (i = 0; i < count; i++) {
458 retval = ejtag_dma_write_b(ejtag_info, addr + i * sizeof(*buf), buf[i]);
459 if (retval != ERROR_OK)