1 /***************************************************************************
2 * Copyright (C) 2008 by John McCarthy *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2008 by David T.L. Wong *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
18 * GNU General Public License for more details. *
20 * You should have received a copy of the GNU General Public License *
21 * along with this program; if not, write to the *
22 * Free Software Foundation, Inc., *
23 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
24 ***************************************************************************/
32 #include "mips32_dmaacc.h"
35 * The following logic shamelessly cloned from HairyDairyMaid's wrt54g_debrick
36 * to support the Broadcom BCM5352 SoC in the Linksys WRT54GL wireless router
37 * (and any others that support EJTAG DMA transfers).
38 * Note: This only supports memory read/write. Since the BCM5352 doesn't
39 * appear to support PRACC accesses, all debug functions except halt
40 * do not work. Still, this does allow erasing/writing flash as well as
41 * displaying/modifying memory and memory mapped registers.
44 static int ejtag_dma_read(mips_ejtag_t *ejtag_info, u32 addr, u32 *data)
48 int retries = RETRY_ATTEMPTS;
54 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
55 mips_ejtag_drscan_32(ejtag_info, &v);
57 // Initiate DMA Read & set DSTRT
58 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
59 ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
60 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
62 // Wait for DSTRT to Clear
64 ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
65 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
66 } while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
69 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
70 mips_ejtag_drscan_32(ejtag_info, data);
72 // Clear DMA & Check DERR
73 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
74 ejtag_ctrl = ejtag_info->ejtag_ctrl;
75 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
76 if (ejtag_ctrl & EJTAG_CTRL_DERR)
79 printf("DMA Read Addr = %08x Data = ERROR ON READ (retrying)\n", addr);
80 goto begin_ejtag_dma_read;
81 } else printf("DMA Read Addr = %08x Data = ERROR ON READ\n", addr);
82 return ERROR_JTAG_DEVICE_ERROR;
88 static int ejtag_dma_read_h(mips_ejtag_t *ejtag_info, u32 addr, u16 *data)
92 int retries = RETRY_ATTEMPTS;
94 begin_ejtag_dma_read_h:
98 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
99 mips_ejtag_drscan_32(ejtag_info, &v);
101 // Initiate DMA Read & set DSTRT
102 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
103 ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
104 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
106 // Wait for DSTRT to Clear
108 ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
109 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
110 } while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
113 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
114 mips_ejtag_drscan_32(ejtag_info, &v);
116 // Clear DMA & Check DERR
117 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
118 ejtag_ctrl = ejtag_info->ejtag_ctrl;
119 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
120 if (ejtag_ctrl & EJTAG_CTRL_DERR)
123 printf("DMA Read Addr = %08x Data = ERROR ON READ (retrying)\n", addr);
124 goto begin_ejtag_dma_read_h;
125 } else printf("DMA Read Addr = %08x Data = ERROR ON READ\n", addr);
126 return ERROR_JTAG_DEVICE_ERROR;
129 // Handle the bigendian/littleendian
130 if ( addr & 0x2 ) *data = (v>>16)&0xffff ;
131 else *data = (v&0x0000ffff) ;
136 static int ejtag_dma_read_b(mips_ejtag_t *ejtag_info, u32 addr, u8 *data)
140 int retries = RETRY_ATTEMPTS;
142 begin_ejtag_dma_read_b:
146 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
147 mips_ejtag_drscan_32(ejtag_info, &v);
149 // Initiate DMA Read & set DSTRT
150 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
151 ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
152 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
154 // Wait for DSTRT to Clear
156 ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
157 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
158 } while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
161 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
162 mips_ejtag_drscan_32(ejtag_info, &v);
164 // Clear DMA & Check DERR
165 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
166 ejtag_ctrl = ejtag_info->ejtag_ctrl;
167 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
168 if (ejtag_ctrl & EJTAG_CTRL_DERR)
171 printf("DMA Read Addr = %08x Data = ERROR ON READ (retrying)\n", addr);
172 goto begin_ejtag_dma_read_b;
173 } else printf("DMA Read Addr = %08x Data = ERROR ON READ\n", addr);
174 return ERROR_JTAG_DEVICE_ERROR;
177 // Handle the bigendian/littleendian
179 case 0: *data = v & 0xff; break;
180 case 1: *data = (v>>8) & 0xff; break;
181 case 2: *data = (v>>16) & 0xff; break;
182 case 3: *data = (v>>24) & 0xff; break;
188 static int ejtag_dma_write(mips_ejtag_t *ejtag_info, u32 addr, u32 data)
192 int retries = RETRY_ATTEMPTS;
194 begin_ejtag_dma_write:
198 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
199 mips_ejtag_drscan_32(ejtag_info, &v);
203 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
204 mips_ejtag_drscan_32(ejtag_info, &v);
206 // Initiate DMA Write & set DSTRT
207 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
208 ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
209 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
211 // Wait for DSTRT to Clear
213 ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
214 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
215 } while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
217 // Clear DMA & Check DERR
218 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
219 ejtag_ctrl = ejtag_info->ejtag_ctrl;
220 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
221 if (ejtag_ctrl & EJTAG_CTRL_DERR)
224 printf("DMA Write Addr = %08x Data = ERROR ON WRITE (retrying)\n", addr);
225 goto begin_ejtag_dma_write;
226 } else printf("DMA Write Addr = %08x Data = ERROR ON WRITE\n", addr);
227 return ERROR_JTAG_DEVICE_ERROR;
233 static int ejtag_dma_write_h(mips_ejtag_t *ejtag_info, u32 addr, u32 data)
237 int retries = RETRY_ATTEMPTS;
240 // Handle the bigendian/littleendian
244 begin_ejtag_dma_write_h:
248 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
249 mips_ejtag_drscan_32(ejtag_info, &v);
253 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
254 mips_ejtag_drscan_32(ejtag_info, &v);
256 // Initiate DMA Write & set DSTRT
257 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
258 ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
259 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
261 // Wait for DSTRT to Clear
263 ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
264 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
265 } while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
267 // Clear DMA & Check DERR
268 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
269 ejtag_ctrl = ejtag_info->ejtag_ctrl;
270 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
271 if (ejtag_ctrl & EJTAG_CTRL_DERR)
274 printf("DMA Write Addr = %08x Data = ERROR ON WRITE (retrying)\n", addr);
275 goto begin_ejtag_dma_write_h;
276 } else printf("DMA Write Addr = %08x Data = ERROR ON WRITE\n", addr);
277 return ERROR_JTAG_DEVICE_ERROR;
283 static int ejtag_dma_write_b(mips_ejtag_t *ejtag_info, u32 addr, u32 data)
287 int retries = RETRY_ATTEMPTS;
290 // Handle the bigendian/littleendian
295 begin_ejtag_dma_write_b:
299 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
300 mips_ejtag_drscan_32(ejtag_info, &v);
304 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
305 mips_ejtag_drscan_32(ejtag_info, &v);
307 // Initiate DMA Write & set DSTRT
308 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
309 ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
310 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
312 // Wait for DSTRT to Clear
314 ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
315 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
316 } while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
318 // Clear DMA & Check DERR
319 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
320 ejtag_ctrl = ejtag_info->ejtag_ctrl;
321 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
322 if (ejtag_ctrl & EJTAG_CTRL_DERR)
325 printf("DMA Write Addr = %08x Data = ERROR ON WRITE (retrying)\n", addr);
326 goto begin_ejtag_dma_write_b;
327 } else printf("DMA Write Addr = %08x Data = ERROR ON WRITE\n", addr);
328 return ERROR_JTAG_DEVICE_ERROR;
334 int mips32_dmaacc_read_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf)
339 return mips32_dmaacc_read_mem8(ejtag_info, addr, count, (u8*)buf);
341 return mips32_dmaacc_read_mem16(ejtag_info, addr, count, (u16*)buf);
343 return mips32_dmaacc_read_mem32(ejtag_info, addr, count, (u32*)buf);
349 int mips32_dmaacc_read_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32 *buf)
354 for(i=0; i<count; i++) {
355 if((retval=ejtag_dma_read(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK)
362 int mips32_dmaacc_read_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 *buf)
367 for(i=0; i<count; i++) {
368 if((retval=ejtag_dma_read_h(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK)
375 int mips32_dmaacc_read_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, u8 *buf)
380 for(i=0; i<count; i++) {
381 if((retval=ejtag_dma_read_b(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK)
388 int mips32_dmaacc_write_mem(mips_ejtag_t *ejtag_info, u32 addr, int size, int count, void *buf)
393 return mips32_dmaacc_write_mem8(ejtag_info, addr, count, (u8*)buf);
395 return mips32_dmaacc_write_mem16(ejtag_info, addr, count,(u16*)buf);
397 return mips32_dmaacc_write_mem32(ejtag_info, addr, count, (u32*)buf);
403 int mips32_dmaacc_write_mem32(mips_ejtag_t *ejtag_info, u32 addr, int count, u32 *buf)
408 for(i=0; i<count; i++) {
409 if((retval=ejtag_dma_write(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK)
416 int mips32_dmaacc_write_mem16(mips_ejtag_t *ejtag_info, u32 addr, int count, u16 *buf)
421 for(i=0; i<count; i++) {
422 if((retval=ejtag_dma_write_h(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK)
429 int mips32_dmaacc_write_mem8(mips_ejtag_t *ejtag_info, u32 addr, int count, u8 *buf)
434 for(i=0; i<count; i++) {
435 if((retval=ejtag_dma_write_b(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK)