git.sur5r.net Git - openocd/blob - src/target/mips32_pracc.h

   1 /***************************************************************************
   2  *   Copyright (C) 2008 by Spencer Oliver                                  *
   3  *   spen@spen-soft.co.uk                                                  *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by David T.L. Wong                                 *
   6  *                                                                         *
   7  *   Copyright (C) 2011 by Drasko DRASKOVIC                                *
   8  *   drasko.draskovic@gmail.com                                            *
   9  *                                                                         *
  10  *   This program is free software; you can redistribute it and/or modify  *
  11  *   it under the terms of the GNU General Public License as published by  *
  12  *   the Free Software Foundation; either version 2 of the License, or     *
  13  *   (at your option) any later version.                                   *
  14  *                                                                         *
  15  *   This program is distributed in the hope that it will be useful,       *
  16  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  17  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  18  *   GNU General Public License for more details.                          *
  19  *                                                                         *
  20  *   You should have received a copy of the GNU General Public License     *
  21  *   along with this program; if not, write to the                         *
  22  *   Free Software Foundation, Inc.,                                       *
  23  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  24  ***************************************************************************/
  25 #ifndef MIPS32_PRACC_H
  26 #define MIPS32_PRACC_H
  27
  28 #include <target/mips32.h>
  29 #include <target/mips_ejtag.h>
  30
  31 #define MIPS32_PRACC_FASTDATA_AREA              0xFF200000
  32 #define MIPS32_PRACC_FASTDATA_SIZE              16
  33 #define MIPS32_PRACC_TEXT                               0xFF200200
  34 #define MIPS32_PRACC_STACK                              0xFF204000
  35 #define MIPS32_PRACC_PARAM_IN                   0xFF201000
  36 #define MIPS32_PRACC_PARAM_IN_SIZE              0x1000
  37 #define MIPS32_PRACC_PARAM_OUT                  (MIPS32_PRACC_PARAM_IN + MIPS32_PRACC_PARAM_IN_SIZE)
  38 #define MIPS32_PRACC_PARAM_OUT_SIZE             0x1000
  39
  40 #define MIPS32_FASTDATA_HANDLER_SIZE    0x80
  41 #define UPPER16(uint32_t)                               (uint32_t >> 16)
  42 #define LOWER16(uint32_t)                               (uint32_t & 0xFFFF)
  43 #define NEG16(v)                                                (((~(v)) + 1) & 0xFFFF)
  44 /*#define NEG18(v) (((~(v)) + 1) & 0x3FFFF)*/
  45
  46 int mips32_pracc_read_mem(struct mips_ejtag *ejtag_info,
  47                 uint32_t addr, int size, int count, void *buf);
  48 int mips32_pracc_write_mem(struct mips_ejtag *ejtag_info,
  49                 uint32_t addr, int size, int count, void *buf);
  50 int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_area *source,
  51                 int write_t, uint32_t addr, int count, uint32_t *buf);
  52
  53 int mips32_pracc_read_regs(struct mips_ejtag *ejtag_info, uint32_t *regs);
  54 int mips32_pracc_write_regs(struct mips_ejtag *ejtag_info, uint32_t *regs);
  55
  56 int mips32_pracc_exec(struct mips_ejtag *ejtag_info, int code_len, const uint32_t *code,
  57                 int num_param_in, uint32_t *param_in,
  58                 int num_param_out, uint32_t *param_out, int cycle);
  59
  60 /**
  61  * \b mips32_cp0_read
  62  *
  63  * Simulates mfc0 ASM instruction (Move From C0),
  64  * i.e. implements copro C0 Register read.
  65  *
  66  * @param[in] ejtag_info
  67  * @param[in] val Storage to hold read value
  68  * @param[in] cp0_reg Number of copro C0 register we want to read
  69  * @param[in] cp0_sel Select for the given C0 register
  70  *
  71  * @return ERROR_OK on Sucess, ERROR_FAIL otherwise
  72  */
  73 int mips32_cp0_read(struct mips_ejtag *ejtag_info,
  74                                                                 uint32_t *val, uint32_t cp0_reg, uint32_t cp0_sel);
  75
  76 /**
  77  * \b mips32_cp0_write
  78  *
  79  * Simulates mtc0 ASM instruction (Move To C0),
  80  * i.e. implements copro C0 Register read.
  81  *
  82  * @param[in] ejtag_info
  83  * @param[in] val Value to be written
  84  * @param[in] cp0_reg Number of copro C0 register we want to write to
  85  * @param[in] cp0_sel Select for the given C0 register
  86  *
  87  * @return ERROR_OK on Sucess, ERROR_FAIL otherwise
  88  */
  89 int mips32_cp0_write(struct mips_ejtag *ejtag_info,
  90                                                                                         uint32_t val, uint32_t cp0_reg, uint32_t cp0_sel);
  91
  92 #endif