1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
5 * Copyright (C) 2008 by David T.L. Wong *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
28 #include "mips32_dmaacc.h"
33 /* forward declarations */
34 int mips_m4k_poll(target_t *target);
35 int mips_m4k_halt(struct target_s *target);
36 int mips_m4k_soft_reset_halt(struct target_s *target);
37 int mips_m4k_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution);
38 int mips_m4k_step(struct target_s *target, int current, u32 address, int handle_breakpoints);
39 int mips_m4k_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
40 int mips_m4k_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
41 int mips_m4k_register_commands(struct command_context_s *cmd_ctx);
42 int mips_m4k_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
43 int mips_m4k_quit(void);
44 int mips_m4k_target_create(struct target_s *target, Jim_Interp *interp);
46 int mips_m4k_examine(struct target_s *target);
47 int mips_m4k_assert_reset(target_t *target);
48 int mips_m4k_deassert_reset(target_t *target);
49 int mips_m4k_checksum_memory(target_t *target, u32 address, u32 size, u32 *checksum);
51 target_type_t mips_m4k_target =
55 .poll = mips_m4k_poll,
56 .arch_state = mips32_arch_state,
58 .target_request_data = NULL,
60 .halt = mips_m4k_halt,
61 .resume = mips_m4k_resume,
62 .step = mips_m4k_step,
64 .assert_reset = mips_m4k_assert_reset,
65 .deassert_reset = mips_m4k_deassert_reset,
66 .soft_reset_halt = mips_m4k_soft_reset_halt,
68 .get_gdb_reg_list = mips32_get_gdb_reg_list,
70 .read_memory = mips_m4k_read_memory,
71 .write_memory = mips_m4k_write_memory,
72 .bulk_write_memory = mips_m4k_bulk_write_memory,
73 .checksum_memory = mips_m4k_checksum_memory,
74 .blank_check_memory = NULL,
76 .run_algorithm = mips32_run_algorithm,
78 .add_breakpoint = mips_m4k_add_breakpoint,
79 .remove_breakpoint = mips_m4k_remove_breakpoint,
80 .add_watchpoint = mips_m4k_add_watchpoint,
81 .remove_watchpoint = mips_m4k_remove_watchpoint,
83 .register_commands = mips_m4k_register_commands,
84 .target_create = mips_m4k_target_create,
85 .init_target = mips_m4k_init_target,
86 .examine = mips_m4k_examine,
90 int mips_m4k_examine_debug_reason(target_t *target)
95 if ((target->debug_reason != DBG_REASON_DBGRQ)
96 && (target->debug_reason != DBG_REASON_SINGLESTEP))
98 /* get info about inst breakpoint support */
99 if ((retval = target_read_u32(target, EJTAG_IBS, &break_status)) != ERROR_OK)
101 if (break_status & 0x1f)
103 /* we have halted on a breakpoint */
104 if ((retval = target_write_u32(target, EJTAG_IBS, 0)) != ERROR_OK)
106 target->debug_reason = DBG_REASON_BREAKPOINT;
109 /* get info about data breakpoint support */
110 if ((retval = target_read_u32(target, 0xFF302000, &break_status)) != ERROR_OK)
112 if (break_status & 0x1f)
114 /* we have halted on a breakpoint */
115 if ((retval = target_write_u32(target, 0xFF302000, 0)) != ERROR_OK)
117 target->debug_reason = DBG_REASON_WATCHPOINT;
124 int mips_m4k_debug_entry(target_t *target)
126 mips32_common_t *mips32 = target->arch_info;
127 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
130 /* read debug register */
131 mips_ejtag_read_debug(ejtag_info, &debug_reg);
133 /* make sure break uit configured */
134 mips32_configure_break_unit(target);
136 /* attempt to find halt reason */
137 mips_m4k_examine_debug_reason(target);
139 /* clear single step if active */
140 if (debug_reg & EJTAG_DEBUG_DSS)
142 /* stopped due to single step - clear step bit */
143 mips_ejtag_config_step(ejtag_info, 0);
146 mips32_save_context(target);
148 LOG_DEBUG("entered debug state at PC 0x%x, target->state: %s",
149 *(u32*)(mips32->core_cache->reg_list[MIPS32_PC].value),
150 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
155 int mips_m4k_poll(target_t *target)
158 mips32_common_t *mips32 = target->arch_info;
159 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
160 u32 ejtag_ctrl = ejtag_info->ejtag_ctrl;
162 /* read ejtag control reg */
163 jtag_add_end_state(TAP_IDLE);
164 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
165 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
167 /* clear this bit before handling polling
168 * as after reset registers will read zero */
169 if (ejtag_ctrl & EJTAG_CTRL_ROCC)
171 /* we have detected a reset, clear flag
172 * otherwise ejtag will not work */
173 jtag_add_end_state(TAP_IDLE);
174 ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
176 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
177 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
178 LOG_DEBUG("Reset Detected");
181 /* check for processor halted */
182 if (ejtag_ctrl & EJTAG_CTRL_BRKST)
184 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
186 jtag_add_end_state(TAP_IDLE);
187 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
189 target->state = TARGET_HALTED;
191 if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK)
194 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
196 else if (target->state == TARGET_DEBUG_RUNNING)
198 target->state = TARGET_HALTED;
200 if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK)
203 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
208 target->state = TARGET_RUNNING;
211 // LOG_DEBUG("ctrl=0x%08X", ejtag_ctrl);
216 int mips_m4k_halt(struct target_s *target)
218 mips32_common_t *mips32 = target->arch_info;
219 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
221 LOG_DEBUG("target->state: %s",
222 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
224 if (target->state == TARGET_HALTED)
226 LOG_DEBUG("target was already halted");
230 if (target->state == TARGET_UNKNOWN)
232 LOG_WARNING("target was in unknown state when halt was requested");
235 if (target->state == TARGET_RESET)
237 if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst)
239 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
240 return ERROR_TARGET_FAILURE;
244 /* we came here in a reset_halt or reset_init sequence
245 * debug entry was already prepared in mips32_prepare_reset_halt()
247 target->debug_reason = DBG_REASON_DBGRQ;
253 /* break processor */
254 mips_ejtag_enter_debug(ejtag_info);
256 target->debug_reason = DBG_REASON_DBGRQ;
261 int mips_m4k_assert_reset(target_t *target)
263 mips32_common_t *mips32 = target->arch_info;
264 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
266 LOG_DEBUG("target->state: %s",
267 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
269 if (!(jtag_reset_config & RESET_HAS_SRST))
271 LOG_ERROR("Can't assert SRST");
275 if (target->reset_halt)
277 /* use hardware to catch reset */
278 jtag_add_end_state(TAP_IDLE);
279 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT, NULL);
283 jtag_add_end_state(TAP_IDLE);
284 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
287 if (strcmp(target->variant, "ejtag_srst") == 0)
289 u32 ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
290 LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
291 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
292 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
296 /* here we should issue a srst only, but we may have to assert trst as well */
297 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
299 jtag_add_reset(1, 1);
303 jtag_add_reset(0, 1);
307 target->state = TARGET_RESET;
308 jtag_add_sleep(50000);
310 mips32_invalidate_core_regs(target);
312 if (target->reset_halt)
315 if ((retval = target_halt(target))!=ERROR_OK)
322 int mips_m4k_deassert_reset(target_t *target)
324 LOG_DEBUG("target->state: %s",
325 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
327 /* deassert reset lines */
328 jtag_add_reset(0, 0);
333 int mips_m4k_soft_reset_halt(struct target_s *target)
339 int mips_m4k_single_step_core(target_t *target)
341 mips32_common_t *mips32 = target->arch_info;
342 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
344 /* configure single step mode */
345 mips_ejtag_config_step(ejtag_info, 1);
347 /* disable interrupts while stepping */
348 mips32_enable_interrupts(target, 0);
350 /* exit debug mode */
351 mips_ejtag_exit_debug(ejtag_info);
353 mips_m4k_debug_entry(target);
358 int mips_m4k_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
360 mips32_common_t *mips32 = target->arch_info;
361 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
362 breakpoint_t *breakpoint = NULL;
365 if (target->state != TARGET_HALTED)
367 LOG_WARNING("target not halted");
368 return ERROR_TARGET_NOT_HALTED;
371 if (!debug_execution)
373 target_free_all_working_areas(target);
374 mips_m4k_enable_breakpoints(target);
375 mips_m4k_enable_watchpoints(target);
378 /* current = 1: continue on current pc, otherwise continue at <address> */
381 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
382 mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
383 mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
386 resume_pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32);
388 mips32_restore_context(target);
390 /* the front-end may request us not to handle breakpoints */
391 if (handle_breakpoints)
393 /* Single step past breakpoint at current address */
394 if ((breakpoint = breakpoint_find(target, resume_pc)))
396 LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
397 mips_m4k_unset_breakpoint(target, breakpoint);
398 mips_m4k_single_step_core(target);
399 mips_m4k_set_breakpoint(target, breakpoint);
403 /* enable interrupts if we are running */
404 mips32_enable_interrupts(target, !debug_execution);
406 /* exit debug mode */
407 mips_ejtag_exit_debug(ejtag_info);
408 target->debug_reason = DBG_REASON_NOTHALTED;
410 /* registers are now invalid */
411 mips32_invalidate_core_regs(target);
413 if (!debug_execution)
415 target->state = TARGET_RUNNING;
416 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
417 LOG_DEBUG("target resumed at 0x%x", resume_pc);
421 target->state = TARGET_DEBUG_RUNNING;
422 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
423 LOG_DEBUG("target debug resumed at 0x%x", resume_pc);
429 int mips_m4k_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
431 /* get pointers to arch-specific information */
432 mips32_common_t *mips32 = target->arch_info;
433 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
434 breakpoint_t *breakpoint = NULL;
436 if (target->state != TARGET_HALTED)
438 LOG_WARNING("target not halted");
439 return ERROR_TARGET_NOT_HALTED;
442 /* current = 1: continue on current pc, otherwise continue at <address> */
444 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
446 /* the front-end may request us not to handle breakpoints */
447 if (handle_breakpoints)
448 if ((breakpoint = breakpoint_find(target, buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32))))
449 mips_m4k_unset_breakpoint(target, breakpoint);
451 /* restore context */
452 mips32_restore_context(target);
454 /* configure single step mode */
455 mips_ejtag_config_step(ejtag_info, 1);
457 target->debug_reason = DBG_REASON_SINGLESTEP;
459 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
461 /* disable interrupts while stepping */
462 mips32_enable_interrupts(target, 0);
464 /* exit debug mode */
465 mips_ejtag_exit_debug(ejtag_info);
467 /* registers are now invalid */
468 mips32_invalidate_core_regs(target);
471 mips_m4k_set_breakpoint(target, breakpoint);
473 LOG_DEBUG("target stepped ");
475 mips_m4k_debug_entry(target);
476 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
481 void mips_m4k_enable_breakpoints(struct target_s *target)
483 breakpoint_t *breakpoint = target->breakpoints;
485 /* set any pending breakpoints */
488 if (breakpoint->set == 0)
489 mips_m4k_set_breakpoint(target, breakpoint);
490 breakpoint = breakpoint->next;
494 int mips_m4k_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
496 mips32_common_t *mips32 = target->arch_info;
497 mips32_comparator_t * comparator_list = mips32->inst_break_list;
502 LOG_WARNING("breakpoint already set");
506 if (breakpoint->type == BKPT_HARD)
510 while(comparator_list[bp_num].used && (bp_num < mips32->num_inst_bpoints))
512 if (bp_num >= mips32->num_inst_bpoints)
514 LOG_DEBUG("ERROR Can not find free FP Comparator");
515 LOG_WARNING("ERROR Can not find free FP Comparator");
518 breakpoint->set = bp_num + 1;
519 comparator_list[bp_num].used = 1;
520 comparator_list[bp_num].bp_value = breakpoint->address;
521 target_write_u32(target, comparator_list[bp_num].reg_address, comparator_list[bp_num].bp_value);
522 target_write_u32(target, comparator_list[bp_num].reg_address + 0x08, 0x00000000);
523 target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 1);
524 LOG_DEBUG("bp_num %i bp_value 0x%x", bp_num, comparator_list[bp_num].bp_value);
526 else if (breakpoint->type == BKPT_SOFT)
528 if (breakpoint->length == 4)
530 u32 verify = 0xffffffff;
532 if((retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK)
536 if ((retval = target_write_u32(target, breakpoint->address, MIPS32_SDBBP)) != ERROR_OK)
541 if ((retval = target_read_u32(target, breakpoint->address, &verify)) != ERROR_OK)
545 if (verify != MIPS32_SDBBP)
547 LOG_ERROR("Unable to set 32bit breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
555 if((retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK)
559 if ((retval = target_write_u16(target, breakpoint->address, MIPS16_SDBBP)) != ERROR_OK)
564 if ((retval = target_read_u16(target, breakpoint->address, &verify)) != ERROR_OK)
568 if (verify != MIPS16_SDBBP)
570 LOG_ERROR("Unable to set 16bit breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
575 breakpoint->set = 20; /* Any nice value but 0 */
581 int mips_m4k_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
583 /* get pointers to arch-specific information */
584 mips32_common_t *mips32 = target->arch_info;
585 mips32_comparator_t * comparator_list = mips32->inst_break_list;
588 if (!breakpoint->set)
590 LOG_WARNING("breakpoint not set");
594 if (breakpoint->type == BKPT_HARD)
596 int bp_num = breakpoint->set - 1;
597 if ((bp_num < 0) || (bp_num >= mips32->num_inst_bpoints))
599 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
602 comparator_list[bp_num].used = 0;
603 comparator_list[bp_num].bp_value = 0;
604 target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 0);
608 /* restore original instruction (kept in target endianness) */
609 if (breakpoint->length == 4)
613 /* check that user program has not modified breakpoint instruction */
614 if ((retval = target_read_memory(target, breakpoint->address, 4, 1, (u8*)¤t_instr)) != ERROR_OK)
618 if (current_instr == MIPS32_SDBBP)
620 if((retval = target_write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
630 /* check that user program has not modified breakpoint instruction */
631 if ((retval = target_read_memory(target, breakpoint->address, 2, 1, (u8*)¤t_instr)) != ERROR_OK)
636 if (current_instr == MIPS16_SDBBP)
638 if((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
650 int mips_m4k_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
652 mips32_common_t *mips32 = target->arch_info;
654 if (breakpoint->type == BKPT_HARD)
656 if (mips32->num_inst_bpoints_avail < 1)
658 LOG_INFO("no hardware breakpoint available");
659 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
662 mips32->num_inst_bpoints_avail--;
665 mips_m4k_set_breakpoint(target, breakpoint);
670 int mips_m4k_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
672 /* get pointers to arch-specific information */
673 mips32_common_t *mips32 = target->arch_info;
675 if (target->state != TARGET_HALTED)
677 LOG_WARNING("target not halted");
678 return ERROR_TARGET_NOT_HALTED;
683 mips_m4k_unset_breakpoint(target, breakpoint);
686 if (breakpoint->type == BKPT_HARD)
687 mips32->num_inst_bpoints_avail++;
692 int mips_m4k_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
698 int mips_m4k_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
704 int mips_m4k_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
710 int mips_m4k_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
716 void mips_m4k_enable_watchpoints(struct target_s *target)
718 watchpoint_t *watchpoint = target->watchpoints;
720 /* set any pending watchpoints */
723 if (watchpoint->set == 0)
724 mips_m4k_set_watchpoint(target, watchpoint);
725 watchpoint = watchpoint->next;
729 int mips_m4k_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
731 mips32_common_t *mips32 = target->arch_info;
732 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
734 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
736 if (target->state != TARGET_HALTED)
738 LOG_WARNING("target not halted");
739 return ERROR_TARGET_NOT_HALTED;
742 /* sanitize arguments */
743 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
744 return ERROR_INVALID_ARGUMENTS;
746 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
747 return ERROR_TARGET_UNALIGNED_ACCESS;
754 /* if noDMA off, use DMAACC mode for memory read */
755 if(ejtag_info->impcode & EJTAG_IMP_NODMA)
756 return mips32_pracc_read_mem(ejtag_info, address, size, count, (void *)buffer);
758 return mips32_dmaacc_read_mem(ejtag_info, address, size, count, (void *)buffer);
760 LOG_ERROR("BUG: we shouldn't get here");
768 int mips_m4k_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
770 mips32_common_t *mips32 = target->arch_info;
771 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
773 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
775 if (target->state != TARGET_HALTED)
777 LOG_WARNING("target not halted");
778 return ERROR_TARGET_NOT_HALTED;
781 /* sanitize arguments */
782 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
783 return ERROR_INVALID_ARGUMENTS;
785 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
786 return ERROR_TARGET_UNALIGNED_ACCESS;
793 /* if noDMA off, use DMAACC mode for memory write */
794 if(ejtag_info->impcode & EJTAG_IMP_NODMA)
795 mips32_pracc_write_mem(ejtag_info, address, size, count, (void *)buffer);
797 mips32_dmaacc_write_mem(ejtag_info, address, size, count, (void *)buffer);
800 LOG_ERROR("BUG: we shouldn't get here");
808 int mips_m4k_register_commands(struct command_context_s *cmd_ctx)
812 retval = mips32_register_commands(cmd_ctx);
816 int mips_m4k_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
818 mips32_build_reg_cache(target);
823 int mips_m4k_quit(void)
828 int mips_m4k_init_arch_info(target_t *target, mips_m4k_common_t *mips_m4k, jtag_tap_t *tap)
830 mips32_common_t *mips32 = &mips_m4k->mips32_common;
832 mips_m4k->common_magic = MIPSM4K_COMMON_MAGIC;
834 /* initialize mips4k specific info */
835 mips32_init_arch_info(target, mips32, tap);
836 mips32->arch_info = mips_m4k;
841 int mips_m4k_target_create(struct target_s *target, Jim_Interp *interp)
843 mips_m4k_common_t *mips_m4k = calloc(1,sizeof(mips_m4k_common_t));
845 mips_m4k_init_arch_info(target, mips_m4k, target->tap);
850 int mips_m4k_examine(struct target_s *target)
853 mips32_common_t *mips32 = target->arch_info;
854 mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
857 if (!target_was_examined(target))
859 mips_ejtag_get_idcode(ejtag_info, &idcode, NULL);
860 ejtag_info->idcode = idcode;
862 if (((idcode >> 1) & 0x7FF) == 0x29)
864 /* we are using a pic32mx so select ejtag port
865 * as it is not selected by default */
866 mips_ejtag_set_instr(ejtag_info, 0x05, NULL);
867 LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
871 /* init rest of ejtag interface */
872 if ((retval = mips_ejtag_init(ejtag_info)) != ERROR_OK)
875 if ((retval = mips32_examine(target)) != ERROR_OK)
881 int mips_m4k_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
883 return mips_m4k_write_memory(target, address, 4, count, buffer);
886 int mips_m4k_checksum_memory(target_t *target, u32 address, u32 size, u32 *checksum)
888 return ERROR_FAIL; /* use bulk read method */