git.sur5r.net Git - openocd/blob - src/target/mips_m4k.c

   1 /***************************************************************************
   2  *   Copyright (C) 2008 by Spencer Oliver                                  *
   3  *   spen@spen-soft.co.uk                                                  *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by David T.L. Wong                                 *
   6  *                                                                         *
   7  *   Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com>          *
   8  *                                                                         *
   9  *   Copyright (C) 2011 by Drasko DRASKOVIC                                *
  10  *   drasko.draskovic@gmail.com                                            *
  11  *                                                                         *
  12  *   This program is free software; you can redistribute it and/or modify  *
  13  *   it under the terms of the GNU General Public License as published by  *
  14  *   the Free Software Foundation; either version 2 of the License, or     *
  15  *   (at your option) any later version.                                   *
  16  *                                                                         *
  17  *   This program is distributed in the hope that it will be useful,       *
  18  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  19  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  20  *   GNU General Public License for more details.                          *
  21  *                                                                         *
  22  *   You should have received a copy of the GNU General Public License     *
  23  *   along with this program; if not, write to the                         *
  24  *   Free Software Foundation, Inc.,                                       *
  25  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  26  ***************************************************************************/
  27
  28 #ifdef HAVE_CONFIG_H
  29 #include "config.h"
  30 #endif
  31
  32 #include "breakpoints.h"
  33 #include "mips32.h"
  34 #include "mips_m4k.h"
  35 #include "mips32_dmaacc.h"
  36 #include "target_type.h"
  37 #include "register.h"
  38
  39 static void mips_m4k_enable_breakpoints(struct target *target);
  40 static void mips_m4k_enable_watchpoints(struct target *target);
  41 static int mips_m4k_set_breakpoint(struct target *target,
  42                 struct breakpoint *breakpoint);
  43 static int mips_m4k_unset_breakpoint(struct target *target,
  44                 struct breakpoint *breakpoint);
  45 static int mips_m4k_internal_restore(struct target *target, int current,
  46                 uint32_t address, int handle_breakpoints,
  47                 int debug_execution);
  48 static int mips_m4k_halt(struct target *target);
  49 static int mips_m4k_bulk_write_memory(struct target *target, uint32_t address,
  50                 uint32_t count, const uint8_t *buffer);
  51
  52 static int mips_m4k_examine_debug_reason(struct target *target)
  53 {
  54         struct mips32_common *mips32 = target_to_mips32(target);
  55         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  56         uint32_t break_status;
  57         int retval;
  58
  59         if ((target->debug_reason != DBG_REASON_DBGRQ)
  60                 && (target->debug_reason != DBG_REASON_SINGLESTEP)) {
  61                 /* get info about inst breakpoint support */
  62                 retval = target_read_u32(target,
  63                         ejtag_info->ejtag_ibs_addr, &break_status);
  64                 if (retval != ERROR_OK)
  65                         return retval;
  66                 if (break_status & 0x1f) {
  67                         /* we have halted on a  breakpoint */
  68                         retval = target_write_u32(target,
  69                                 ejtag_info->ejtag_ibs_addr, 0);
  70                         if (retval != ERROR_OK)
  71                                 return retval;
  72                         target->debug_reason = DBG_REASON_BREAKPOINT;
  73                 }
  74
  75                 /* get info about data breakpoint support */
  76                 retval = target_read_u32(target,
  77                         ejtag_info->ejtag_dbs_addr, &break_status);
  78                 if (retval != ERROR_OK)
  79                         return retval;
  80                 if (break_status & 0x1f) {
  81                         /* we have halted on a  breakpoint */
  82                         retval = target_write_u32(target,
  83                                 ejtag_info->ejtag_dbs_addr, 0);
  84                         if (retval != ERROR_OK)
  85                                 return retval;
  86                         target->debug_reason = DBG_REASON_WATCHPOINT;
  87                 }
  88         }
  89
  90         return ERROR_OK;
  91 }
  92
  93 static int mips_m4k_debug_entry(struct target *target)
  94 {
  95         struct mips32_common *mips32 = target_to_mips32(target);
  96         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  97
  98         mips32_save_context(target);
  99
 100         /* make sure stepping disabled, SSt bit in CP0 debug register cleared */
 101         mips_ejtag_config_step(ejtag_info, 0);
 102
 103         /* make sure break unit configured */
 104         mips32_configure_break_unit(target);
 105
 106         /* attempt to find halt reason */
 107         mips_m4k_examine_debug_reason(target);
 108
 109         /* default to mips32 isa, it will be changed below if required */
 110         mips32->isa_mode = MIPS32_ISA_MIPS32;
 111
 112         if (ejtag_info->impcode & EJTAG_IMP_MIPS16)
 113                 mips32->isa_mode = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 1);
 114
 115         LOG_DEBUG("entered debug state at PC 0x%" PRIx32 ", target->state: %s",
 116                         buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32),
 117                         target_state_name(target));
 118
 119         return ERROR_OK;
 120 }
 121
 122 static struct target *get_mips_m4k(struct target *target, int32_t coreid)
 123 {
 124         struct target_list *head;
 125         struct target *curr;
 126
 127         head = target->head;
 128         while (head != (struct target_list *)NULL) {
 129                 curr = head->target;
 130                 if ((curr->coreid == coreid) && (curr->state == TARGET_HALTED))
 131                         return curr;
 132                 head = head->next;
 133         }
 134         return target;
 135 }
 136
 137 static int mips_m4k_halt_smp(struct target *target)
 138 {
 139         int retval = ERROR_OK;
 140         struct target_list *head;
 141         struct target *curr;
 142         head = target->head;
 143         while (head != (struct target_list *)NULL) {
 144                 int ret = ERROR_OK;
 145                 curr = head->target;
 146                 if ((curr != target) && (curr->state != TARGET_HALTED))
 147                         ret = mips_m4k_halt(curr);
 148
 149                 if (ret != ERROR_OK) {
 150                         LOG_ERROR("halt failed target->coreid: %d", curr->coreid);
 151                         retval = ret;
 152                 }
 153                 head = head->next;
 154         }
 155         return retval;
 156 }
 157
 158 static int update_halt_gdb(struct target *target)
 159 {
 160         int retval = ERROR_OK;
 161         if (target->gdb_service->core[0] == -1) {
 162                 target->gdb_service->target = target;
 163                 target->gdb_service->core[0] = target->coreid;
 164                 retval = mips_m4k_halt_smp(target);
 165         }
 166         return retval;
 167 }
 168
 169 static int mips_m4k_poll(struct target *target)
 170 {
 171         int retval = ERROR_OK;
 172         struct mips32_common *mips32 = target_to_mips32(target);
 173         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 174         uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl;
 175         enum target_state prev_target_state = target->state;
 176
 177         /*  toggle to another core is done by gdb as follow */
 178         /*  maint packet J core_id */
 179         /*  continue */
 180         /*  the next polling trigger an halt event sent to gdb */
 181         if ((target->state == TARGET_HALTED) && (target->smp) &&
 182                 (target->gdb_service) &&
 183                 (target->gdb_service->target == NULL)) {
 184                 target->gdb_service->target =
 185                         get_mips_m4k(target, target->gdb_service->core[1]);
 186                 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 187                 return retval;
 188         }
 189
 190         /* read ejtag control reg */
 191         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 192         retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 193         if (retval != ERROR_OK)
 194                 return retval;
 195
 196         /* clear this bit before handling polling
 197          * as after reset registers will read zero */
 198         if (ejtag_ctrl & EJTAG_CTRL_ROCC) {
 199                 /* we have detected a reset, clear flag
 200                  * otherwise ejtag will not work */
 201                 ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
 202
 203                 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 204                 retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 205                 if (retval != ERROR_OK)
 206                         return retval;
 207                 LOG_DEBUG("Reset Detected");
 208         }
 209
 210         /* check for processor halted */
 211         if (ejtag_ctrl & EJTAG_CTRL_BRKST) {
 212                 if ((target->state != TARGET_HALTED)
 213                     && (target->state != TARGET_DEBUG_RUNNING)) {
 214                         if (target->state == TARGET_UNKNOWN)
 215                                 LOG_DEBUG("EJTAG_CTRL_BRKST already set during server startup.");
 216
 217                         /* OpenOCD was was probably started on the board with EJTAG_CTRL_BRKST already set
 218                          * (maybe put on by HALT-ing the board in the previous session).
 219                          *
 220                          * Force enable debug entry for this session.
 221                          */
 222                         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT);
 223                         target->state = TARGET_HALTED;
 224                         retval = mips_m4k_debug_entry(target);
 225                         if (retval != ERROR_OK)
 226                                 return retval;
 227
 228                         if (target->smp &&
 229                                 ((prev_target_state == TARGET_RUNNING)
 230                              || (prev_target_state == TARGET_RESET))) {
 231                                 retval = update_halt_gdb(target);
 232                                 if (retval != ERROR_OK)
 233                                         return retval;
 234                         }
 235                         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 236                 } else if (target->state == TARGET_DEBUG_RUNNING) {
 237                         target->state = TARGET_HALTED;
 238
 239                         retval = mips_m4k_debug_entry(target);
 240                         if (retval != ERROR_OK)
 241                                 return retval;
 242
 243                         if (target->smp) {
 244                                 retval = update_halt_gdb(target);
 245                                 if (retval != ERROR_OK)
 246                                         return retval;
 247                         }
 248
 249                         target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
 250                 }
 251         } else
 252                 target->state = TARGET_RUNNING;
 253
 254 /*      LOG_DEBUG("ctrl = 0x%08X", ejtag_ctrl); */
 255
 256         return ERROR_OK;
 257 }
 258
 259 static int mips_m4k_halt(struct target *target)
 260 {
 261         struct mips32_common *mips32 = target_to_mips32(target);
 262         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 263
 264         LOG_DEBUG("target->state: %s", target_state_name(target));
 265
 266         if (target->state == TARGET_HALTED) {
 267                 LOG_DEBUG("target was already halted");
 268                 return ERROR_OK;
 269         }
 270
 271         if (target->state == TARGET_UNKNOWN)
 272                 LOG_WARNING("target was in unknown state when halt was requested");
 273
 274         if (target->state == TARGET_RESET) {
 275                 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
 276                         LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
 277                         return ERROR_TARGET_FAILURE;
 278                 } else {
 279                         /* we came here in a reset_halt or reset_init sequence
 280                          * debug entry was already prepared in mips_m4k_assert_reset()
 281                          */
 282                         target->debug_reason = DBG_REASON_DBGRQ;
 283
 284                         return ERROR_OK;
 285                 }
 286         }
 287
 288         /* break processor */
 289         mips_ejtag_enter_debug(ejtag_info);
 290
 291         target->debug_reason = DBG_REASON_DBGRQ;
 292
 293         return ERROR_OK;
 294 }
 295
 296 static int mips_m4k_assert_reset(struct target *target)
 297 {
 298         struct mips_m4k_common *mips_m4k = target_to_m4k(target);
 299         struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
 300
 301         LOG_DEBUG("target->state: %s",
 302                 target_state_name(target));
 303
 304         enum reset_types jtag_reset_config = jtag_get_reset_config();
 305
 306         /* some cores support connecting while srst is asserted
 307          * use that mode is it has been configured */
 308
 309         bool srst_asserted = false;
 310
 311         if (!(jtag_reset_config & RESET_SRST_PULLS_TRST) &&
 312                         (jtag_reset_config & RESET_SRST_NO_GATING)) {
 313                 jtag_add_reset(0, 1);
 314                 srst_asserted = true;
 315         }
 316
 317         if (target->reset_halt) {
 318                 /* use hardware to catch reset */
 319                 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT);
 320         } else
 321                 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT);
 322
 323         if (jtag_reset_config & RESET_HAS_SRST) {
 324                 /* here we should issue a srst only, but we may have to assert trst as well */
 325                 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
 326                         jtag_add_reset(1, 1);
 327                 else if (!srst_asserted)
 328                         jtag_add_reset(0, 1);
 329         } else {
 330                 if (mips_m4k->is_pic32mx) {
 331                         LOG_DEBUG("Using MTAP reset to reset processor...");
 332
 333                         /* use microchip specific MTAP reset */
 334                         mips_ejtag_set_instr(ejtag_info, MTAP_SW_MTAP);
 335                         mips_ejtag_set_instr(ejtag_info, MTAP_COMMAND);
 336
 337                         mips_ejtag_drscan_8_out(ejtag_info, MCHP_ASERT_RST);
 338                         mips_ejtag_drscan_8_out(ejtag_info, MCHP_DE_ASSERT_RST);
 339                         mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
 340                 } else {
 341                         /* use ejtag reset - not supported by all cores */
 342                         uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
 343                         LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
 344                         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 345                         mips_ejtag_drscan_32_out(ejtag_info, ejtag_ctrl);
 346                 }
 347         }
 348
 349         target->state = TARGET_RESET;
 350         jtag_add_sleep(50000);
 351
 352         register_cache_invalidate(mips_m4k->mips32.core_cache);
 353
 354         if (target->reset_halt) {
 355                 int retval = target_halt(target);
 356                 if (retval != ERROR_OK)
 357                         return retval;
 358         }
 359
 360         return ERROR_OK;
 361 }
 362
 363 static int mips_m4k_deassert_reset(struct target *target)
 364 {
 365         LOG_DEBUG("target->state: %s", target_state_name(target));
 366
 367         /* deassert reset lines */
 368         jtag_add_reset(0, 0);
 369
 370         return ERROR_OK;
 371 }
 372
 373 static int mips_m4k_soft_reset_halt(struct target *target)
 374 {
 375         /* TODO */
 376         return ERROR_OK;
 377 }
 378
 379 static int mips_m4k_single_step_core(struct target *target)
 380 {
 381         struct mips32_common *mips32 = target_to_mips32(target);
 382         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 383
 384         /* configure single step mode */
 385         mips_ejtag_config_step(ejtag_info, 1);
 386
 387         /* disable interrupts while stepping */
 388         mips32_enable_interrupts(target, 0);
 389
 390         /* exit debug mode */
 391         mips_ejtag_exit_debug(ejtag_info);
 392
 393         mips_m4k_debug_entry(target);
 394
 395         return ERROR_OK;
 396 }
 397
 398 static int mips_m4k_restore_smp(struct target *target, uint32_t address, int handle_breakpoints)
 399 {
 400         int retval = ERROR_OK;
 401         struct target_list *head;
 402         struct target *curr;
 403
 404         head = target->head;
 405         while (head != (struct target_list *)NULL) {
 406                 int ret = ERROR_OK;
 407                 curr = head->target;
 408                 if ((curr != target) && (curr->state != TARGET_RUNNING)) {
 409                         /*  resume current address , not in step mode */
 410                         ret = mips_m4k_internal_restore(curr, 1, address,
 411                                                    handle_breakpoints, 0);
 412
 413                         if (ret != ERROR_OK) {
 414                                 LOG_ERROR("target->coreid :%d failed to resume at address :0x%x",
 415                                                   curr->coreid, address);
 416                                 retval = ret;
 417                         }
 418                 }
 419                 head = head->next;
 420         }
 421         return retval;
 422 }
 423
 424 static int mips_m4k_internal_restore(struct target *target, int current,
 425                 uint32_t address, int handle_breakpoints, int debug_execution)
 426 {
 427         struct mips32_common *mips32 = target_to_mips32(target);
 428         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 429         struct breakpoint *breakpoint = NULL;
 430         uint32_t resume_pc;
 431
 432         if (target->state != TARGET_HALTED) {
 433                 LOG_WARNING("target not halted");
 434                 return ERROR_TARGET_NOT_HALTED;
 435         }
 436
 437         if (!debug_execution) {
 438                 target_free_all_working_areas(target);
 439                 mips_m4k_enable_breakpoints(target);
 440                 mips_m4k_enable_watchpoints(target);
 441         }
 442
 443         /* current = 1: continue on current pc, otherwise continue at <address> */
 444         if (!current) {
 445                 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
 446                 mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
 447                 mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
 448         }
 449
 450         if (ejtag_info->impcode & EJTAG_IMP_MIPS16)
 451                 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 1, mips32->isa_mode);
 452
 453         if (!current)
 454                 resume_pc = address;
 455         else
 456                 resume_pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32);
 457
 458         mips32_restore_context(target);
 459
 460         /* the front-end may request us not to handle breakpoints */
 461         if (handle_breakpoints) {
 462                 /* Single step past breakpoint at current address */
 463                 breakpoint = breakpoint_find(target, resume_pc);
 464                 if (breakpoint) {
 465                         LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
 466                         mips_m4k_unset_breakpoint(target, breakpoint);
 467                         mips_m4k_single_step_core(target);
 468                         mips_m4k_set_breakpoint(target, breakpoint);
 469                 }
 470         }
 471
 472         /* enable interrupts if we are running */
 473         mips32_enable_interrupts(target, !debug_execution);
 474
 475         /* exit debug mode */
 476         mips_ejtag_exit_debug(ejtag_info);
 477         target->debug_reason = DBG_REASON_NOTHALTED;
 478
 479         /* registers are now invalid */
 480         register_cache_invalidate(mips32->core_cache);
 481
 482         if (!debug_execution) {
 483                 target->state = TARGET_RUNNING;
 484                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 485                 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
 486         } else {
 487                 target->state = TARGET_DEBUG_RUNNING;
 488                 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
 489                 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
 490         }
 491
 492         return ERROR_OK;
 493 }
 494
 495 static int mips_m4k_resume(struct target *target, int current,
 496                 uint32_t address, int handle_breakpoints, int debug_execution)
 497 {
 498         int retval = ERROR_OK;
 499
 500         /* dummy resume for smp toggle in order to reduce gdb impact  */
 501         if ((target->smp) && (target->gdb_service->core[1] != -1)) {
 502                 /*   simulate a start and halt of target */
 503                 target->gdb_service->target = NULL;
 504                 target->gdb_service->core[0] = target->gdb_service->core[1];
 505                 /*  fake resume at next poll we play the  target core[1], see poll*/
 506                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 507                 return retval;
 508         }
 509
 510         retval = mips_m4k_internal_restore(target, current, address,
 511                                 handle_breakpoints,
 512                                 debug_execution);
 513
 514         if (retval == ERROR_OK && target->smp) {
 515                 target->gdb_service->core[0] = -1;
 516                 retval = mips_m4k_restore_smp(target, address, handle_breakpoints);
 517         }
 518
 519         return retval;
 520 }
 521
 522 static int mips_m4k_step(struct target *target, int current,
 523                 uint32_t address, int handle_breakpoints)
 524 {
 525         /* get pointers to arch-specific information */
 526         struct mips32_common *mips32 = target_to_mips32(target);
 527         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 528         struct breakpoint *breakpoint = NULL;
 529
 530         if (target->state != TARGET_HALTED) {
 531                 LOG_WARNING("target not halted");
 532                 return ERROR_TARGET_NOT_HALTED;
 533         }
 534
 535         /* current = 1: continue on current pc, otherwise continue at <address> */
 536         if (!current) {
 537                 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
 538                 mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
 539                 mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
 540         }
 541
 542         /* the front-end may request us not to handle breakpoints */
 543         if (handle_breakpoints) {
 544                 breakpoint = breakpoint_find(target,
 545                                 buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32));
 546                 if (breakpoint)
 547                         mips_m4k_unset_breakpoint(target, breakpoint);
 548         }
 549
 550         /* restore context */
 551         mips32_restore_context(target);
 552
 553         /* configure single step mode */
 554         mips_ejtag_config_step(ejtag_info, 1);
 555
 556         target->debug_reason = DBG_REASON_SINGLESTEP;
 557
 558         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 559
 560         /* disable interrupts while stepping */
 561         mips32_enable_interrupts(target, 0);
 562
 563         /* exit debug mode */
 564         mips_ejtag_exit_debug(ejtag_info);
 565
 566         /* registers are now invalid */
 567         register_cache_invalidate(mips32->core_cache);
 568
 569         LOG_DEBUG("target stepped ");
 570         mips_m4k_debug_entry(target);
 571
 572         if (breakpoint)
 573                 mips_m4k_set_breakpoint(target, breakpoint);
 574
 575         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 576
 577         return ERROR_OK;
 578 }
 579
 580 static void mips_m4k_enable_breakpoints(struct target *target)
 581 {
 582         struct breakpoint *breakpoint = target->breakpoints;
 583
 584         /* set any pending breakpoints */
 585         while (breakpoint) {
 586                 if (breakpoint->set == 0)
 587                         mips_m4k_set_breakpoint(target, breakpoint);
 588                 breakpoint = breakpoint->next;
 589         }
 590 }
 591
 592 static int mips_m4k_set_breakpoint(struct target *target,
 593                 struct breakpoint *breakpoint)
 594 {
 595         struct mips32_common *mips32 = target_to_mips32(target);
 596         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 597         struct mips32_comparator *comparator_list = mips32->inst_break_list;
 598         int retval;
 599
 600         if (breakpoint->set) {
 601                 LOG_WARNING("breakpoint already set");
 602                 return ERROR_OK;
 603         }
 604
 605         if (breakpoint->type == BKPT_HARD) {
 606                 int bp_num = 0;
 607
 608                 while (comparator_list[bp_num].used && (bp_num < mips32->num_inst_bpoints))
 609                         bp_num++;
 610                 if (bp_num >= mips32->num_inst_bpoints) {
 611                         LOG_ERROR("Can not find free FP Comparator(bpid: %d)",
 612                                         breakpoint->unique_id);
 613                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 614                 }
 615                 breakpoint->set = bp_num + 1;
 616                 comparator_list[bp_num].used = 1;
 617                 comparator_list[bp_num].bp_value = breakpoint->address;
 618
 619                 /* EJTAG 2.0 uses 30bit IBA. First 2 bits are reserved.
 620                  * Warning: there is no IB ASID registers in 2.0.
 621                  * Do not set it! :) */
 622                 if (ejtag_info->ejtag_version == EJTAG_VERSION_20)
 623                         comparator_list[bp_num].bp_value &= 0xFFFFFFFC;
 624
 625                 target_write_u32(target, comparator_list[bp_num].reg_address,
 626                                 comparator_list[bp_num].bp_value);
 627                 target_write_u32(target, comparator_list[bp_num].reg_address +
 628                                  ejtag_info->ejtag_ibm_offs, 0x00000000);
 629                 target_write_u32(target, comparator_list[bp_num].reg_address +
 630                                  ejtag_info->ejtag_ibc_offs, 1);
 631                 LOG_DEBUG("bpid: %d, bp_num %i bp_value 0x%" PRIx32 "",
 632                                   breakpoint->unique_id,
 633                                   bp_num, comparator_list[bp_num].bp_value);
 634         } else if (breakpoint->type == BKPT_SOFT) {
 635                 LOG_DEBUG("bpid: %d", breakpoint->unique_id);
 636                 if (breakpoint->length == 4) {
 637                         uint32_t verify = 0xffffffff;
 638
 639                         retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1,
 640                                         breakpoint->orig_instr);
 641                         if (retval != ERROR_OK)
 642                                 return retval;
 643                         retval = target_write_u32(target, breakpoint->address, MIPS32_SDBBP);
 644                         if (retval != ERROR_OK)
 645                                 return retval;
 646
 647                         retval = target_read_u32(target, breakpoint->address, &verify);
 648                         if (retval != ERROR_OK)
 649                                 return retval;
 650                         if (verify != MIPS32_SDBBP) {
 651                                 LOG_ERROR("Unable to set 32bit breakpoint at address %08" PRIx32
 652                                                 " - check that memory is read/writable", breakpoint->address);
 653                                 return ERROR_OK;
 654                         }
 655                 } else {
 656                         uint16_t verify = 0xffff;
 657
 658                         retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1,
 659                                         breakpoint->orig_instr);
 660                         if (retval != ERROR_OK)
 661                                 return retval;
 662                         retval = target_write_u16(target, breakpoint->address, MIPS16_SDBBP);
 663                         if (retval != ERROR_OK)
 664                                 return retval;
 665
 666                         retval = target_read_u16(target, breakpoint->address, &verify);
 667                         if (retval != ERROR_OK)
 668                                 return retval;
 669                         if (verify != MIPS16_SDBBP) {
 670                                 LOG_ERROR("Unable to set 16bit breakpoint at address %08" PRIx32
 671                                                 " - check that memory is read/writable", breakpoint->address);
 672                                 return ERROR_OK;
 673                         }
 674                 }
 675
 676                 breakpoint->set = 20; /* Any nice value but 0 */
 677         }
 678
 679         return ERROR_OK;
 680 }
 681
 682 static int mips_m4k_unset_breakpoint(struct target *target,
 683                 struct breakpoint *breakpoint)
 684 {
 685         /* get pointers to arch-specific information */
 686         struct mips32_common *mips32 = target_to_mips32(target);
 687         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 688         struct mips32_comparator *comparator_list = mips32->inst_break_list;
 689         int retval;
 690
 691         if (!breakpoint->set) {
 692                 LOG_WARNING("breakpoint not set");
 693                 return ERROR_OK;
 694         }
 695
 696         if (breakpoint->type == BKPT_HARD) {
 697                 int bp_num = breakpoint->set - 1;
 698                 if ((bp_num < 0) || (bp_num >= mips32->num_inst_bpoints)) {
 699                         LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %d)",
 700                                           breakpoint->unique_id);
 701                         return ERROR_OK;
 702                 }
 703                 LOG_DEBUG("bpid: %d - releasing hw: %d",
 704                                 breakpoint->unique_id,
 705                                 bp_num);
 706                 comparator_list[bp_num].used = 0;
 707                 comparator_list[bp_num].bp_value = 0;
 708                 target_write_u32(target, comparator_list[bp_num].reg_address +
 709                                  ejtag_info->ejtag_ibc_offs, 0);
 710
 711         } else {
 712                 /* restore original instruction (kept in target endianness) */
 713                 LOG_DEBUG("bpid: %d", breakpoint->unique_id);
 714                 if (breakpoint->length == 4) {
 715                         uint32_t current_instr;
 716
 717                         /* check that user program has not modified breakpoint instruction */
 718                         retval = target_read_memory(target, breakpoint->address, 4, 1,
 719                                         (uint8_t *)&current_instr);
 720                         if (retval != ERROR_OK)
 721                                 return retval;
 722
 723                         /**
 724                          * target_read_memory() gets us data in _target_ endianess.
 725                          * If we want to use this data on the host for comparisons with some macros
 726                          * we must first transform it to _host_ endianess using target_buffer_get_u32().
 727                          */
 728                         current_instr = target_buffer_get_u32(target, (uint8_t *)&current_instr);
 729
 730                         if (current_instr == MIPS32_SDBBP) {
 731                                 retval = target_write_memory(target, breakpoint->address, 4, 1,
 732                                                 breakpoint->orig_instr);
 733                                 if (retval != ERROR_OK)
 734                                         return retval;
 735                         }
 736                 } else {
 737                         uint16_t current_instr;
 738
 739                         /* check that user program has not modified breakpoint instruction */
 740                         retval = target_read_memory(target, breakpoint->address, 2, 1,
 741                                         (uint8_t *)&current_instr);
 742                         if (retval != ERROR_OK)
 743                                 return retval;
 744                         current_instr = target_buffer_get_u16(target, (uint8_t *)&current_instr);
 745                         if (current_instr == MIPS16_SDBBP) {
 746                                 retval = target_write_memory(target, breakpoint->address, 2, 1,
 747                                                 breakpoint->orig_instr);
 748                                 if (retval != ERROR_OK)
 749                                         return retval;
 750                         }
 751                 }
 752         }
 753         breakpoint->set = 0;
 754
 755         return ERROR_OK;
 756 }
 757
 758 static int mips_m4k_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
 759 {
 760         struct mips32_common *mips32 = target_to_mips32(target);
 761
 762         if (breakpoint->type == BKPT_HARD) {
 763                 if (mips32->num_inst_bpoints_avail < 1) {
 764                         LOG_INFO("no hardware breakpoint available");
 765                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 766                 }
 767
 768                 mips32->num_inst_bpoints_avail--;
 769         }
 770
 771         return mips_m4k_set_breakpoint(target, breakpoint);
 772 }
 773
 774 static int mips_m4k_remove_breakpoint(struct target *target,
 775                 struct breakpoint *breakpoint)
 776 {
 777         /* get pointers to arch-specific information */
 778         struct mips32_common *mips32 = target_to_mips32(target);
 779
 780         if (target->state != TARGET_HALTED) {
 781                 LOG_WARNING("target not halted");
 782                 return ERROR_TARGET_NOT_HALTED;
 783         }
 784
 785         if (breakpoint->set)
 786                 mips_m4k_unset_breakpoint(target, breakpoint);
 787
 788         if (breakpoint->type == BKPT_HARD)
 789                 mips32->num_inst_bpoints_avail++;
 790
 791         return ERROR_OK;
 792 }
 793
 794 static int mips_m4k_set_watchpoint(struct target *target,
 795                 struct watchpoint *watchpoint)
 796 {
 797         struct mips32_common *mips32 = target_to_mips32(target);
 798         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 799         struct mips32_comparator *comparator_list = mips32->data_break_list;
 800         int wp_num = 0;
 801         /*
 802          * watchpoint enabled, ignore all byte lanes in value register
 803          * and exclude both load and store accesses from  watchpoint
 804          * condition evaluation
 805         */
 806         int enable = EJTAG_DBCn_NOSB | EJTAG_DBCn_NOLB | EJTAG_DBCn_BE |
 807                         (0xff << EJTAG_DBCn_BLM_SHIFT);
 808
 809         if (watchpoint->set) {
 810                 LOG_WARNING("watchpoint already set");
 811                 return ERROR_OK;
 812         }
 813
 814         while (comparator_list[wp_num].used && (wp_num < mips32->num_data_bpoints))
 815                 wp_num++;
 816         if (wp_num >= mips32->num_data_bpoints) {
 817                 LOG_ERROR("Can not find free FP Comparator");
 818                 return ERROR_FAIL;
 819         }
 820
 821         if (watchpoint->length != 4) {
 822                 LOG_ERROR("Only watchpoints of length 4 are supported");
 823                 return ERROR_TARGET_UNALIGNED_ACCESS;
 824         }
 825
 826         if (watchpoint->address % 4) {
 827                 LOG_ERROR("Watchpoints address should be word aligned");
 828                 return ERROR_TARGET_UNALIGNED_ACCESS;
 829         }
 830
 831         switch (watchpoint->rw) {
 832                 case WPT_READ:
 833                         enable &= ~EJTAG_DBCn_NOLB;
 834                         break;
 835                 case WPT_WRITE:
 836                         enable &= ~EJTAG_DBCn_NOSB;
 837                         break;
 838                 case WPT_ACCESS:
 839                         enable &= ~(EJTAG_DBCn_NOLB | EJTAG_DBCn_NOSB);
 840                         break;
 841                 default:
 842                         LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
 843         }
 844
 845         watchpoint->set = wp_num + 1;
 846         comparator_list[wp_num].used = 1;
 847         comparator_list[wp_num].bp_value = watchpoint->address;
 848
 849         /* EJTAG 2.0 uses 29bit DBA. First 3 bits are reserved.
 850          * There is as well no ASID register support. */
 851         if (ejtag_info->ejtag_version == EJTAG_VERSION_20)
 852                 comparator_list[wp_num].bp_value &= 0xFFFFFFF8;
 853         else
 854                 target_write_u32(target, comparator_list[wp_num].reg_address +
 855                          ejtag_info->ejtag_dbasid_offs, 0x00000000);
 856
 857         target_write_u32(target, comparator_list[wp_num].reg_address,
 858                          comparator_list[wp_num].bp_value);
 859         target_write_u32(target, comparator_list[wp_num].reg_address +
 860                          ejtag_info->ejtag_dbm_offs, 0x00000000);
 861
 862         target_write_u32(target, comparator_list[wp_num].reg_address +
 863                          ejtag_info->ejtag_dbc_offs, enable);
 864         /* TODO: probably this value is ignored on 2.0 */
 865         target_write_u32(target, comparator_list[wp_num].reg_address +
 866                          ejtag_info->ejtag_dbv_offs, 0);
 867         LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32 "", wp_num, comparator_list[wp_num].bp_value);
 868
 869         return ERROR_OK;
 870 }
 871
 872 static int mips_m4k_unset_watchpoint(struct target *target,
 873                 struct watchpoint *watchpoint)
 874 {
 875         /* get pointers to arch-specific information */
 876         struct mips32_common *mips32 = target_to_mips32(target);
 877         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 878         struct mips32_comparator *comparator_list = mips32->data_break_list;
 879
 880         if (!watchpoint->set) {
 881                 LOG_WARNING("watchpoint not set");
 882                 return ERROR_OK;
 883         }
 884
 885         int wp_num = watchpoint->set - 1;
 886         if ((wp_num < 0) || (wp_num >= mips32->num_data_bpoints)) {
 887                 LOG_DEBUG("Invalid FP Comparator number in watchpoint");
 888                 return ERROR_OK;
 889         }
 890         comparator_list[wp_num].used = 0;
 891         comparator_list[wp_num].bp_value = 0;
 892         target_write_u32(target, comparator_list[wp_num].reg_address +
 893                          ejtag_info->ejtag_dbc_offs, 0);
 894         watchpoint->set = 0;
 895
 896         return ERROR_OK;
 897 }
 898
 899 static int mips_m4k_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
 900 {
 901         struct mips32_common *mips32 = target_to_mips32(target);
 902
 903         if (mips32->num_data_bpoints_avail < 1) {
 904                 LOG_INFO("no hardware watchpoints available");
 905                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 906         }
 907
 908         mips32->num_data_bpoints_avail--;
 909
 910         mips_m4k_set_watchpoint(target, watchpoint);
 911         return ERROR_OK;
 912 }
 913
 914 static int mips_m4k_remove_watchpoint(struct target *target,
 915                 struct watchpoint *watchpoint)
 916 {
 917         /* get pointers to arch-specific information */
 918         struct mips32_common *mips32 = target_to_mips32(target);
 919
 920         if (target->state != TARGET_HALTED) {
 921                 LOG_WARNING("target not halted");
 922                 return ERROR_TARGET_NOT_HALTED;
 923         }
 924
 925         if (watchpoint->set)
 926                 mips_m4k_unset_watchpoint(target, watchpoint);
 927
 928         mips32->num_data_bpoints_avail++;
 929
 930         return ERROR_OK;
 931 }
 932
 933 static void mips_m4k_enable_watchpoints(struct target *target)
 934 {
 935         struct watchpoint *watchpoint = target->watchpoints;
 936
 937         /* set any pending watchpoints */
 938         while (watchpoint) {
 939                 if (watchpoint->set == 0)
 940                         mips_m4k_set_watchpoint(target, watchpoint);
 941                 watchpoint = watchpoint->next;
 942         }
 943 }
 944
 945 static int mips_m4k_read_memory(struct target *target, uint32_t address,
 946                 uint32_t size, uint32_t count, uint8_t *buffer)
 947 {
 948         struct mips32_common *mips32 = target_to_mips32(target);
 949         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 950
 951         LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
 952                         address, size, count);
 953
 954         if (target->state != TARGET_HALTED) {
 955                 LOG_WARNING("target not halted");
 956                 return ERROR_TARGET_NOT_HALTED;
 957         }
 958
 959         /* sanitize arguments */
 960         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
 961                 return ERROR_COMMAND_SYNTAX_ERROR;
 962
 963         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
 964                 return ERROR_TARGET_UNALIGNED_ACCESS;
 965
 966         /* since we don't know if buffer is aligned, we allocate new mem that is always aligned */
 967         void *t = NULL;
 968
 969         if (size > 1) {
 970                 t = malloc(count * size * sizeof(uint8_t));
 971                 if (t == NULL) {
 972                         LOG_ERROR("Out of memory");
 973                         return ERROR_FAIL;
 974                 }
 975         } else
 976                 t = buffer;
 977
 978         /* if noDMA off, use DMAACC mode for memory read */
 979         int retval;
 980         if (ejtag_info->impcode & EJTAG_IMP_NODMA)
 981                 retval = mips32_pracc_read_mem(ejtag_info, address, size, count, t);
 982         else
 983                 retval = mips32_dmaacc_read_mem(ejtag_info, address, size, count, t);
 984
 985         /* mips32_..._read_mem with size 4/2 returns uint32_t/uint16_t in host */
 986         /* endianness, but byte array should represent target endianness       */
 987         if (ERROR_OK == retval) {
 988                 switch (size) {
 989                 case 4:
 990                         target_buffer_set_u32_array(target, buffer, count, t);
 991                         break;
 992                 case 2:
 993                         target_buffer_set_u16_array(target, buffer, count, t);
 994                         break;
 995                 }
 996         }
 997
 998         if ((size > 1) && (t != NULL))
 999                 free(t);
1000
1001         return retval;
1002 }
1003
1004 static int mips_m4k_write_memory(struct target *target, uint32_t address,
1005                 uint32_t size, uint32_t count, const uint8_t *buffer)
1006 {
1007         struct mips32_common *mips32 = target_to_mips32(target);
1008         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
1009
1010         LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
1011                         address, size, count);
1012
1013         if (target->state != TARGET_HALTED) {
1014                 LOG_WARNING("target not halted");
1015                 return ERROR_TARGET_NOT_HALTED;
1016         }
1017
1018         if (size == 4 && count > 32) {
1019                 int retval = mips_m4k_bulk_write_memory(target, address, count, buffer);
1020                 if (retval == ERROR_OK)
1021                         return ERROR_OK;
1022                 LOG_WARNING("Falling back to non-bulk write");
1023         }
1024
1025         /* sanitize arguments */
1026         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1027                 return ERROR_COMMAND_SYNTAX_ERROR;
1028
1029         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1030                 return ERROR_TARGET_UNALIGNED_ACCESS;
1031
1032         /** correct endianess if we have word or hword access */
1033         void *t = NULL;
1034         if (size > 1) {
1035                 /* mips32_..._write_mem with size 4/2 requires uint32_t/uint16_t in host */
1036                 /* endianness, but byte array represents target endianness               */
1037                 t = malloc(count * size * sizeof(uint8_t));
1038                 if (t == NULL) {
1039                         LOG_ERROR("Out of memory");
1040                         return ERROR_FAIL;
1041                 }
1042
1043                 switch (size) {
1044                 case 4:
1045                         target_buffer_get_u32_array(target, buffer, count, (uint32_t *)t);
1046                         break;
1047                 case 2:
1048                         target_buffer_get_u16_array(target, buffer, count, (uint16_t *)t);
1049                         break;
1050                 }
1051                 buffer = t;
1052         }
1053
1054         /* if noDMA off, use DMAACC mode for memory write */
1055         int retval;
1056         if (ejtag_info->impcode & EJTAG_IMP_NODMA)
1057                 retval = mips32_pracc_write_mem(ejtag_info, address, size, count, (void *)buffer);
1058         else
1059                 retval = mips32_dmaacc_write_mem(ejtag_info, address, size, count, (void *)buffer);
1060
1061         if (t != NULL)
1062                 free(t);
1063
1064         if (ERROR_OK != retval)
1065                 return retval;
1066
1067         return ERROR_OK;
1068 }
1069
1070 static int mips_m4k_init_target(struct command_context *cmd_ctx,
1071                 struct target *target)
1072 {
1073         mips32_build_reg_cache(target);
1074
1075         return ERROR_OK;
1076 }
1077
1078 static int mips_m4k_init_arch_info(struct target *target,
1079                 struct mips_m4k_common *mips_m4k, struct jtag_tap *tap)
1080 {
1081         struct mips32_common *mips32 = &mips_m4k->mips32;
1082
1083         mips_m4k->common_magic = MIPSM4K_COMMON_MAGIC;
1084
1085         /* initialize mips4k specific info */
1086         mips32_init_arch_info(target, mips32, tap);
1087         mips32->arch_info = mips_m4k;
1088
1089         return ERROR_OK;
1090 }
1091
1092 static int mips_m4k_target_create(struct target *target, Jim_Interp *interp)
1093 {
1094         struct mips_m4k_common *mips_m4k = calloc(1, sizeof(struct mips_m4k_common));
1095
1096         mips_m4k_init_arch_info(target, mips_m4k, target->tap);
1097
1098         return ERROR_OK;
1099 }
1100
1101 static int mips_m4k_examine(struct target *target)
1102 {
1103         int retval;
1104         struct mips_m4k_common *mips_m4k = target_to_m4k(target);
1105         struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
1106         uint32_t idcode = 0;
1107
1108         if (!target_was_examined(target)) {
1109                 retval = mips_ejtag_get_idcode(ejtag_info, &idcode);
1110                 if (retval != ERROR_OK)
1111                         return retval;
1112                 ejtag_info->idcode = idcode;
1113
1114                 if (((idcode >> 1) & 0x7FF) == 0x29) {
1115                         /* we are using a pic32mx so select ejtag port
1116                          * as it is not selected by default */
1117                         mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
1118                         LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
1119                         mips_m4k->is_pic32mx = true;
1120                 }
1121         }
1122
1123         /* init rest of ejtag interface */
1124         retval = mips_ejtag_init(ejtag_info);
1125         if (retval != ERROR_OK)
1126                 return retval;
1127
1128         retval = mips32_examine(target);
1129         if (retval != ERROR_OK)
1130                 return retval;
1131
1132         return ERROR_OK;
1133 }
1134
1135 static int mips_m4k_bulk_write_memory(struct target *target, uint32_t address,
1136                 uint32_t count, const uint8_t *buffer)
1137 {
1138         struct mips32_common *mips32 = target_to_mips32(target);
1139         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
1140         int retval;
1141         int write_t = 1;
1142
1143         LOG_DEBUG("address: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, count);
1144
1145         /* check alignment */
1146         if (address & 0x3u)
1147                 return ERROR_TARGET_UNALIGNED_ACCESS;
1148
1149         if (mips32->fast_data_area == NULL) {
1150                 /* Get memory for block write handler
1151                  * we preserve this area between calls and gain a speed increase
1152                  * of about 3kb/sec when writing flash
1153                  * this will be released/nulled by the system when the target is resumed or reset */
1154                 retval = target_alloc_working_area(target,
1155                                 MIPS32_FASTDATA_HANDLER_SIZE,
1156                                 &mips32->fast_data_area);
1157                 if (retval != ERROR_OK) {
1158                         LOG_ERROR("No working area available");
1159                         return retval;
1160                 }
1161
1162                 /* reset fastadata state so the algo get reloaded */
1163                 ejtag_info->fast_access_save = -1;
1164         }
1165
1166         /* mips32_pracc_fastdata_xfer requires uint32_t in host endianness, */
1167         /* but byte array represents target endianness                      */
1168         uint32_t *t = NULL;
1169         t = malloc(count * sizeof(uint32_t));
1170         if (t == NULL) {
1171                 LOG_ERROR("Out of memory");
1172                 return ERROR_FAIL;
1173         }
1174
1175         target_buffer_get_u32_array(target, buffer, count, t);
1176
1177         retval = mips32_pracc_fastdata_xfer(ejtag_info, mips32->fast_data_area, write_t, address,
1178                         count, t);
1179
1180         if (t != NULL)
1181                 free(t);
1182
1183         if (retval != ERROR_OK)
1184                 LOG_ERROR("Fastdata access Failed");
1185
1186         return retval;
1187 }
1188
1189 static int mips_m4k_verify_pointer(struct command_context *cmd_ctx,
1190                 struct mips_m4k_common *mips_m4k)
1191 {
1192         if (mips_m4k->common_magic != MIPSM4K_COMMON_MAGIC) {
1193                 command_print(cmd_ctx, "target is not an MIPS_M4K");
1194                 return ERROR_TARGET_INVALID;
1195         }
1196         return ERROR_OK;
1197 }
1198
1199 COMMAND_HANDLER(mips_m4k_handle_cp0_command)
1200 {
1201         int retval;
1202         struct target *target = get_current_target(CMD_CTX);
1203         struct mips_m4k_common *mips_m4k = target_to_m4k(target);
1204         struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
1205
1206         retval = mips_m4k_verify_pointer(CMD_CTX, mips_m4k);
1207         if (retval != ERROR_OK)
1208                 return retval;
1209
1210         if (target->state != TARGET_HALTED) {
1211                 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
1212                 return ERROR_OK;
1213         }
1214
1215         /* two or more argument, access a single register/select (write if third argument is given) */
1216         if (CMD_ARGC < 2)
1217                 return ERROR_COMMAND_SYNTAX_ERROR;
1218         else {
1219                 uint32_t cp0_reg, cp0_sel;
1220                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], cp0_reg);
1221                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], cp0_sel);
1222
1223                 if (CMD_ARGC == 2) {
1224                         uint32_t value;
1225                         retval = mips32_cp0_read(ejtag_info, &value, cp0_reg, cp0_sel);
1226                         if (retval != ERROR_OK) {
1227                                 command_print(CMD_CTX,
1228                                                 "couldn't access reg %" PRIi32,
1229                                                 cp0_reg);
1230                                 return ERROR_OK;
1231                         }
1232                         command_print(CMD_CTX, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
1233                                         cp0_reg, cp0_sel, value);
1234
1235                 } else if (CMD_ARGC == 3) {
1236                         uint32_t value;
1237                         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
1238                         retval = mips32_cp0_write(ejtag_info, value, cp0_reg, cp0_sel);
1239                         if (retval != ERROR_OK) {
1240                                 command_print(CMD_CTX,
1241                                                 "couldn't access cp0 reg %" PRIi32 ", select %" PRIi32,
1242                                                 cp0_reg,  cp0_sel);
1243                                 return ERROR_OK;
1244                         }
1245                         command_print(CMD_CTX, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
1246                                         cp0_reg, cp0_sel, value);
1247                 }
1248         }
1249
1250         return ERROR_OK;
1251 }
1252
1253 COMMAND_HANDLER(mips_m4k_handle_smp_off_command)
1254 {
1255         struct target *target = get_current_target(CMD_CTX);
1256         /* check target is an smp target */
1257         struct target_list *head;
1258         struct target *curr;
1259         head = target->head;
1260         target->smp = 0;
1261         if (head != (struct target_list *)NULL) {
1262                 while (head != (struct target_list *)NULL) {
1263                         curr = head->target;
1264                         curr->smp = 0;
1265                         head = head->next;
1266                 }
1267                 /*  fixes the target display to the debugger */
1268                 target->gdb_service->target = target;
1269         }
1270         return ERROR_OK;
1271 }
1272
1273 COMMAND_HANDLER(mips_m4k_handle_smp_on_command)
1274 {
1275         struct target *target = get_current_target(CMD_CTX);
1276         struct target_list *head;
1277         struct target *curr;
1278         head = target->head;
1279         if (head != (struct target_list *)NULL) {
1280                 target->smp = 1;
1281                 while (head != (struct target_list *)NULL) {
1282                         curr = head->target;
1283                         curr->smp = 1;
1284                         head = head->next;
1285                 }
1286         }
1287         return ERROR_OK;
1288 }
1289
1290 COMMAND_HANDLER(mips_m4k_handle_smp_gdb_command)
1291 {
1292         struct target *target = get_current_target(CMD_CTX);
1293         int retval = ERROR_OK;
1294         struct target_list *head;
1295         head = target->head;
1296         if (head != (struct target_list *)NULL) {
1297                 if (CMD_ARGC == 1) {
1298                         int coreid = 0;
1299                         COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], coreid);
1300                         if (ERROR_OK != retval)
1301                                 return retval;
1302                         target->gdb_service->core[1] = coreid;
1303
1304                 }
1305                 command_print(CMD_CTX, "gdb coreid  %d -> %d", target->gdb_service->core[0]
1306                         , target->gdb_service->core[1]);
1307         }
1308         return ERROR_OK;
1309 }
1310
1311 COMMAND_HANDLER(mips_m4k_handle_scan_delay_command)
1312 {
1313         struct target *target = get_current_target(CMD_CTX);
1314         struct mips_m4k_common *mips_m4k = target_to_m4k(target);
1315         struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
1316
1317         if (CMD_ARGC == 1)
1318                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], ejtag_info->scan_delay);
1319         else if (CMD_ARGC > 1)
1320                         return ERROR_COMMAND_SYNTAX_ERROR;
1321
1322         command_print(CMD_CTX, "scan delay: %d nsec", ejtag_info->scan_delay);
1323         if (ejtag_info->scan_delay >= 20000000) {
1324                 ejtag_info->mode = 0;
1325                 command_print(CMD_CTX, "running in legacy mode");
1326         } else {
1327                 ejtag_info->mode = 1;
1328                 command_print(CMD_CTX, "running in fast queued mode");
1329         }
1330
1331         return ERROR_OK;
1332 }
1333
1334 static const struct command_registration mips_m4k_exec_command_handlers[] = {
1335         {
1336                 .name = "cp0",
1337                 .handler = mips_m4k_handle_cp0_command,
1338                 .mode = COMMAND_EXEC,
1339                 .usage = "regnum [value]",
1340                 .help = "display/modify cp0 register",
1341         },
1342         {
1343                 .name = "smp_off",
1344                 .handler = mips_m4k_handle_smp_off_command,
1345                 .mode = COMMAND_EXEC,
1346                 .help = "Stop smp handling",
1347                 .usage = "",},
1348
1349         {
1350                 .name = "smp_on",
1351                 .handler = mips_m4k_handle_smp_on_command,
1352                 .mode = COMMAND_EXEC,
1353                 .help = "Restart smp handling",
1354                 .usage = "",
1355         },
1356         {
1357                 .name = "smp_gdb",
1358                 .handler = mips_m4k_handle_smp_gdb_command,
1359                 .mode = COMMAND_EXEC,
1360                 .help = "display/fix current core played to gdb",
1361                 .usage = "",
1362         },
1363         {
1364                 .name = "scan_delay",
1365                 .handler = mips_m4k_handle_scan_delay_command,
1366                 .mode = COMMAND_ANY,
1367                 .help = "display/set scan delay in nano seconds",
1368                 .usage = "[value]",
1369         },
1370         COMMAND_REGISTRATION_DONE
1371 };
1372
1373 const struct command_registration mips_m4k_command_handlers[] = {
1374         {
1375                 .chain = mips32_command_handlers,
1376         },
1377         {
1378                 .name = "mips_m4k",
1379                 .mode = COMMAND_ANY,
1380                 .help = "mips_m4k command group",
1381                 .usage = "",
1382                 .chain = mips_m4k_exec_command_handlers,
1383         },
1384         COMMAND_REGISTRATION_DONE
1385 };
1386
1387 struct target_type mips_m4k_target = {
1388         .name = "mips_m4k",
1389
1390         .poll = mips_m4k_poll,
1391         .arch_state = mips32_arch_state,
1392
1393         .target_request_data = NULL,
1394
1395         .halt = mips_m4k_halt,
1396         .resume = mips_m4k_resume,
1397         .step = mips_m4k_step,
1398
1399         .assert_reset = mips_m4k_assert_reset,
1400         .deassert_reset = mips_m4k_deassert_reset,
1401         .soft_reset_halt = mips_m4k_soft_reset_halt,
1402
1403         .get_gdb_reg_list = mips32_get_gdb_reg_list,
1404
1405         .read_memory = mips_m4k_read_memory,
1406         .write_memory = mips_m4k_write_memory,
1407         .checksum_memory = mips32_checksum_memory,
1408         .blank_check_memory = mips32_blank_check_memory,
1409
1410         .run_algorithm = mips32_run_algorithm,
1411
1412         .add_breakpoint = mips_m4k_add_breakpoint,
1413         .remove_breakpoint = mips_m4k_remove_breakpoint,
1414         .add_watchpoint = mips_m4k_add_watchpoint,
1415         .remove_watchpoint = mips_m4k_remove_watchpoint,
1416
1417         .commands = mips_m4k_command_handlers,
1418         .target_create = mips_m4k_target_create,
1419         .init_target = mips_m4k_init_target,
1420         .examine = mips_m4k_examine,
1421 };