1 /***************************************************************************
2 * Copyright (C) 2013 Andes Technology *
3 * Hsiangkai Wang <hkwang@andestech.com> *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
19 ***************************************************************************/
24 #include <jtag/jtag.h>
26 #include "target_type.h"
28 #include "breakpoints.h"
29 #include "nds32_reg.h"
30 #include "nds32_insn.h"
31 #include "nds32_edm.h"
33 #define NDS32_EDM_OPERATION_MAX_NUM 64
35 #define CHECK_RETVAL(action) \
37 int __retval = (action); \
38 if (__retval != ERROR_OK) { \
39 LOG_DEBUG("error while calling \"%s\"", \
47 * Holds the interface to Andes cores.
50 extern const char *nds32_debug_type_name[11];
52 enum nds32_debug_reason {
53 NDS32_DEBUG_BREAK = 0,
55 NDS32_DEBUG_INST_BREAK,
56 NDS32_DEBUG_DATA_ADDR_WATCHPOINT_PRECISE,
57 NDS32_DEBUG_DATA_VALUE_WATCHPOINT_PRECISE,
58 NDS32_DEBUG_DATA_VALUE_WATCHPOINT_IMPRECISE,
59 NDS32_DEBUG_DEBUG_INTERRUPT,
60 NDS32_DEBUG_HARDWARE_SINGLE_STEP,
61 NDS32_DEBUG_DATA_ADDR_WATCHPOINT_NEXT_PRECISE,
62 NDS32_DEBUG_DATA_VALUE_WATCHPOINT_NEXT_PRECISE,
63 NDS32_DEBUG_LOAD_STORE_GLOBAL_STOP,
66 #define NDS32_STRUCT_STAT_SIZE 60
67 #define NDS32_STRUCT_TIMEVAL_SIZE 8
69 enum nds32_syscall_id {
70 NDS32_SYSCALL_UNDEFINED = 0,
71 NDS32_SYSCALL_EXIT = 1,
72 NDS32_SYSCALL_OPEN = 2,
73 NDS32_SYSCALL_CLOSE = 3,
74 NDS32_SYSCALL_READ = 4,
75 NDS32_SYSCALL_WRITE = 5,
76 NDS32_SYSCALL_LSEEK = 6,
77 NDS32_SYSCALL_UNLINK = 7,
78 NDS32_SYSCALL_RENAME = 3001,
79 NDS32_SYSCALL_FSTAT = 10,
80 NDS32_SYSCALL_STAT = 15,
81 NDS32_SYSCALL_GETTIMEOFDAY = 19,
82 NDS32_SYSCALL_ISATTY = 3002,
83 NDS32_SYSCALL_SYSTEM = 3003,
84 NDS32_SYSCALL_ERRNO = 6001,
87 #define NDS32_COMMON_MAGIC (int)0xADE5ADE5
91 /** EDM_CFG.VER, indicate the EDM version */
94 /** The number of hardware breakpoints */
97 /** EDM_CFG.DALM, indicate if direct local memory access
98 * feature is supported or not */
99 bool direct_access_local_memory;
101 /** Support ACC_CTL register */
105 bool support_max_stop;
110 /** enable cache or not */
113 /** cache sets per way */
119 /** cache line size */
122 /** cache locking support */
126 struct nds32_memory {
129 struct nds32_cache icache;
132 struct nds32_cache dcache;
134 /** On-chip instruction local memory base */
137 /** On-chip instruction local memory size */
140 /** ILM base register alignment version */
143 /** DLM is enabled or not */
146 /** DLM start address */
149 /** DLM end address */
152 /** On-chip data local memory base */
155 /** On-chip data local memory size */
158 /** DLM base register alignment version */
161 /** DLM is enabled or not */
164 /** DLM start address */
167 /** DLM end address */
170 /** Memory access method */
171 enum nds_memory_access access_channel;
173 /** Memory access mode */
174 enum nds_memory_select mode;
176 /** Address translation */
177 bool address_translation;
180 struct nds32_cpu_version {
181 bool performance_extension;
182 bool _16bit_extension;
183 bool performance_extension_2;
184 bool cop_fpu_extension;
185 bool string_extension;
192 struct nds32_mmu_config {
193 int memory_protection;
194 int memory_protection_version;
195 bool fully_associative_tlb;
199 bool _8k_page_support;
200 int extra_page_size_support;
202 bool hardware_page_table_walker;
209 int default_min_page_size;
210 bool multiple_page_size_in_use;
213 struct nds32_misc_config {
215 bool local_memory_dma;
216 bool performance_monitor;
217 bool high_speed_memory_port;
219 bool div_instruction;
220 bool mac_instruction;
223 bool reduce_register;
225 bool interruption_level;
226 int baseline_instruction;
228 bool implement_dependant_register;
229 bool implement_dependant_sr_encoding;
237 * Represents a generic Andes core.
241 struct reg_cache *core_cache;
243 /** Handle for the debug module. */
244 struct nds32_edm edm;
246 /** Memory information */
247 struct nds32_memory memory;
250 struct nds32_cpu_version cpu_version;
252 /** MMU configuration */
253 struct nds32_mmu_config mmu_config;
255 /** Misc configuration */
256 struct nds32_misc_config misc_config;
258 /** Retrieve all core registers, for display. */
259 int (*full_context)(struct nds32 *nds32);
261 /** Register mappings */
262 int (*register_map)(struct nds32 *nds32, int reg_no);
264 /** Get debug exception virtual address */
265 int (*get_debug_reason)(struct nds32 *nds32, uint32_t *reason);
267 /** Restore target registers may be modified in debug state */
268 int (*leave_debug_state)(struct nds32 *nds32, bool enable_watchpoint);
270 /** Backup target registers may be modified in debug state */
271 int (*enter_debug_state)(struct nds32 *nds32, bool enable_watchpoint);
273 /** Get address hit watchpoint */
274 int (*get_watched_address)(struct nds32 *nds32, uint32_t *address, uint32_t reason);
276 /** maximum interrupt level */
277 uint32_t max_interrupt_level;
279 /** current interrupt level */
280 uint32_t current_interrupt_level;
282 uint32_t watched_address;
284 /** Flag reporting whether virtual hosting is active. */
285 bool virtual_hosting;
287 /** Flag reporting whether continue/step hits syscall or not */
290 /** Value to be returned by virtual hosting SYS_ERRNO request. */
291 int virtual_hosting_errno;
293 /** Flag reporting whether syscall is aborted */
294 bool virtual_hosting_ctrl_c;
296 /** Record syscall ID for other operations to do special processing for target */
297 int active_syscall_id;
299 struct breakpoint syscall_break;
301 /** Flag reporting whether global stop is active. */
304 /** Flag reporting whether to use soft-reset-halt or not as issuing reset-halt. */
305 bool soft_reset_halt;
307 /** reset-halt as target examine */
308 bool reset_halt_as_examine;
310 /** backup/restore target EDM_CTL value. As debugging target debug
311 * handler, it should be true. */
312 bool keep_target_edm_ctl;
314 /* Value of $EDM_CTL before target enters debug mode */
315 uint32_t backup_edm_ctl;
317 /** always use word-aligned address to access memory */
318 bool word_access_mem;
320 /** EDM passcode for debugging secure MCU */
323 /** current privilege_level if using secure MCU. value 0 is the highest level. */
326 /** Period to wait after SRST. */
329 /** Flag to indicate HSS steps into ISR or not */
330 bool step_isr_enable;
332 /** Flag to indicate register table is ready or not */
333 bool init_arch_info_after_halted;
335 /** Flag to indicate audio-extension is enabled or not */
338 /** Flag to indicate fpu-extension is enabled or not */
341 /* Andes Core has mixed endian model. Instruction is always big-endian.
342 * Data may be big or little endian. Device registers may have different
343 * endian from data and instruction. */
344 /** Endian of data memory */
345 enum target_endianness data_endian;
347 /** Endian of device registers */
348 enum target_endianness device_reg_endian;
350 /** Flag to indicate if auto convert software breakpoints to
351 * hardware breakpoints or not in ROM */
352 bool auto_convert_hw_bp;
354 /* Flag to indicate the target is attached by debugger or not */
357 /** Backpointer to the target. */
358 struct target *target;
366 struct target *target;
371 struct nds32_edm_operation {
376 extern int nds32_config(struct nds32 *nds32);
377 extern int nds32_init_arch_info(struct target *target, struct nds32 *nds32);
378 extern int nds32_full_context(struct nds32 *nds32);
379 extern int nds32_arch_state(struct target *target);
380 extern int nds32_add_software_breakpoint(struct target *target,
381 struct breakpoint *breakpoint);
382 extern int nds32_remove_software_breakpoint(struct target *target,
383 struct breakpoint *breakpoint);
385 extern int nds32_get_gdb_reg_list(struct target *target,
386 struct reg **reg_list[], int *reg_list_size,
387 enum target_register_class reg_class);
389 extern int nds32_write_buffer(struct target *target, uint32_t address,
390 uint32_t size, const uint8_t *buffer);
391 extern int nds32_read_buffer(struct target *target, uint32_t address,
392 uint32_t size, uint8_t *buffer);
393 extern int nds32_read_memory(struct target *target, uint32_t address,
394 uint32_t size, uint32_t count, uint8_t *buffer);
395 extern int nds32_write_memory(struct target *target, uint32_t address,
396 uint32_t size, uint32_t count, const uint8_t *buffer);
398 extern int nds32_init_register_table(struct nds32 *nds32);
399 extern int nds32_init_memory_info(struct nds32 *nds32);
400 extern int nds32_restore_context(struct target *target);
401 extern int nds32_get_mapped_reg(struct nds32 *nds32, unsigned regnum, uint32_t *value);
402 extern int nds32_set_mapped_reg(struct nds32 *nds32, unsigned regnum, uint32_t value);
404 extern int nds32_edm_config(struct nds32 *nds32);
405 extern int nds32_cache_sync(struct target *target, uint32_t address, uint32_t length);
406 extern int nds32_mmu(struct target *target, int *enabled);
407 extern int nds32_virtual_to_physical(struct target *target, uint32_t address,
409 extern int nds32_read_phys_memory(struct target *target, uint32_t address,
410 uint32_t size, uint32_t count, uint8_t *buffer);
411 extern int nds32_write_phys_memory(struct target *target, uint32_t address,
412 uint32_t size, uint32_t count, const uint8_t *buffer);
413 extern uint32_t nds32_nextpc(struct nds32 *nds32, int current, uint32_t address);
414 extern int nds32_examine_debug_reason(struct nds32 *nds32);
415 extern int nds32_step(struct target *target, int current,
416 uint32_t address, int handle_breakpoints);
417 extern int nds32_target_state(struct nds32 *nds32, enum target_state *state);
418 extern int nds32_halt(struct target *target);
419 extern int nds32_poll(struct target *target);
420 extern int nds32_resume(struct target *target, int current,
421 uint32_t address, int handle_breakpoints, int debug_execution);
422 extern int nds32_assert_reset(struct target *target);
423 extern int nds32_init(struct nds32 *nds32);
424 extern int nds32_get_gdb_fileio_info(struct target *target, struct gdb_fileio_info *fileio_info);
425 extern int nds32_gdb_fileio_write_memory(struct nds32 *nds32, uint32_t address,
426 uint32_t size, const uint8_t *buffer);
427 extern int nds32_gdb_fileio_end(struct target *target, int retcode, int fileio_errno, bool ctrl_c);
428 extern int nds32_reset_halt(struct nds32 *nds32);
429 extern int nds32_login(struct nds32 *nds32);
430 extern int nds32_profiling(struct target *target, uint32_t *samples,
431 uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds);
433 /** Convert target handle to generic Andes target state handle. */
434 static inline struct nds32 *target_to_nds32(struct target *target)
436 assert(target != NULL);
437 return target->arch_info;
441 static inline struct aice_port_s *target_to_aice(struct target *target)
443 assert(target != NULL);
444 return target->tap->priv;
447 static inline bool is_nds32(struct nds32 *nds32)
449 assert(nds32 != NULL);
450 return nds32->common_magic == NDS32_COMMON_MAGIC;
453 static inline bool nds32_reach_max_interrupt_level(struct nds32 *nds32)
455 assert(nds32 != NULL);
456 return nds32->max_interrupt_level == nds32->current_interrupt_level;
459 #endif /* __NDS32_H__ */