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   1 /***************************************************************************
   2  *   Copyright (C) 2013 Andes Technology                                   *
   3  *   Hsiangkai Wang <hkwang@andestech.com>                                 *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  17  ***************************************************************************/
  18
  19 #ifndef OPENOCD_TARGET_NDS32_EDM_H
  20 #define OPENOCD_TARGET_NDS32_EDM_H
  21
  22 /**
  23  * @file
  24  * This is the interface to the Embedded Debug Module for Andes cores.
  25  */
  26
  27 /* EDM misc registers */
  28 enum nds_edm_misc_reg {
  29         NDS_EDM_MISC_DIMIR = 0x0,
  30         NDS_EDM_MISC_SBAR,
  31         NDS_EDM_MISC_EDM_CMDR,
  32         NDS_EDM_MISC_DBGER,
  33         NDS_EDM_MISC_ACC_CTL,
  34         NDS_EDM_MISC_EDM_PROBE,
  35         NDS_EDM_MISC_GEN_PORT0,
  36         NDS_EDM_MISC_GEN_PORT1,
  37 };
  38
  39 /* EDM system registers */
  40 enum nds_edm_system_reg {
  41         NDS_EDM_SR_BPC0 = 0x00,
  42         NDS_EDM_SR_BPC1,
  43         NDS_EDM_SR_BPC2,
  44         NDS_EDM_SR_BPC3,
  45         NDS_EDM_SR_BPC4,
  46         NDS_EDM_SR_BPC5,
  47         NDS_EDM_SR_BPC6,
  48         NDS_EDM_SR_BPC7,
  49         NDS_EDM_SR_BPA0 = 0x08,
  50         NDS_EDM_SR_BPA1,
  51         NDS_EDM_SR_BPA2,
  52         NDS_EDM_SR_BPA3,
  53         NDS_EDM_SR_BPA4,
  54         NDS_EDM_SR_BPA5,
  55         NDS_EDM_SR_BPA6,
  56         NDS_EDM_SR_BPA7,
  57         NDS_EDM_SR_BPAM0 = 0x10,
  58         NDS_EDM_SR_BPAM1,
  59         NDS_EDM_SR_BPAM2,
  60         NDS_EDM_SR_BPAM3,
  61         NDS_EDM_SR_BPAM4,
  62         NDS_EDM_SR_BPAM5,
  63         NDS_EDM_SR_BPAM6,
  64         NDS_EDM_SR_BPAM7,
  65         NDS_EDM_SR_BPV0 = 0x18,
  66         NDS_EDM_SR_BPV1,
  67         NDS_EDM_SR_BPV2,
  68         NDS_EDM_SR_BPV3,
  69         NDS_EDM_SR_BPV4,
  70         NDS_EDM_SR_BPV5,
  71         NDS_EDM_SR_BPV6,
  72         NDS_EDM_SR_BPV7,
  73         NDS_EDM_SR_BPCID0 = 0x20,
  74         NDS_EDM_SR_BPCID1,
  75         NDS_EDM_SR_BPCID2,
  76         NDS_EDM_SR_BPCID3,
  77         NDS_EDM_SR_BPCID4,
  78         NDS_EDM_SR_BPCID5,
  79         NDS_EDM_SR_BPCID6,
  80         NDS_EDM_SR_BPCID7,
  81         NDS_EDM_SR_EDM_CFG = 0x28,
  82         NDS_EDM_SR_EDMSW = 0x30,
  83         NDS_EDM_SR_EDM_CTL = 0x38,
  84         NDS_EDM_SR_EDM_DTR = 0x40,
  85         NDS_EDM_SR_BPMTV = 0x48,
  86         NDS_EDM_SR_DIMBR = 0x50,
  87         NDS_EDM_SR_TECR0 = 0x70,
  88         NDS_EDM_SR_TECR1 = 0x71,
  89 };
  90
  91 enum nds_memory_access {
  92         NDS_MEMORY_ACC_BUS = 0,
  93         NDS_MEMORY_ACC_CPU,
  94 };
  95
  96 enum nds_memory_select {
  97         NDS_MEMORY_SELECT_AUTO = 0,
  98         NDS_MEMORY_SELECT_MEM = 1,
  99         NDS_MEMORY_SELECT_ILM = 2,
 100         NDS_MEMORY_SELECT_DLM = 3,
 101 };
 102
 103 #define NDS_DBGER_DEX           (0x1)
 104 #define NDS_DBGER_DPED          (0x2)
 105 #define NDS_DBGER_CRST          (0x4)
 106 #define NDS_DBGER_AT_MAX        (0x8)
 107 #define NDS_DBGER_ILL_SEC_ACC   (0x10)
 108 #define NDS_DBGER_ALL_SUPRS_EX  (0x40000000)
 109 #define NDS_DBGER_RESACC        (0x80000000)
 110 #define NDS_DBGER_CLEAR_ALL     (0x1F)
 111
 112 #define NDS_EDMSW_WDV           (1 << 0)
 113 #define NDS_EDMSW_RDV           (1 << 1)
 114
 115 #endif /* OPENOCD_TARGET_NDS32_EDM_H */