2 # Texas Instruments DaVinci family: TMS320DM355
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4 if { [info exists CHIPNAME] } {
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5 set _CHIPNAME $CHIPNAME
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9 if { [info exists ENDIAN] } {
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16 # For now, expect EMU0/EMU1 jumpered LOW (not TI's default) so ARM and ETB
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17 # are enabled without making ICEpick route ARM and ETB into the JTAG chain.
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19 # Also note: when running without RTCK before the PLLs are set up, you
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20 # may need to slow the JTAG clock down quite a lot (under 2 MHz).
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23 # Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
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24 if { [info exists ETB_TAPID ] } {
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25 set _ETB_TAPID $ETB_TAPID
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27 set _ETB_TAPID 0x2b900f0f
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29 jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_ETB_TAPID
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31 # Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
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32 if { [info exists CPU_TAPID ] } {
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33 set _CPU_TAPID $CPU_TAPID
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35 set _CPU_TAPID 0x07926001
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37 jtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPU_TAPID
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39 # Primary TAP: ICEpick (JTAG route controller) and boundary scan
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40 if { [info exists JRC_TAPID ] } {
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41 set _JRC_TAPID $JRC_TAPID
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43 set _JRC_TAPID 0x0b73b02f
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45 jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID
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47 # GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 16K)
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48 # and the ETB memory (4K) are other options, while trace is unused.
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49 set _TARGETNAME $_CHIPNAME.arm
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51 target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
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52 $_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00014000 -work-area-size 0x4000 -work-area-backup 0
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55 arm7_9 fast_memory_access enable
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56 arm7_9 dcc_downloads enable
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59 # FIXME we ought to be able to say "... config $_TARGETNAME ..."
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60 # (not "config 0") facilitating additional targets (e.g. other chips)
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61 etm config 0 16 normal full etb
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62 etb config 0 $_CHIPNAME.etb
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