1 /***************************************************************************
2 * Copyright (C) 2006, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "replacements.h"
31 #include "arm_simulator.h"
32 #include "arm_disassembler.h"
35 #include "binarybuffer.h"
36 #include "time_support.h"
37 #include "breakpoints.h"
43 #include <sys/types.h>
49 int xscale_register_commands(struct command_context_s *cmd_ctx);
51 /* forward declarations */
52 int xscale_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
53 int xscale_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
56 int xscale_arch_state(struct target_s *target);
57 int xscale_poll(target_t *target);
58 int xscale_halt(target_t *target);
59 int xscale_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution);
60 int xscale_step(struct target_s *target, int current, u32 address, int handle_breakpoints);
61 int xscale_debug_entry(target_t *target);
62 int xscale_restore_context(target_t *target);
64 int xscale_assert_reset(target_t *target);
65 int xscale_deassert_reset(target_t *target);
66 int xscale_soft_reset_halt(struct target_s *target);
68 int xscale_set_reg_u32(reg_t *reg, u32 value);
70 int xscale_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode);
71 int xscale_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, u32 value);
73 int xscale_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
74 int xscale_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
75 int xscale_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer);
76 int xscale_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum);
78 int xscale_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
79 int xscale_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
80 int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
81 int xscale_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
82 int xscale_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
83 int xscale_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
84 void xscale_enable_watchpoints(struct target_s *target);
85 void xscale_enable_breakpoints(struct target_s *target);
86 static int xscale_virt2phys(struct target_s *target, u32 virtual, u32 *physical);
87 static int xscale_mmu(struct target_s *target, int *enabled);
89 int xscale_read_trace(target_t *target);
91 target_type_t xscale_target =
96 .arch_state = xscale_arch_state,
98 .target_request_data = NULL,
101 .resume = xscale_resume,
104 .assert_reset = xscale_assert_reset,
105 .deassert_reset = xscale_deassert_reset,
106 .soft_reset_halt = xscale_soft_reset_halt,
108 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
110 .read_memory = xscale_read_memory,
111 .write_memory = xscale_write_memory,
112 .bulk_write_memory = xscale_bulk_write_memory,
113 .checksum_memory = xscale_checksum_memory,
115 .run_algorithm = armv4_5_run_algorithm,
117 .add_breakpoint = xscale_add_breakpoint,
118 .remove_breakpoint = xscale_remove_breakpoint,
119 .add_watchpoint = xscale_add_watchpoint,
120 .remove_watchpoint = xscale_remove_watchpoint,
122 .register_commands = xscale_register_commands,
123 .target_command = xscale_target_command,
124 .init_target = xscale_init_target,
127 .virt2phys = xscale_virt2phys,
131 char* xscale_reg_list[] =
133 "XSCALE_MAINID", /* 0 */
143 "XSCALE_IBCR0", /* 10 */
153 "XSCALE_RX", /* 20 */
157 xscale_reg_t xscale_reg_arch_info[] =
159 {XSCALE_MAINID, NULL},
160 {XSCALE_CACHETYPE, NULL},
162 {XSCALE_AUXCTRL, NULL},
168 {XSCALE_CPACCESS, NULL},
169 {XSCALE_IBCR0, NULL},
170 {XSCALE_IBCR1, NULL},
173 {XSCALE_DBCON, NULL},
174 {XSCALE_TBREG, NULL},
175 {XSCALE_CHKPT0, NULL},
176 {XSCALE_CHKPT1, NULL},
177 {XSCALE_DCSR, NULL}, /* DCSR accessed via JTAG or SW */
178 {-1, NULL}, /* TX accessed via JTAG */
179 {-1, NULL}, /* RX accessed via JTAG */
180 {-1, NULL}, /* TXRXCTRL implicit access via JTAG */
183 int xscale_reg_arch_type = -1;
185 int xscale_get_reg(reg_t *reg);
186 int xscale_set_reg(reg_t *reg, u8 *buf);
188 int xscale_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, xscale_common_t **xscale_p)
190 armv4_5_common_t *armv4_5 = target->arch_info;
191 xscale_common_t *xscale = armv4_5->arch_info;
193 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
195 LOG_ERROR("target isn't an XScale target");
199 if (xscale->common_magic != XSCALE_COMMON_MAGIC)
201 LOG_ERROR("target isn't an XScale target");
205 *armv4_5_p = armv4_5;
211 int xscale_jtag_set_instr(int chain_pos, u32 new_instr)
213 jtag_device_t *device = jtag_get_device(chain_pos);
215 if (buf_get_u32(device->cur_instr, 0, device->ir_length) != new_instr)
219 field.device = chain_pos;
220 field.num_bits = device->ir_length;
221 field.out_value = calloc(CEIL(field.num_bits, 8), 1);
222 buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
223 field.out_mask = NULL;
224 field.in_value = NULL;
225 jtag_set_check_value(&field, device->expected, device->expected_mask, NULL);
227 jtag_add_ir_scan(1, &field, -1);
229 free(field.out_value);
235 int xscale_read_dcsr(target_t *target)
237 armv4_5_common_t *armv4_5 = target->arch_info;
238 xscale_common_t *xscale = armv4_5->arch_info;
242 scan_field_t fields[3];
244 u8 field0_check_value = 0x2;
245 u8 field0_check_mask = 0x7;
247 u8 field2_check_value = 0x0;
248 u8 field2_check_mask = 0x1;
250 jtag_add_end_state(TAP_PD);
251 xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dcsr);
253 buf_set_u32(&field0, 1, 1, xscale->hold_rst);
254 buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
256 fields[0].device = xscale->jtag_info.chain_pos;
257 fields[0].num_bits = 3;
258 fields[0].out_value = &field0;
259 fields[0].out_mask = NULL;
260 fields[0].in_value = NULL;
261 jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL);
263 fields[1].device = xscale->jtag_info.chain_pos;
264 fields[1].num_bits = 32;
265 fields[1].out_value = NULL;
266 fields[1].out_mask = NULL;
267 fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
268 fields[1].in_handler = NULL;
269 fields[1].in_handler_priv = NULL;
270 fields[1].in_check_value = NULL;
271 fields[1].in_check_mask = NULL;
273 fields[2].device = xscale->jtag_info.chain_pos;
274 fields[2].num_bits = 1;
275 fields[2].out_value = &field2;
276 fields[2].out_mask = NULL;
277 fields[2].in_value = NULL;
278 jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
280 jtag_add_dr_scan(3, fields, -1);
282 if ((retval = jtag_execute_queue()) != ERROR_OK)
284 LOG_ERROR("JTAG error while reading DCSR");
288 xscale->reg_cache->reg_list[XSCALE_DCSR].dirty = 0;
289 xscale->reg_cache->reg_list[XSCALE_DCSR].valid = 1;
291 /* write the register with the value we just read
292 * on this second pass, only the first bit of field0 is guaranteed to be 0)
294 field0_check_mask = 0x1;
295 fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
296 fields[1].in_value = NULL;
298 jtag_add_end_state(TAP_RTI);
300 jtag_add_dr_scan(3, fields, -1);
302 /* DANGER!!! this must be here. It will make sure that the arguments
303 * to jtag_set_check_value() does not go out of scope! */
304 return jtag_execute_queue();
307 int xscale_receive(target_t *target, u32 *buffer, int num_words)
310 return ERROR_INVALID_ARGUMENTS;
313 armv4_5_common_t *armv4_5 = target->arch_info;
314 xscale_common_t *xscale = armv4_5->arch_info;
316 enum tap_state path[3];
317 scan_field_t fields[3];
319 u8 *field0 = malloc(num_words * 1);
320 u8 field0_check_value = 0x2;
321 u8 field0_check_mask = 0x6;
322 u32 *field1 = malloc(num_words * 4);
323 u8 field2_check_value = 0x0;
324 u8 field2_check_mask = 0x1;
326 int words_scheduled = 0;
334 fields[0].device = xscale->jtag_info.chain_pos;
335 fields[0].num_bits = 3;
336 fields[0].out_value = NULL;
337 fields[0].out_mask = NULL;
338 fields[0].in_value = NULL;
339 jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL);
341 fields[1].device = xscale->jtag_info.chain_pos;
342 fields[1].num_bits = 32;
343 fields[1].out_value = NULL;
344 fields[1].out_mask = NULL;
345 fields[1].in_value = NULL;
346 fields[1].in_handler = NULL;
347 fields[1].in_handler_priv = NULL;
348 fields[1].in_check_value = NULL;
349 fields[1].in_check_mask = NULL;
353 fields[2].device = xscale->jtag_info.chain_pos;
354 fields[2].num_bits = 1;
355 fields[2].out_value = NULL;
356 fields[2].out_mask = NULL;
357 fields[2].in_value = NULL;
358 jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
360 jtag_add_end_state(TAP_RTI);
361 xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dbgtx);
362 jtag_add_runtest(1, -1); /* ensures that we're in the TAP_RTI state as the above could be a no-op */
364 /* repeat until all words have been collected */
366 while (words_done < num_words)
370 for (i = words_done; i < num_words; i++)
372 fields[0].in_value = &field0[i];
373 fields[1].in_handler = buf_to_u32_handler;
374 fields[1].in_handler_priv = (u8*)&field1[i];
376 jtag_add_pathmove(3, path);
377 jtag_add_dr_scan(3, fields, TAP_RTI);
381 if ((retval = jtag_execute_queue()) != ERROR_OK)
383 LOG_ERROR("JTAG error while receiving data from debug handler");
387 /* examine results */
388 for (i = words_done; i < num_words; i++)
390 if (!(field0[0] & 1))
392 /* move backwards if necessary */
394 for (j = i; j < num_words - 1; j++)
396 field0[j] = field0[j+1];
397 field1[j] = field1[j+1];
402 if (words_scheduled==0)
404 if (attempts++==1000)
406 LOG_ERROR("Failed to receiving data from debug handler after 1000 attempts");
407 retval=ERROR_TARGET_TIMEOUT;
412 words_done += words_scheduled;
415 for (i = 0; i < num_words; i++)
416 *(buffer++) = buf_get_u32((u8*)&field1[i], 0, 32);
423 int xscale_read_tx(target_t *target, int consume)
425 armv4_5_common_t *armv4_5 = target->arch_info;
426 xscale_common_t *xscale = armv4_5->arch_info;
427 enum tap_state path[3];
428 enum tap_state noconsume_path[6];
431 struct timeval timeout, now;
433 scan_field_t fields[3];
435 u8 field0_check_value = 0x2;
436 u8 field0_check_mask = 0x6;
437 u8 field2_check_value = 0x0;
438 u8 field2_check_mask = 0x1;
440 jtag_add_end_state(TAP_RTI);
442 xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dbgtx);
448 noconsume_path[0] = TAP_SDS;
449 noconsume_path[1] = TAP_CD;
450 noconsume_path[2] = TAP_E1D;
451 noconsume_path[3] = TAP_PD;
452 noconsume_path[4] = TAP_E2D;
453 noconsume_path[5] = TAP_SD;
455 fields[0].device = xscale->jtag_info.chain_pos;
456 fields[0].num_bits = 3;
457 fields[0].out_value = NULL;
458 fields[0].out_mask = NULL;
459 fields[0].in_value = &field0_in;
460 jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL);
462 fields[1].device = xscale->jtag_info.chain_pos;
463 fields[1].num_bits = 32;
464 fields[1].out_value = NULL;
465 fields[1].out_mask = NULL;
466 fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_TX].value;
467 fields[1].in_handler = NULL;
468 fields[1].in_handler_priv = NULL;
469 fields[1].in_check_value = NULL;
470 fields[1].in_check_mask = NULL;
474 fields[2].device = xscale->jtag_info.chain_pos;
475 fields[2].num_bits = 1;
476 fields[2].out_value = NULL;
477 fields[2].out_mask = NULL;
478 fields[2].in_value = NULL;
479 jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
481 gettimeofday(&timeout, NULL);
482 timeval_add_time(&timeout, 1, 0);
487 for (i=0; i<100; i++)
489 /* if we want to consume the register content (i.e. clear TX_READY),
490 * we have to go straight from Capture-DR to Shift-DR
491 * otherwise, we go from Capture-DR to Exit1-DR to Pause-DR
494 jtag_add_pathmove(3, path);
497 jtag_add_pathmove(sizeof(noconsume_path)/sizeof(*noconsume_path), noconsume_path);
500 jtag_add_dr_scan(3, fields, TAP_RTI);
502 if ((retval = jtag_execute_queue()) != ERROR_OK)
504 LOG_ERROR("JTAG error while reading TX");
505 return ERROR_TARGET_TIMEOUT;
508 gettimeofday(&now, NULL);
509 if ((now.tv_sec > timeout.tv_sec) || ((now.tv_sec == timeout.tv_sec)&& (now.tv_usec > timeout.tv_usec)))
511 LOG_ERROR("time out reading TX register");
512 return ERROR_TARGET_TIMEOUT;
514 if (!((!(field0_in & 1)) && consume))
519 LOG_DEBUG("waiting 10ms");
520 usleep(10*1000); /* avoid flooding the logs */
524 if (!(field0_in & 1))
525 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
530 int xscale_write_rx(target_t *target)
532 armv4_5_common_t *armv4_5 = target->arch_info;
533 xscale_common_t *xscale = armv4_5->arch_info;
536 struct timeval timeout, now;
538 scan_field_t fields[3];
541 u8 field0_check_value = 0x2;
542 u8 field0_check_mask = 0x6;
544 u8 field2_check_value = 0x0;
545 u8 field2_check_mask = 0x1;
547 jtag_add_end_state(TAP_RTI);
549 xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dbgrx);
551 fields[0].device = xscale->jtag_info.chain_pos;
552 fields[0].num_bits = 3;
553 fields[0].out_value = &field0_out;
554 fields[0].out_mask = NULL;
555 fields[0].in_value = &field0_in;
556 jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL);
558 fields[1].device = xscale->jtag_info.chain_pos;
559 fields[1].num_bits = 32;
560 fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_RX].value;
561 fields[1].out_mask = NULL;
562 fields[1].in_value = NULL;
563 fields[1].in_handler = NULL;
564 fields[1].in_handler_priv = NULL;
565 fields[1].in_check_value = NULL;
566 fields[1].in_check_mask = NULL;
570 fields[2].device = xscale->jtag_info.chain_pos;
571 fields[2].num_bits = 1;
572 fields[2].out_value = &field2;
573 fields[2].out_mask = NULL;
574 fields[2].in_value = NULL;
575 jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
577 gettimeofday(&timeout, NULL);
578 timeval_add_time(&timeout, 1, 0);
580 /* poll until rx_read is low */
581 LOG_DEBUG("polling RX");
587 jtag_add_dr_scan(3, fields, TAP_RTI);
589 if ((retval = jtag_execute_queue()) != ERROR_OK)
591 LOG_ERROR("JTAG error while writing RX");
595 gettimeofday(&now, NULL);
596 if ((now.tv_sec > timeout.tv_sec) || ((now.tv_sec == timeout.tv_sec)&& (now.tv_usec > timeout.tv_usec)))
598 LOG_ERROR("time out writing RX register");
599 return ERROR_TARGET_TIMEOUT;
601 if (!(field0_in & 1))
604 LOG_DEBUG("waiting 10ms");
605 usleep(10*1000); /* wait 10ms to avoid flooding the logs */
611 jtag_add_dr_scan(3, fields, TAP_RTI);
613 if ((retval = jtag_execute_queue()) != ERROR_OK)
615 LOG_ERROR("JTAG error while writing RX");
622 /* send count elements of size byte to the debug handler */
623 int xscale_send(target_t *target, u8 *buffer, int count, int size)
625 armv4_5_common_t *armv4_5 = target->arch_info;
626 xscale_common_t *xscale = armv4_5->arch_info;
634 jtag_add_end_state(TAP_RTI);
636 xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dbgrx);
643 int endianness = target->endianness;
644 while (done_count++ < count)
649 if (endianness == TARGET_LITTLE_ENDIAN)
651 t[1]=le_to_h_u32(buffer);
654 t[1]=be_to_h_u32(buffer);
658 if (endianness == TARGET_LITTLE_ENDIAN)
660 t[1]=le_to_h_u16(buffer);
663 t[1]=be_to_h_u16(buffer);
670 LOG_ERROR("BUG: size neither 4, 2 nor 1");
673 jtag_add_dr_out(xscale->jtag_info.chain_pos,
681 if ((retval = jtag_execute_queue()) != ERROR_OK)
683 LOG_ERROR("JTAG error while sending data to debug handler");
690 int xscale_send_u32(target_t *target, u32 value)
692 armv4_5_common_t *armv4_5 = target->arch_info;
693 xscale_common_t *xscale = armv4_5->arch_info;
695 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_RX].value, 0, 32, value);
696 return xscale_write_rx(target);
699 int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk)
701 armv4_5_common_t *armv4_5 = target->arch_info;
702 xscale_common_t *xscale = armv4_5->arch_info;
706 scan_field_t fields[3];
708 u8 field0_check_value = 0x2;
709 u8 field0_check_mask = 0x7;
711 u8 field2_check_value = 0x0;
712 u8 field2_check_mask = 0x1;
715 xscale->hold_rst = hold_rst;
717 if (ext_dbg_brk != -1)
718 xscale->external_debug_break = ext_dbg_brk;
720 jtag_add_end_state(TAP_RTI);
721 xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dcsr);
723 buf_set_u32(&field0, 1, 1, xscale->hold_rst);
724 buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
726 fields[0].device = xscale->jtag_info.chain_pos;
727 fields[0].num_bits = 3;
728 fields[0].out_value = &field0;
729 fields[0].out_mask = NULL;
730 fields[0].in_value = NULL;
731 jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL);
733 fields[1].device = xscale->jtag_info.chain_pos;
734 fields[1].num_bits = 32;
735 fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
736 fields[1].out_mask = NULL;
737 fields[1].in_value = NULL;
738 fields[1].in_handler = NULL;
739 fields[1].in_handler_priv = NULL;
740 fields[1].in_check_value = NULL;
741 fields[1].in_check_mask = NULL;
745 fields[2].device = xscale->jtag_info.chain_pos;
746 fields[2].num_bits = 1;
747 fields[2].out_value = &field2;
748 fields[2].out_mask = NULL;
749 fields[2].in_value = NULL;
750 jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
752 jtag_add_dr_scan(3, fields, -1);
754 if ((retval = jtag_execute_queue()) != ERROR_OK)
756 LOG_ERROR("JTAG error while writing DCSR");
760 xscale->reg_cache->reg_list[XSCALE_DCSR].dirty = 0;
761 xscale->reg_cache->reg_list[XSCALE_DCSR].valid = 1;
766 /* parity of the number of bits 0 if even; 1 if odd. for 32 bit words */
767 unsigned int parity (unsigned int v)
774 LOG_DEBUG("parity of 0x%x is %i", ov, (0x6996 >> v) & 1);
775 return (0x6996 >> v) & 1;
778 int xscale_load_ic(target_t *target, int mini, u32 va, u32 buffer[8])
780 armv4_5_common_t *armv4_5 = target->arch_info;
781 xscale_common_t *xscale = armv4_5->arch_info;
786 scan_field_t fields[2];
788 LOG_DEBUG("loading miniIC at 0x%8.8x", va);
790 jtag_add_end_state(TAP_RTI);
791 xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.ldic); /* LDIC */
793 /* CMD is b010 for Main IC and b011 for Mini IC */
795 buf_set_u32(&cmd, 0, 3, 0x3);
797 buf_set_u32(&cmd, 0, 3, 0x2);
799 buf_set_u32(&cmd, 3, 3, 0x0);
801 /* virtual address of desired cache line */
802 buf_set_u32(packet, 0, 27, va >> 5);
804 fields[0].device = xscale->jtag_info.chain_pos;
805 fields[0].num_bits = 6;
806 fields[0].out_value = &cmd;
807 fields[0].out_mask = NULL;
808 fields[0].in_value = NULL;
809 fields[0].in_check_value = NULL;
810 fields[0].in_check_mask = NULL;
811 fields[0].in_handler = NULL;
812 fields[0].in_handler_priv = NULL;
814 fields[1].device = xscale->jtag_info.chain_pos;
815 fields[1].num_bits = 27;
816 fields[1].out_value = packet;
817 fields[1].out_mask = NULL;
818 fields[1].in_value = NULL;
819 fields[1].in_check_value = NULL;
820 fields[1].in_check_mask = NULL;
821 fields[1].in_handler = NULL;
822 fields[1].in_handler_priv = NULL;
824 jtag_add_dr_scan(2, fields, -1);
826 fields[0].num_bits = 32;
827 fields[0].out_value = packet;
829 fields[1].num_bits = 1;
830 fields[1].out_value = &cmd;
832 for (word = 0; word < 8; word++)
834 buf_set_u32(packet, 0, 32, buffer[word]);
835 cmd = parity(*((u32*)packet));
836 jtag_add_dr_scan(2, fields, -1);
839 jtag_execute_queue();
844 int xscale_invalidate_ic_line(target_t *target, u32 va)
846 armv4_5_common_t *armv4_5 = target->arch_info;
847 xscale_common_t *xscale = armv4_5->arch_info;
851 scan_field_t fields[2];
853 jtag_add_end_state(TAP_RTI);
854 xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.ldic); /* LDIC */
856 /* CMD for invalidate IC line b000, bits [6:4] b000 */
857 buf_set_u32(&cmd, 0, 6, 0x0);
859 /* virtual address of desired cache line */
860 buf_set_u32(packet, 0, 27, va >> 5);
862 fields[0].device = xscale->jtag_info.chain_pos;
863 fields[0].num_bits = 6;
864 fields[0].out_value = &cmd;
865 fields[0].out_mask = NULL;
866 fields[0].in_value = NULL;
867 fields[0].in_check_value = NULL;
868 fields[0].in_check_mask = NULL;
869 fields[0].in_handler = NULL;
870 fields[0].in_handler_priv = NULL;
872 fields[1].device = xscale->jtag_info.chain_pos;
873 fields[1].num_bits = 27;
874 fields[1].out_value = packet;
875 fields[1].out_mask = NULL;
876 fields[1].in_value = NULL;
877 fields[1].in_check_value = NULL;
878 fields[1].in_check_mask = NULL;
879 fields[1].in_handler = NULL;
880 fields[1].in_handler_priv = NULL;
882 jtag_add_dr_scan(2, fields, -1);
887 int xscale_update_vectors(target_t *target)
889 armv4_5_common_t *armv4_5 = target->arch_info;
890 xscale_common_t *xscale = armv4_5->arch_info;
894 u32 low_reset_branch, high_reset_branch;
896 for (i = 1; i < 8; i++)
898 /* if there's a static vector specified for this exception, override */
899 if (xscale->static_high_vectors_set & (1 << i))
901 xscale->high_vectors[i] = xscale->static_high_vectors[i];
905 retval=target_read_u32(target, 0xffff0000 + 4*i, &xscale->high_vectors[i]);
906 if (retval == ERROR_TARGET_TIMEOUT)
908 if (retval!=ERROR_OK)
910 /* Some of these reads will fail as part of normal execution */
911 xscale->high_vectors[i] = ARMV4_5_B(0xfffffe, 0);
916 for (i = 1; i < 8; i++)
918 if (xscale->static_low_vectors_set & (1 << i))
920 xscale->low_vectors[i] = xscale->static_low_vectors[i];
924 retval=target_read_u32(target, 0x0 + 4*i, &xscale->low_vectors[i]);
925 if (retval == ERROR_TARGET_TIMEOUT)
927 if (retval!=ERROR_OK)
929 /* Some of these reads will fail as part of normal execution */
930 xscale->low_vectors[i] = ARMV4_5_B(0xfffffe, 0);
935 /* calculate branches to debug handler */
936 low_reset_branch = (xscale->handler_address + 0x20 - 0x0 - 0x8) >> 2;
937 high_reset_branch = (xscale->handler_address + 0x20 - 0xffff0000 - 0x8) >> 2;
939 xscale->low_vectors[0] = ARMV4_5_B((low_reset_branch & 0xffffff), 0);
940 xscale->high_vectors[0] = ARMV4_5_B((high_reset_branch & 0xffffff), 0);
942 /* invalidate and load exception vectors in mini i-cache */
943 xscale_invalidate_ic_line(target, 0x0);
944 xscale_invalidate_ic_line(target, 0xffff0000);
946 xscale_load_ic(target, 1, 0x0, xscale->low_vectors);
947 xscale_load_ic(target, 1, 0xffff0000, xscale->high_vectors);
952 int xscale_arch_state(struct target_s *target)
954 armv4_5_common_t *armv4_5 = target->arch_info;
955 xscale_common_t *xscale = armv4_5->arch_info;
959 "disabled", "enabled"
962 char *arch_dbg_reason[] =
964 "", "\n(processor reset)", "\n(trace buffer full)"
967 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
969 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
973 LOG_USER("target halted in %s state due to %s, current mode: %s\n"
974 "cpsr: 0x%8.8x pc: 0x%8.8x\n"
975 "MMU: %s, D-Cache: %s, I-Cache: %s"
977 armv4_5_state_strings[armv4_5->core_state],
978 target_debug_reason_strings[target->debug_reason],
979 armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
980 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
981 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
982 state[xscale->armv4_5_mmu.mmu_enabled],
983 state[xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
984 state[xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled],
985 arch_dbg_reason[xscale->arch_debug_reason]);
990 int xscale_poll(target_t *target)
993 armv4_5_common_t *armv4_5 = target->arch_info;
994 xscale_common_t *xscale = armv4_5->arch_info;
996 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_DEBUG_RUNNING))
998 enum target_state previous_state = target->state;
999 if ((retval = xscale_read_tx(target, 0)) == ERROR_OK)
1002 /* there's data to read from the tx register, we entered debug state */
1003 xscale->handler_running = 1;
1005 target->state = TARGET_HALTED;
1007 /* process debug entry, fetching current mode regs */
1008 retval = xscale_debug_entry(target);
1010 else if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
1012 LOG_USER("error while polling TX register, reset CPU");
1013 /* here we "lie" so GDB won't get stuck and a reset can be perfomed */
1014 target->state = TARGET_HALTED;
1017 /* debug_entry could have overwritten target state (i.e. immediate resume)
1018 * don't signal event handlers in that case
1020 if (target->state != TARGET_HALTED)
1023 /* if target was running, signal that we halted
1024 * otherwise we reentered from debug execution */
1025 if (previous_state == TARGET_RUNNING)
1026 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1028 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
1034 int xscale_debug_entry(target_t *target)
1036 armv4_5_common_t *armv4_5 = target->arch_info;
1037 xscale_common_t *xscale = armv4_5->arch_info;
1045 /* clear external dbg break (will be written on next DCSR read) */
1046 xscale->external_debug_break = 0;
1047 if ((retval=xscale_read_dcsr(target))!=ERROR_OK)
1050 /* get r0, pc, r1 to r7 and cpsr */
1051 if ((retval=xscale_receive(target, buffer, 10))!=ERROR_OK)
1054 /* move r0 from buffer to register cache */
1055 buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, buffer[0]);
1056 armv4_5->core_cache->reg_list[15].dirty = 1;
1057 armv4_5->core_cache->reg_list[15].valid = 1;
1058 LOG_DEBUG("r0: 0x%8.8x", buffer[0]);
1060 /* move pc from buffer to register cache */
1061 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, buffer[1]);
1062 armv4_5->core_cache->reg_list[15].dirty = 1;
1063 armv4_5->core_cache->reg_list[15].valid = 1;
1064 LOG_DEBUG("pc: 0x%8.8x", buffer[1]);
1066 /* move data from buffer to register cache */
1067 for (i = 1; i <= 7; i++)
1069 buf_set_u32(armv4_5->core_cache->reg_list[i].value, 0, 32, buffer[1 + i]);
1070 armv4_5->core_cache->reg_list[i].dirty = 1;
1071 armv4_5->core_cache->reg_list[i].valid = 1;
1072 LOG_DEBUG("r%i: 0x%8.8x", i, buffer[i + 1]);
1075 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, buffer[9]);
1076 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
1077 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1078 LOG_DEBUG("cpsr: 0x%8.8x", buffer[9]);
1080 armv4_5->core_mode = buffer[9] & 0x1f;
1081 if (armv4_5_mode_to_number(armv4_5->core_mode) == -1)
1083 target->state = TARGET_UNKNOWN;
1084 LOG_ERROR("cpsr contains invalid mode value - communication failure");
1085 return ERROR_TARGET_FAILURE;
1087 LOG_DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]);
1089 if (buffer[9] & 0x20)
1090 armv4_5->core_state = ARMV4_5_STATE_THUMB;
1092 armv4_5->core_state = ARMV4_5_STATE_ARM;
1095 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1098 /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
1099 if ((armv4_5->core_mode != ARMV4_5_MODE_USR) && (armv4_5->core_mode != ARMV4_5_MODE_SYS))
1101 xscale_receive(target, buffer, 8);
1102 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, buffer[7]);
1103 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
1104 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
1108 /* r8 to r14, but no spsr */
1109 xscale_receive(target, buffer, 7);
1112 /* move data from buffer to register cache */
1113 for (i = 8; i <= 14; i++)
1115 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, buffer[i - 8]);
1116 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0;
1117 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
1120 /* examine debug reason */
1121 xscale_read_dcsr(target);
1122 moe = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 2, 3);
1124 /* stored PC (for calculating fixup) */
1125 pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1129 case 0x0: /* Processor reset */
1130 target->debug_reason = DBG_REASON_DBGRQ;
1131 xscale->arch_debug_reason = XSCALE_DBG_REASON_RESET;
1134 case 0x1: /* Instruction breakpoint hit */
1135 target->debug_reason = DBG_REASON_BREAKPOINT;
1136 xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
1139 case 0x2: /* Data breakpoint hit */
1140 target->debug_reason = DBG_REASON_WATCHPOINT;
1141 xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
1144 case 0x3: /* BKPT instruction executed */
1145 target->debug_reason = DBG_REASON_BREAKPOINT;
1146 xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
1149 case 0x4: /* Ext. debug event */
1150 target->debug_reason = DBG_REASON_DBGRQ;
1151 xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
1154 case 0x5: /* Vector trap occured */
1155 target->debug_reason = DBG_REASON_BREAKPOINT;
1156 xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
1159 case 0x6: /* Trace buffer full break */
1160 target->debug_reason = DBG_REASON_DBGRQ;
1161 xscale->arch_debug_reason = XSCALE_DBG_REASON_TB_FULL;
1164 case 0x7: /* Reserved */
1166 LOG_ERROR("Method of Entry is 'Reserved'");
1171 /* apply PC fixup */
1172 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, pc);
1174 /* on the first debug entry, identify cache type */
1175 if (xscale->armv4_5_mmu.armv4_5_cache.ctype == -1)
1179 /* read cp15 cache type register */
1180 xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CACHETYPE]);
1181 cache_type_reg = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CACHETYPE].value, 0, 32);
1183 armv4_5_identify_cache(cache_type_reg, &xscale->armv4_5_mmu.armv4_5_cache);
1186 /* examine MMU and Cache settings */
1187 /* read cp15 control register */
1188 xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
1189 xscale->cp15_control_reg = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
1190 xscale->armv4_5_mmu.mmu_enabled = (xscale->cp15_control_reg & 0x1U) ? 1 : 0;
1191 xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (xscale->cp15_control_reg & 0x4U) ? 1 : 0;
1192 xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (xscale->cp15_control_reg & 0x1000U) ? 1 : 0;
1194 /* tracing enabled, read collected trace data */
1195 if (xscale->trace.buffer_enabled)
1197 xscale_read_trace(target);
1198 xscale->trace.buffer_fill--;
1200 /* resume if we're still collecting trace data */
1201 if ((xscale->arch_debug_reason == XSCALE_DBG_REASON_TB_FULL)
1202 && (xscale->trace.buffer_fill > 0))
1204 xscale_resume(target, 1, 0x0, 1, 0);
1208 xscale->trace.buffer_enabled = 0;
1215 int xscale_halt(target_t *target)
1217 armv4_5_common_t *armv4_5 = target->arch_info;
1218 xscale_common_t *xscale = armv4_5->arch_info;
1220 LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
1222 if (target->state == TARGET_HALTED)
1224 LOG_DEBUG("target was already halted");
1227 else if (target->state == TARGET_UNKNOWN)
1229 /* this must not happen for a xscale target */
1230 LOG_ERROR("target was in unknown state when halt was requested");
1231 return ERROR_TARGET_INVALID;
1233 else if (target->state == TARGET_RESET)
1235 LOG_DEBUG("target->state == TARGET_RESET");
1239 /* assert external dbg break */
1240 xscale->external_debug_break = 1;
1241 xscale_read_dcsr(target);
1243 target->debug_reason = DBG_REASON_DBGRQ;
1249 int xscale_enable_single_step(struct target_s *target, u32 next_pc)
1251 armv4_5_common_t *armv4_5 = target->arch_info;
1252 xscale_common_t *xscale= armv4_5->arch_info;
1253 reg_t *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0];
1255 if (xscale->ibcr0_used)
1257 breakpoint_t *ibcr0_bp = breakpoint_find(target, buf_get_u32(ibcr0->value, 0, 32) & 0xfffffffe);
1261 xscale_unset_breakpoint(target, ibcr0_bp);
1265 LOG_ERROR("BUG: xscale->ibcr0_used is set, but no breakpoint with that address found");
1270 xscale_set_reg_u32(ibcr0, next_pc | 0x1);
1275 int xscale_disable_single_step(struct target_s *target)
1277 armv4_5_common_t *armv4_5 = target->arch_info;
1278 xscale_common_t *xscale= armv4_5->arch_info;
1279 reg_t *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0];
1281 xscale_set_reg_u32(ibcr0, 0x0);
1286 int xscale_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
1288 armv4_5_common_t *armv4_5 = target->arch_info;
1289 xscale_common_t *xscale= armv4_5->arch_info;
1290 breakpoint_t *breakpoint = target->breakpoints;
1299 if (target->state != TARGET_HALTED)
1301 LOG_WARNING("target not halted");
1302 return ERROR_TARGET_NOT_HALTED;
1305 if (!debug_execution)
1307 target_free_all_working_areas(target);
1310 /* update vector tables */
1311 if ((retval=xscale_update_vectors(target))!=ERROR_OK)
1314 /* current = 1: continue on current pc, otherwise continue at <address> */
1316 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1318 current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1320 /* if we're at the reset vector, we have to simulate the branch */
1321 if (current_pc == 0x0)
1323 arm_simulate_step(target, NULL);
1324 current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1327 /* the front-end may request us not to handle breakpoints */
1328 if (handle_breakpoints)
1330 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1334 /* there's a breakpoint at the current PC, we have to step over it */
1335 LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
1336 xscale_unset_breakpoint(target, breakpoint);
1338 /* calculate PC of next instruction */
1339 if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
1342 target_read_u32(target, current_pc, ¤t_opcode);
1343 LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode);
1346 LOG_DEBUG("enable single-step");
1347 xscale_enable_single_step(target, next_pc);
1349 /* restore banked registers */
1350 xscale_restore_context(target);
1352 /* send resume request (command 0x30 or 0x31)
1353 * clean the trace buffer if it is to be enabled (0x62) */
1354 if (xscale->trace.buffer_enabled)
1356 xscale_send_u32(target, 0x62);
1357 xscale_send_u32(target, 0x31);
1360 xscale_send_u32(target, 0x30);
1363 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1364 LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1366 for (i = 7; i >= 0; i--)
1369 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1370 LOG_DEBUG("writing r%i with value 0x%8.8x", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1374 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1375 LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1377 /* wait for and process debug entry */
1378 xscale_debug_entry(target);
1380 LOG_DEBUG("disable single-step");
1381 xscale_disable_single_step(target);
1383 LOG_DEBUG("set breakpoint at 0x%8.8x", breakpoint->address);
1384 xscale_set_breakpoint(target, breakpoint);
1388 /* enable any pending breakpoints and watchpoints */
1389 xscale_enable_breakpoints(target);
1390 xscale_enable_watchpoints(target);
1392 /* restore banked registers */
1393 xscale_restore_context(target);
1395 /* send resume request (command 0x30 or 0x31)
1396 * clean the trace buffer if it is to be enabled (0x62) */
1397 if (xscale->trace.buffer_enabled)
1399 xscale_send_u32(target, 0x62);
1400 xscale_send_u32(target, 0x31);
1403 xscale_send_u32(target, 0x30);
1406 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1407 LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1409 for (i = 7; i >= 0; i--)
1412 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1413 LOG_DEBUG("writing r%i with value 0x%8.8x", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1417 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1418 LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1420 target->debug_reason = DBG_REASON_NOTHALTED;
1422 if (!debug_execution)
1424 /* registers are now invalid */
1425 armv4_5_invalidate_core_regs(target);
1426 target->state = TARGET_RUNNING;
1427 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1431 target->state = TARGET_DEBUG_RUNNING;
1432 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
1435 LOG_DEBUG("target resumed");
1437 xscale->handler_running = 1;
1442 int xscale_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
1444 armv4_5_common_t *armv4_5 = target->arch_info;
1445 xscale_common_t *xscale = armv4_5->arch_info;
1446 breakpoint_t *breakpoint = target->breakpoints;
1448 u32 current_pc, next_pc;
1452 if (target->state != TARGET_HALTED)
1454 LOG_WARNING("target not halted");
1455 return ERROR_TARGET_NOT_HALTED;
1458 /* current = 1: continue on current pc, otherwise continue at <address> */
1460 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1462 current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1464 /* if we're at the reset vector, we have to simulate the step */
1465 if (current_pc == 0x0)
1467 arm_simulate_step(target, NULL);
1468 current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1470 target->debug_reason = DBG_REASON_SINGLESTEP;
1471 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1476 /* the front-end may request us not to handle breakpoints */
1477 if (handle_breakpoints)
1478 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1480 xscale_unset_breakpoint(target, breakpoint);
1483 target->debug_reason = DBG_REASON_SINGLESTEP;
1485 /* calculate PC of next instruction */
1486 if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
1489 target_read_u32(target, current_pc, ¤t_opcode);
1490 LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode);
1493 LOG_DEBUG("enable single-step");
1494 xscale_enable_single_step(target, next_pc);
1496 /* restore banked registers */
1497 xscale_restore_context(target);
1499 /* send resume request (command 0x30 or 0x31)
1500 * clean the trace buffer if it is to be enabled (0x62) */
1501 if (xscale->trace.buffer_enabled)
1503 xscale_send_u32(target, 0x62);
1504 xscale_send_u32(target, 0x31);
1507 xscale_send_u32(target, 0x30);
1510 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1511 LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1513 for (i = 7; i >= 0; i--)
1516 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1517 LOG_DEBUG("writing r%i with value 0x%8.8x", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1521 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1522 LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1524 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1526 /* registers are now invalid */
1527 armv4_5_invalidate_core_regs(target);
1529 /* wait for and process debug entry */
1530 xscale_debug_entry(target);
1532 LOG_DEBUG("disable single-step");
1533 xscale_disable_single_step(target);
1535 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1539 xscale_set_breakpoint(target, breakpoint);
1542 LOG_DEBUG("target stepped");
1548 int xscale_assert_reset(target_t *target)
1550 armv4_5_common_t *armv4_5 = target->arch_info;
1551 xscale_common_t *xscale = armv4_5->arch_info;
1553 LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
1555 /* select DCSR instruction (set endstate to R-T-I to ensure we don't
1556 * end up in T-L-R, which would reset JTAG
1558 jtag_add_end_state(TAP_RTI);
1559 xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dcsr);
1561 /* set Hold reset, Halt mode and Trap Reset */
1562 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
1563 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1);
1564 xscale_write_dcsr(target, 1, 0);
1566 /* select BYPASS, because having DCSR selected caused problems on the PXA27x */
1567 xscale_jtag_set_instr(xscale->jtag_info.chain_pos, 0x7f);
1568 jtag_execute_queue();
1571 jtag_add_reset(0, 1);
1573 /* sleep 1ms, to be sure we fulfill any requirements */
1574 jtag_add_sleep(1000);
1575 jtag_execute_queue();
1577 target->state = TARGET_RESET;
1582 int xscale_deassert_reset(target_t *target)
1584 armv4_5_common_t *armv4_5 = target->arch_info;
1585 xscale_common_t *xscale = armv4_5->arch_info;
1587 fileio_t debug_handler;
1595 breakpoint_t *breakpoint = target->breakpoints;
1599 xscale->ibcr_available = 2;
1600 xscale->ibcr0_used = 0;
1601 xscale->ibcr1_used = 0;
1603 xscale->dbr_available = 2;
1604 xscale->dbr0_used = 0;
1605 xscale->dbr1_used = 0;
1607 /* mark all hardware breakpoints as unset */
1610 if (breakpoint->type == BKPT_HARD)
1612 breakpoint->set = 0;
1614 breakpoint = breakpoint->next;
1617 if (!xscale->handler_installed)
1620 jtag_add_reset(0, 0);
1622 /* wait 300ms; 150 and 100ms were not enough */
1623 jtag_add_sleep(300*1000);
1625 jtag_add_runtest(2030, TAP_RTI);
1626 jtag_execute_queue();
1628 /* set Hold reset, Halt mode and Trap Reset */
1629 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
1630 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1);
1631 xscale_write_dcsr(target, 1, 0);
1633 /* Load debug handler */
1634 if (fileio_open(&debug_handler, "xscale/debug_handler.bin", FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1639 if ((binary_size = debug_handler.size) % 4)
1641 LOG_ERROR("debug_handler.bin: size not a multiple of 4");
1645 if (binary_size > 0x800)
1647 LOG_ERROR("debug_handler.bin: larger than 2kb");
1651 binary_size = CEIL(binary_size, 32) * 32;
1653 address = xscale->handler_address;
1654 while (binary_size > 0)
1659 if ((retval = fileio_read(&debug_handler, 32, buffer, &buf_cnt)) != ERROR_OK)
1664 for (i = 0; i < buf_cnt; i += 4)
1666 /* convert LE buffer to host-endian u32 */
1667 cache_line[i / 4] = le_to_h_u32(&buffer[i]);
1670 for (; buf_cnt < 32; buf_cnt += 4)
1672 cache_line[buf_cnt / 4] = 0xe1a08008;
1675 /* only load addresses other than the reset vectors */
1676 if ((address % 0x400) != 0x0)
1678 xscale_load_ic(target, 1, address, cache_line);
1682 binary_size -= buf_cnt;
1685 xscale_load_ic(target, 1, 0x0, xscale->low_vectors);
1686 xscale_load_ic(target, 1, 0xffff0000, xscale->high_vectors);
1688 jtag_add_runtest(30, TAP_RTI);
1690 jtag_add_sleep(100000);
1692 /* set Hold reset, Halt mode and Trap Reset */
1693 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
1694 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1);
1695 xscale_write_dcsr(target, 1, 0);
1697 /* clear Hold reset to let the target run (should enter debug handler) */
1698 xscale_write_dcsr(target, 0, 1);
1699 target->state = TARGET_RUNNING;
1701 if ((target->reset_mode != RESET_HALT) && (target->reset_mode != RESET_INIT))
1703 jtag_add_sleep(10000);
1705 /* we should have entered debug now */
1706 xscale_debug_entry(target);
1707 target->state = TARGET_HALTED;
1709 /* resume the target */
1710 xscale_resume(target, 1, 0x0, 1, 0);
1713 fileio_close(&debug_handler);
1717 jtag_add_reset(0, 0);
1724 int xscale_soft_reset_halt(struct target_s *target)
1730 int xscale_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode)
1736 int xscale_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, u32 value)
1742 int xscale_full_context(target_t *target)
1744 armv4_5_common_t *armv4_5 = target->arch_info;
1752 if (target->state != TARGET_HALTED)
1754 LOG_WARNING("target not halted");
1755 return ERROR_TARGET_NOT_HALTED;
1758 buffer = malloc(4 * 8);
1760 /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
1761 * we can't enter User mode on an XScale (unpredictable),
1762 * but User shares registers with SYS
1764 for(i = 1; i < 7; i++)
1768 /* check if there are invalid registers in the current mode
1770 for (j = 0; j <= 16; j++)
1772 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1780 /* request banked registers */
1781 xscale_send_u32(target, 0x0);
1784 tmp_cpsr |= armv4_5_number_to_mode(i);
1785 tmp_cpsr |= 0xc0; /* I/F bits */
1787 /* send CPSR for desired mode */
1788 xscale_send_u32(target, tmp_cpsr);
1790 /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
1791 if ((armv4_5_number_to_mode(i) != ARMV4_5_MODE_USR) && (armv4_5_number_to_mode(i) != ARMV4_5_MODE_SYS))
1793 xscale_receive(target, buffer, 8);
1794 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, buffer[7]);
1795 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
1796 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1;
1800 xscale_receive(target, buffer, 7);
1803 /* move data from buffer to register cache */
1804 for (j = 8; j <= 14; j++)
1806 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value, 0, 32, buffer[j - 8]);
1807 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
1808 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1;
1818 int xscale_restore_context(target_t *target)
1820 armv4_5_common_t *armv4_5 = target->arch_info;
1826 if (target->state != TARGET_HALTED)
1828 LOG_WARNING("target not halted");
1829 return ERROR_TARGET_NOT_HALTED;
1832 /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
1833 * we can't enter User mode on an XScale (unpredictable),
1834 * but User shares registers with SYS
1836 for(i = 1; i < 7; i++)
1840 /* check if there are invalid registers in the current mode
1842 for (j = 8; j <= 14; j++)
1844 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty == 1)
1848 /* if not USR/SYS, check if the SPSR needs to be written */
1849 if ((armv4_5_number_to_mode(i) != ARMV4_5_MODE_USR) && (armv4_5_number_to_mode(i) != ARMV4_5_MODE_SYS))
1851 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty == 1)
1859 /* send banked registers */
1860 xscale_send_u32(target, 0x1);
1863 tmp_cpsr |= armv4_5_number_to_mode(i);
1864 tmp_cpsr |= 0xc0; /* I/F bits */
1866 /* send CPSR for desired mode */
1867 xscale_send_u32(target, tmp_cpsr);
1869 /* send banked registers, r8 to r14, and spsr if not in USR/SYS mode */
1870 for (j = 8; j <= 14; j++)
1872 xscale_send_u32(target, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, j).value, 0, 32));
1873 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
1876 if ((armv4_5_number_to_mode(i) != ARMV4_5_MODE_USR) && (armv4_5_number_to_mode(i) != ARMV4_5_MODE_SYS))
1878 xscale_send_u32(target, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32));
1879 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
1887 int xscale_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1889 armv4_5_common_t *armv4_5 = target->arch_info;
1890 xscale_common_t *xscale = armv4_5->arch_info;
1895 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1897 if (target->state != TARGET_HALTED)
1899 LOG_WARNING("target not halted");
1900 return ERROR_TARGET_NOT_HALTED;
1903 /* sanitize arguments */
1904 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1905 return ERROR_INVALID_ARGUMENTS;
1907 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1908 return ERROR_TARGET_UNALIGNED_ACCESS;
1910 /* send memory read request (command 0x1n, n: access size) */
1911 if ((retval=xscale_send_u32(target, 0x10 | size))!=ERROR_OK)
1914 /* send base address for read request */
1915 if ((retval=xscale_send_u32(target, address))!=ERROR_OK)
1918 /* send number of requested data words */
1919 if ((retval=xscale_send_u32(target, count))!=ERROR_OK)
1922 /* receive data from target (count times 32-bit words in host endianness) */
1923 buf32 = malloc(4 * count);
1924 if ((retval=xscale_receive(target, buf32, count))!=ERROR_OK)
1927 /* extract data from host-endian buffer into byte stream */
1928 for (i = 0; i < count; i++)
1933 target_buffer_set_u32(target, buffer, buf32[i]);
1937 target_buffer_set_u16(target, buffer, buf32[i] & 0xffff);
1941 *buffer++ = buf32[i] & 0xff;
1944 LOG_ERROR("should never get here");
1951 /* examine DCSR, to see if Sticky Abort (SA) got set */
1952 if ((retval=xscale_read_dcsr(target))!=ERROR_OK)
1954 if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1)
1957 if ((retval=xscale_send_u32(target, 0x60))!=ERROR_OK)
1960 return ERROR_TARGET_DATA_ABORT;
1966 int xscale_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1968 armv4_5_common_t *armv4_5 = target->arch_info;
1969 xscale_common_t *xscale = armv4_5->arch_info;
1972 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1974 if (target->state != TARGET_HALTED)
1976 LOG_WARNING("target not halted");
1977 return ERROR_TARGET_NOT_HALTED;
1980 /* sanitize arguments */
1981 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1982 return ERROR_INVALID_ARGUMENTS;
1984 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1985 return ERROR_TARGET_UNALIGNED_ACCESS;
1987 /* send memory write request (command 0x2n, n: access size) */
1988 if ((retval=xscale_send_u32(target, 0x20 | size))!=ERROR_OK)
1991 /* send base address for read request */
1992 if ((retval=xscale_send_u32(target, address))!=ERROR_OK)
1995 /* send number of requested data words to be written*/
1996 if ((retval=xscale_send_u32(target, count))!=ERROR_OK)
1999 /* extract data from host-endian buffer into byte stream */
2001 for (i = 0; i < count; i++)
2006 value = target_buffer_get_u32(target, buffer);
2007 xscale_send_u32(target, value);
2011 value = target_buffer_get_u16(target, buffer);
2012 xscale_send_u32(target, value);
2017 xscale_send_u32(target, value);
2021 LOG_ERROR("should never get here");
2026 if ((retval=xscale_send(target, buffer, count, size))!=ERROR_OK)
2029 /* examine DCSR, to see if Sticky Abort (SA) got set */
2030 if ((retval=xscale_read_dcsr(target))!=ERROR_OK)
2032 if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1)
2035 if ((retval=xscale_send_u32(target, 0x60))!=ERROR_OK)
2038 return ERROR_TARGET_DATA_ABORT;
2044 int xscale_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
2046 return xscale_write_memory(target, address, 4, count, buffer);
2049 int xscale_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
2051 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2054 u32 xscale_get_ttb(target_t *target)
2056 armv4_5_common_t *armv4_5 = target->arch_info;
2057 xscale_common_t *xscale = armv4_5->arch_info;
2060 xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_TTB]);
2061 ttb = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_TTB].value, 0, 32);
2066 void xscale_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
2068 armv4_5_common_t *armv4_5 = target->arch_info;
2069 xscale_common_t *xscale = armv4_5->arch_info;
2072 /* read cp15 control register */
2073 xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
2074 cp15_control = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
2077 cp15_control &= ~0x1U;
2082 xscale_send_u32(target, 0x50);
2083 xscale_send_u32(target, xscale->cache_clean_address);
2085 /* invalidate DCache */
2086 xscale_send_u32(target, 0x51);
2088 cp15_control &= ~0x4U;
2093 /* invalidate ICache */
2094 xscale_send_u32(target, 0x52);
2095 cp15_control &= ~0x1000U;
2098 /* write new cp15 control register */
2099 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_CTRL], cp15_control);
2101 /* execute cpwait to ensure outstanding operations complete */
2102 xscale_send_u32(target, 0x53);
2105 void xscale_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
2107 armv4_5_common_t *armv4_5 = target->arch_info;
2108 xscale_common_t *xscale = armv4_5->arch_info;
2111 /* read cp15 control register */
2112 xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
2113 cp15_control = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
2116 cp15_control |= 0x1U;
2119 cp15_control |= 0x4U;
2122 cp15_control |= 0x1000U;
2124 /* write new cp15 control register */
2125 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_CTRL], cp15_control);
2127 /* execute cpwait to ensure outstanding operations complete */
2128 xscale_send_u32(target, 0x53);
2131 int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
2133 armv4_5_common_t *armv4_5 = target->arch_info;
2134 xscale_common_t *xscale = armv4_5->arch_info;
2136 if (target->state != TARGET_HALTED)
2138 LOG_WARNING("target not halted");
2139 return ERROR_TARGET_NOT_HALTED;
2142 if (xscale->force_hw_bkpts)
2143 breakpoint->type = BKPT_HARD;
2145 if (breakpoint->set)
2147 LOG_WARNING("breakpoint already set");
2151 if (breakpoint->type == BKPT_HARD)
2153 u32 value = breakpoint->address | 1;
2154 if (!xscale->ibcr0_used)
2156 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR0], value);
2157 xscale->ibcr0_used = 1;
2158 breakpoint->set = 1; /* breakpoint set on first breakpoint register */
2160 else if (!xscale->ibcr1_used)
2162 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR1], value);
2163 xscale->ibcr1_used = 1;
2164 breakpoint->set = 2; /* breakpoint set on second breakpoint register */
2168 LOG_ERROR("BUG: no hardware comparator available");
2172 else if (breakpoint->type == BKPT_SOFT)
2174 if (breakpoint->length == 4)
2176 /* keep the original instruction in target endianness */
2177 target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
2178 /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
2179 target_write_u32(target, breakpoint->address, xscale->arm_bkpt);
2183 /* keep the original instruction in target endianness */
2184 target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
2185 /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
2186 target_write_u32(target, breakpoint->address, xscale->thumb_bkpt);
2188 breakpoint->set = 1;
2195 int xscale_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
2197 armv4_5_common_t *armv4_5 = target->arch_info;
2198 xscale_common_t *xscale = armv4_5->arch_info;
2200 if (target->state != TARGET_HALTED)
2202 LOG_WARNING("target not halted");
2203 return ERROR_TARGET_NOT_HALTED;
2206 if (xscale->force_hw_bkpts)
2208 LOG_DEBUG("forcing use of hardware breakpoint at address 0x%8.8x", breakpoint->address);
2209 breakpoint->type = BKPT_HARD;
2212 if ((breakpoint->type == BKPT_HARD) && (xscale->ibcr_available < 1))
2214 LOG_INFO("no breakpoint unit available for hardware breakpoint");
2215 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2219 xscale->ibcr_available--;
2222 if ((breakpoint->length != 2) && (breakpoint->length != 4))
2224 LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
2225 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2231 int xscale_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
2233 armv4_5_common_t *armv4_5 = target->arch_info;
2234 xscale_common_t *xscale = armv4_5->arch_info;
2236 if (target->state != TARGET_HALTED)
2238 LOG_WARNING("target not halted");
2239 return ERROR_TARGET_NOT_HALTED;
2242 if (!breakpoint->set)
2244 LOG_WARNING("breakpoint not set");
2248 if (breakpoint->type == BKPT_HARD)
2250 if (breakpoint->set == 1)
2252 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR0], 0x0);
2253 xscale->ibcr0_used = 0;
2255 else if (breakpoint->set == 2)
2257 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR1], 0x0);
2258 xscale->ibcr1_used = 0;
2260 breakpoint->set = 0;
2264 /* restore original instruction (kept in target endianness) */
2265 if (breakpoint->length == 4)
2267 target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
2271 target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
2273 breakpoint->set = 0;
2279 int xscale_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
2281 armv4_5_common_t *armv4_5 = target->arch_info;
2282 xscale_common_t *xscale = armv4_5->arch_info;
2284 if (target->state != TARGET_HALTED)
2286 LOG_WARNING("target not halted");
2287 return ERROR_TARGET_NOT_HALTED;
2290 if (breakpoint->set)
2292 xscale_unset_breakpoint(target, breakpoint);
2295 if (breakpoint->type == BKPT_HARD)
2296 xscale->ibcr_available++;
2301 int xscale_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
2303 armv4_5_common_t *armv4_5 = target->arch_info;
2304 xscale_common_t *xscale = armv4_5->arch_info;
2306 reg_t *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON];
2307 u32 dbcon_value = buf_get_u32(dbcon->value, 0, 32);
2309 if (target->state != TARGET_HALTED)
2311 LOG_WARNING("target not halted");
2312 return ERROR_TARGET_NOT_HALTED;
2315 xscale_get_reg(dbcon);
2317 switch (watchpoint->rw)
2329 LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
2332 if (!xscale->dbr0_used)
2334 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_DBR0], watchpoint->address);
2335 dbcon_value |= enable;
2336 xscale_set_reg_u32(dbcon, dbcon_value);
2337 watchpoint->set = 1;
2338 xscale->dbr0_used = 1;
2340 else if (!xscale->dbr1_used)
2342 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_DBR1], watchpoint->address);
2343 dbcon_value |= enable << 2;
2344 xscale_set_reg_u32(dbcon, dbcon_value);
2345 watchpoint->set = 2;
2346 xscale->dbr1_used = 1;
2350 LOG_ERROR("BUG: no hardware comparator available");
2357 int xscale_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
2359 armv4_5_common_t *armv4_5 = target->arch_info;
2360 xscale_common_t *xscale = armv4_5->arch_info;
2362 if (target->state != TARGET_HALTED)
2364 LOG_WARNING("target not halted");
2365 return ERROR_TARGET_NOT_HALTED;
2368 if (xscale->dbr_available < 1)
2370 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2373 if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4))
2375 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2378 xscale->dbr_available--;
2383 int xscale_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
2385 armv4_5_common_t *armv4_5 = target->arch_info;
2386 xscale_common_t *xscale = armv4_5->arch_info;
2387 reg_t *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON];
2388 u32 dbcon_value = buf_get_u32(dbcon->value, 0, 32);
2390 if (target->state != TARGET_HALTED)
2392 LOG_WARNING("target not halted");
2393 return ERROR_TARGET_NOT_HALTED;
2396 if (!watchpoint->set)
2398 LOG_WARNING("breakpoint not set");
2402 if (watchpoint->set == 1)
2404 dbcon_value &= ~0x3;
2405 xscale_set_reg_u32(dbcon, dbcon_value);
2406 xscale->dbr0_used = 0;
2408 else if (watchpoint->set == 2)
2410 dbcon_value &= ~0xc;
2411 xscale_set_reg_u32(dbcon, dbcon_value);
2412 xscale->dbr1_used = 0;
2414 watchpoint->set = 0;
2419 int xscale_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
2421 armv4_5_common_t *armv4_5 = target->arch_info;
2422 xscale_common_t *xscale = armv4_5->arch_info;
2424 if (target->state != TARGET_HALTED)
2426 LOG_WARNING("target not halted");
2427 return ERROR_TARGET_NOT_HALTED;
2430 if (watchpoint->set)
2432 xscale_unset_watchpoint(target, watchpoint);
2435 xscale->dbr_available++;
2440 void xscale_enable_watchpoints(struct target_s *target)
2442 watchpoint_t *watchpoint = target->watchpoints;
2446 if (watchpoint->set == 0)
2447 xscale_set_watchpoint(target, watchpoint);
2448 watchpoint = watchpoint->next;
2452 void xscale_enable_breakpoints(struct target_s *target)
2454 breakpoint_t *breakpoint = target->breakpoints;
2456 /* set any pending breakpoints */
2459 if (breakpoint->set == 0)
2460 xscale_set_breakpoint(target, breakpoint);
2461 breakpoint = breakpoint->next;
2465 int xscale_get_reg(reg_t *reg)
2467 xscale_reg_t *arch_info = reg->arch_info;
2468 target_t *target = arch_info->target;
2469 armv4_5_common_t *armv4_5 = target->arch_info;
2470 xscale_common_t *xscale = armv4_5->arch_info;
2472 /* DCSR, TX and RX are accessible via JTAG */
2473 if (strcmp(reg->name, "XSCALE_DCSR") == 0)
2475 return xscale_read_dcsr(arch_info->target);
2477 else if (strcmp(reg->name, "XSCALE_TX") == 0)
2479 /* 1 = consume register content */
2480 return xscale_read_tx(arch_info->target, 1);
2482 else if (strcmp(reg->name, "XSCALE_RX") == 0)
2484 /* can't read from RX register (host -> debug handler) */
2487 else if (strcmp(reg->name, "XSCALE_TXRXCTRL") == 0)
2489 /* can't (explicitly) read from TXRXCTRL register */
2492 else /* Other DBG registers have to be transfered by the debug handler */
2494 /* send CP read request (command 0x40) */
2495 xscale_send_u32(target, 0x40);
2497 /* send CP register number */
2498 xscale_send_u32(target, arch_info->dbg_handler_number);
2500 /* read register value */
2501 xscale_read_tx(target, 1);
2502 buf_cpy(xscale->reg_cache->reg_list[XSCALE_TX].value, reg->value, 32);
2511 int xscale_set_reg(reg_t *reg, u8* buf)
2513 xscale_reg_t *arch_info = reg->arch_info;
2514 target_t *target = arch_info->target;
2515 armv4_5_common_t *armv4_5 = target->arch_info;
2516 xscale_common_t *xscale = armv4_5->arch_info;
2517 u32 value = buf_get_u32(buf, 0, 32);
2519 /* DCSR, TX and RX are accessible via JTAG */
2520 if (strcmp(reg->name, "XSCALE_DCSR") == 0)
2522 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 0, 32, value);
2523 return xscale_write_dcsr(arch_info->target, -1, -1);
2525 else if (strcmp(reg->name, "XSCALE_RX") == 0)
2527 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_RX].value, 0, 32, value);
2528 return xscale_write_rx(arch_info->target);
2530 else if (strcmp(reg->name, "XSCALE_TX") == 0)
2532 /* can't write to TX register (debug-handler -> host) */
2535 else if (strcmp(reg->name, "XSCALE_TXRXCTRL") == 0)
2537 /* can't (explicitly) write to TXRXCTRL register */
2540 else /* Other DBG registers have to be transfered by the debug handler */
2542 /* send CP write request (command 0x41) */
2543 xscale_send_u32(target, 0x41);
2545 /* send CP register number */
2546 xscale_send_u32(target, arch_info->dbg_handler_number);
2548 /* send CP register value */
2549 xscale_send_u32(target, value);
2550 buf_set_u32(reg->value, 0, 32, value);
2556 /* convenience wrapper to access XScale specific registers */
2557 int xscale_set_reg_u32(reg_t *reg, u32 value)
2561 buf_set_u32(buf, 0, 32, value);
2563 return xscale_set_reg(reg, buf);
2566 int xscale_write_dcsr_sw(target_t *target, u32 value)
2568 /* get pointers to arch-specific information */
2569 armv4_5_common_t *armv4_5 = target->arch_info;
2570 xscale_common_t *xscale = armv4_5->arch_info;
2571 reg_t *dcsr = &xscale->reg_cache->reg_list[XSCALE_DCSR];
2572 xscale_reg_t *dcsr_arch_info = dcsr->arch_info;
2574 /* send CP write request (command 0x41) */
2575 xscale_send_u32(target, 0x41);
2577 /* send CP register number */
2578 xscale_send_u32(target, dcsr_arch_info->dbg_handler_number);
2580 /* send CP register value */
2581 xscale_send_u32(target, value);
2582 buf_set_u32(dcsr->value, 0, 32, value);
2587 int xscale_read_trace(target_t *target)
2589 /* get pointers to arch-specific information */
2590 armv4_5_common_t *armv4_5 = target->arch_info;
2591 xscale_common_t *xscale = armv4_5->arch_info;
2592 xscale_trace_data_t **trace_data_p;
2594 /* 258 words from debug handler
2595 * 256 trace buffer entries
2596 * 2 checkpoint addresses
2598 u32 trace_buffer[258];
2599 int is_address[256];
2602 if (target->state != TARGET_HALTED)
2604 LOG_WARNING("target must be stopped to read trace data");
2605 return ERROR_TARGET_NOT_HALTED;
2608 /* send read trace buffer command (command 0x61) */
2609 xscale_send_u32(target, 0x61);
2611 /* receive trace buffer content */
2612 xscale_receive(target, trace_buffer, 258);
2614 /* parse buffer backwards to identify address entries */
2615 for (i = 255; i >= 0; i--)
2618 if (((trace_buffer[i] & 0xf0) == 0x90) ||
2619 ((trace_buffer[i] & 0xf0) == 0xd0))
2622 is_address[--i] = 1;
2624 is_address[--i] = 1;
2626 is_address[--i] = 1;
2628 is_address[--i] = 1;
2633 /* search first non-zero entry */
2634 for (j = 0; (j < 256) && (trace_buffer[j] == 0) && (!is_address[j]); j++)
2639 LOG_DEBUG("no trace data collected");
2640 return ERROR_XSCALE_NO_TRACE_DATA;
2643 for (trace_data_p = &xscale->trace.data; *trace_data_p; trace_data_p = &(*trace_data_p)->next)
2646 *trace_data_p = malloc(sizeof(xscale_trace_data_t));
2647 (*trace_data_p)->next = NULL;
2648 (*trace_data_p)->chkpt0 = trace_buffer[256];
2649 (*trace_data_p)->chkpt1 = trace_buffer[257];
2650 (*trace_data_p)->last_instruction = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
2651 (*trace_data_p)->entries = malloc(sizeof(xscale_trace_entry_t) * (256 - j));
2652 (*trace_data_p)->depth = 256 - j;
2654 for (i = j; i < 256; i++)
2656 (*trace_data_p)->entries[i - j].data = trace_buffer[i];
2658 (*trace_data_p)->entries[i - j].type = XSCALE_TRACE_ADDRESS;
2660 (*trace_data_p)->entries[i - j].type = XSCALE_TRACE_MESSAGE;
2666 int xscale_read_instruction(target_t *target, arm_instruction_t *instruction)
2668 /* get pointers to arch-specific information */
2669 armv4_5_common_t *armv4_5 = target->arch_info;
2670 xscale_common_t *xscale = armv4_5->arch_info;
2677 if (!xscale->trace.image)
2678 return ERROR_TRACE_IMAGE_UNAVAILABLE;
2680 /* search for the section the current instruction belongs to */
2681 for (i = 0; i < xscale->trace.image->num_sections; i++)
2683 if ((xscale->trace.image->sections[i].base_address <= xscale->trace.current_pc) &&
2684 (xscale->trace.image->sections[i].base_address + xscale->trace.image->sections[i].size > xscale->trace.current_pc))
2693 /* current instruction couldn't be found in the image */
2694 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
2697 if (xscale->trace.core_state == ARMV4_5_STATE_ARM)
2700 if ((retval = image_read_section(xscale->trace.image, section,
2701 xscale->trace.current_pc - xscale->trace.image->sections[section].base_address,
2702 4, buf, &size_read)) != ERROR_OK)
2704 LOG_ERROR("error while reading instruction: %i", retval);
2705 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
2707 opcode = target_buffer_get_u32(target, buf);
2708 arm_evaluate_opcode(opcode, xscale->trace.current_pc, instruction);
2710 else if (xscale->trace.core_state == ARMV4_5_STATE_THUMB)
2713 if ((retval = image_read_section(xscale->trace.image, section,
2714 xscale->trace.current_pc - xscale->trace.image->sections[section].base_address,
2715 2, buf, &size_read)) != ERROR_OK)
2717 LOG_ERROR("error while reading instruction: %i", retval);
2718 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
2720 opcode = target_buffer_get_u16(target, buf);
2721 thumb_evaluate_opcode(opcode, xscale->trace.current_pc, instruction);
2725 LOG_ERROR("BUG: unknown core state encountered");
2732 int xscale_branch_address(xscale_trace_data_t *trace_data, int i, u32 *target)
2734 /* if there are less than four entries prior to the indirect branch message
2735 * we can't extract the address */
2741 *target = (trace_data->entries[i-1].data) | (trace_data->entries[i-2].data << 8) |
2742 (trace_data->entries[i-3].data << 16) | (trace_data->entries[i-4].data << 24);
2747 int xscale_analyze_trace(target_t *target, command_context_t *cmd_ctx)
2749 /* get pointers to arch-specific information */
2750 armv4_5_common_t *armv4_5 = target->arch_info;
2751 xscale_common_t *xscale = armv4_5->arch_info;
2754 xscale_trace_data_t *trace_data = xscale->trace.data;
2763 xscale->trace.core_state = ARMV4_5_STATE_ARM;
2768 for (i = 0; i < trace_data->depth; i++)
2774 if (trace_data->entries[i].type == XSCALE_TRACE_ADDRESS)
2777 switch ((trace_data->entries[i].data & 0xf0) >> 4)
2779 case 0: /* Exceptions */
2787 exception = (trace_data->entries[i].data & 0x70) >> 4;
2789 next_pc = (trace_data->entries[i].data & 0xf0) >> 2;
2790 command_print(cmd_ctx, "--- exception %i ---", (trace_data->entries[i].data & 0xf0) >> 4);
2792 case 8: /* Direct Branch */
2795 case 9: /* Indirect Branch */
2797 if (xscale_branch_address(trace_data, i, &next_pc) == 0)
2802 case 13: /* Checkpointed Indirect Branch */
2803 if (xscale_branch_address(trace_data, i, &next_pc) == 0)
2806 if (((chkpt == 0) && (next_pc != trace_data->chkpt0))
2807 || ((chkpt == 1) && (next_pc != trace_data->chkpt1)))
2808 LOG_WARNING("checkpointed indirect branch target address doesn't match checkpoint");
2810 /* explicit fall-through */
2811 case 12: /* Checkpointed Direct Branch */
2816 next_pc = trace_data->chkpt0;
2819 else if (chkpt == 1)
2822 next_pc = trace_data->chkpt0;
2827 LOG_WARNING("more than two checkpointed branches encountered");
2830 case 15: /* Roll-over */
2833 default: /* Reserved */
2834 command_print(cmd_ctx, "--- reserved trace message ---");
2835 LOG_ERROR("BUG: trace message %i is reserved", (trace_data->entries[i].data & 0xf0) >> 4);
2839 if (xscale->trace.pc_ok)
2841 int executed = (trace_data->entries[i].data & 0xf) + rollover * 16;
2842 arm_instruction_t instruction;
2844 if ((exception == 6) || (exception == 7))
2846 /* IRQ or FIQ exception, no instruction executed */
2850 while (executed-- >= 0)
2852 if ((retval = xscale_read_instruction(target, &instruction)) != ERROR_OK)
2854 /* can't continue tracing with no image available */
2855 if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
2859 else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE)
2861 /* TODO: handle incomplete images */
2865 /* a precise abort on a load to the PC is included in the incremental
2866 * word count, other instructions causing data aborts are not included
2868 if ((executed == 0) && (exception == 4)
2869 && ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_LDM)))
2871 if ((instruction.type == ARM_LDM)
2872 && ((instruction.info.load_store_multiple.register_list & 0x8000) == 0))
2876 else if (((instruction.type >= ARM_LDR) && (instruction.type <= ARM_LDRSH))
2877 && (instruction.info.load_store.Rd != 15))
2883 /* only the last instruction executed
2884 * (the one that caused the control flow change)
2885 * could be a taken branch
2887 if (((executed == -1) && (branch == 1)) &&
2888 (((instruction.type == ARM_B) ||
2889 (instruction.type == ARM_BL) ||
2890 (instruction.type == ARM_BLX)) &&
2891 (instruction.info.b_bl_bx_blx.target_address != -1)))
2893 xscale->trace.current_pc = instruction.info.b_bl_bx_blx.target_address;
2897 xscale->trace.current_pc += (xscale->trace.core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
2899 command_print(cmd_ctx, "%s", instruction.text);
2907 xscale->trace.current_pc = next_pc;
2908 xscale->trace.pc_ok = 1;
2912 for (; xscale->trace.current_pc < trace_data->last_instruction; xscale->trace.current_pc += (xscale->trace.core_state == ARMV4_5_STATE_ARM) ? 4 : 2)
2914 arm_instruction_t instruction;
2915 if ((retval = xscale_read_instruction(target, &instruction)) != ERROR_OK)
2917 /* can't continue tracing with no image available */
2918 if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
2922 else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE)
2924 /* TODO: handle incomplete images */
2927 command_print(cmd_ctx, "%s", instruction.text);
2930 trace_data = trace_data->next;
2936 void xscale_build_reg_cache(target_t *target)
2938 /* get pointers to arch-specific information */
2939 armv4_5_common_t *armv4_5 = target->arch_info;
2940 xscale_common_t *xscale = armv4_5->arch_info;
2942 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
2943 xscale_reg_t *arch_info = malloc(sizeof(xscale_reg_arch_info));
2945 int num_regs = sizeof(xscale_reg_arch_info) / sizeof(xscale_reg_t);
2947 (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
2948 armv4_5->core_cache = (*cache_p);
2950 /* register a register arch-type for XScale dbg registers only once */
2951 if (xscale_reg_arch_type == -1)
2952 xscale_reg_arch_type = register_reg_arch_type(xscale_get_reg, xscale_set_reg);
2954 (*cache_p)->next = malloc(sizeof(reg_cache_t));
2955 cache_p = &(*cache_p)->next;
2957 /* fill in values for the xscale reg cache */
2958 (*cache_p)->name = "XScale registers";
2959 (*cache_p)->next = NULL;
2960 (*cache_p)->reg_list = malloc(num_regs * sizeof(reg_t));
2961 (*cache_p)->num_regs = num_regs;
2963 for (i = 0; i < num_regs; i++)
2965 (*cache_p)->reg_list[i].name = xscale_reg_list[i];
2966 (*cache_p)->reg_list[i].value = calloc(4, 1);
2967 (*cache_p)->reg_list[i].dirty = 0;
2968 (*cache_p)->reg_list[i].valid = 0;
2969 (*cache_p)->reg_list[i].size = 32;
2970 (*cache_p)->reg_list[i].bitfield_desc = NULL;
2971 (*cache_p)->reg_list[i].num_bitfields = 0;
2972 (*cache_p)->reg_list[i].arch_info = &arch_info[i];
2973 (*cache_p)->reg_list[i].arch_type = xscale_reg_arch_type;
2974 arch_info[i] = xscale_reg_arch_info[i];
2975 arch_info[i].target = target;
2978 xscale->reg_cache = (*cache_p);
2981 int xscale_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
2992 int xscale_init_arch_info(target_t *target, xscale_common_t *xscale, int chain_pos, char *variant)
2994 armv4_5_common_t *armv4_5;
2995 u32 high_reset_branch, low_reset_branch;
2998 armv4_5 = &xscale->armv4_5_common;
3000 /* store architecture specfic data (none so far) */
3001 xscale->arch_info = NULL;
3002 xscale->common_magic = XSCALE_COMMON_MAGIC;
3004 /* remember the variant (PXA25x, PXA27x, IXP42x, ...) */
3005 xscale->variant = strdup(variant);
3007 /* prepare JTAG information for the new target */
3008 xscale->jtag_info.chain_pos = chain_pos;
3010 xscale->jtag_info.dbgrx = 0x02;
3011 xscale->jtag_info.dbgtx = 0x10;
3012 xscale->jtag_info.dcsr = 0x09;
3013 xscale->jtag_info.ldic = 0x07;
3015 if ((strcmp(xscale->variant, "pxa250") == 0) ||
3016 (strcmp(xscale->variant, "pxa255") == 0) ||
3017 (strcmp(xscale->variant, "pxa26x") == 0))
3019 xscale->jtag_info.ir_length = 5;
3021 else if ((strcmp(xscale->variant, "pxa27x") == 0) ||
3022 (strcmp(xscale->variant, "ixp42x") == 0) ||
3023 (strcmp(xscale->variant, "ixp45x") == 0) ||
3024 (strcmp(xscale->variant, "ixp46x") == 0))
3026 xscale->jtag_info.ir_length = 7;
3029 /* the debug handler isn't installed (and thus not running) at this time */
3030 xscale->handler_installed = 0;
3031 xscale->handler_running = 0;
3032 xscale->handler_address = 0xfe000800;
3034 /* clear the vectors we keep locally for reference */
3035 memset(xscale->low_vectors, 0, sizeof(xscale->low_vectors));
3036 memset(xscale->high_vectors, 0, sizeof(xscale->high_vectors));
3038 /* no user-specified vectors have been configured yet */
3039 xscale->static_low_vectors_set = 0x0;
3040 xscale->static_high_vectors_set = 0x0;
3042 /* calculate branches to debug handler */
3043 low_reset_branch = (xscale->handler_address + 0x20 - 0x0 - 0x8) >> 2;
3044 high_reset_branch = (xscale->handler_address + 0x20 - 0xffff0000 - 0x8) >> 2;
3046 xscale->low_vectors[0] = ARMV4_5_B((low_reset_branch & 0xffffff), 0);
3047 xscale->high_vectors[0] = ARMV4_5_B((high_reset_branch & 0xffffff), 0);
3049 for (i = 1; i <= 7; i++)
3051 xscale->low_vectors[i] = ARMV4_5_B(0xfffffe, 0);
3052 xscale->high_vectors[i] = ARMV4_5_B(0xfffffe, 0);
3055 /* 64kB aligned region used for DCache cleaning */
3056 xscale->cache_clean_address = 0xfffe0000;
3058 xscale->hold_rst = 0;
3059 xscale->external_debug_break = 0;
3061 xscale->force_hw_bkpts = 1;
3063 xscale->ibcr_available = 2;
3064 xscale->ibcr0_used = 0;
3065 xscale->ibcr1_used = 0;
3067 xscale->dbr_available = 2;
3068 xscale->dbr0_used = 0;
3069 xscale->dbr1_used = 0;
3071 xscale->arm_bkpt = ARMV5_BKPT(0x0);
3072 xscale->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff;
3074 xscale->vector_catch = 0x1;
3076 xscale->trace.capture_status = TRACE_IDLE;
3077 xscale->trace.data = NULL;
3078 xscale->trace.image = NULL;
3079 xscale->trace.buffer_enabled = 0;
3080 xscale->trace.buffer_fill = 0;
3082 /* prepare ARMv4/5 specific information */
3083 armv4_5->arch_info = xscale;
3084 armv4_5->read_core_reg = xscale_read_core_reg;
3085 armv4_5->write_core_reg = xscale_write_core_reg;
3086 armv4_5->full_context = xscale_full_context;
3088 armv4_5_init_arch_info(target, armv4_5);
3090 xscale->armv4_5_mmu.armv4_5_cache.ctype = -1;
3091 xscale->armv4_5_mmu.get_ttb = xscale_get_ttb;
3092 xscale->armv4_5_mmu.read_memory = xscale_read_memory;
3093 xscale->armv4_5_mmu.write_memory = xscale_write_memory;
3094 xscale->armv4_5_mmu.disable_mmu_caches = xscale_disable_mmu_caches;
3095 xscale->armv4_5_mmu.enable_mmu_caches = xscale_enable_mmu_caches;
3096 xscale->armv4_5_mmu.has_tiny_pages = 1;
3097 xscale->armv4_5_mmu.mmu_enabled = 0;
3102 /* target xscale <endianess> <startup_mode> <chain_pos> <variant> */
3103 int xscale_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
3106 char *variant = NULL;
3107 xscale_common_t *xscale = malloc(sizeof(xscale_common_t));
3108 memset(xscale, 0, sizeof(*xscale));
3112 LOG_ERROR("'target xscale' requires four arguments: <endianess> <startup_mode> <chain_pos> <variant>");
3116 chain_pos = strtoul(args[3], NULL, 0);
3120 xscale_init_arch_info(target, xscale, chain_pos, variant);
3121 xscale_build_reg_cache(target);
3126 int xscale_handle_debug_handler_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
3128 target_t *target = NULL;
3129 armv4_5_common_t *armv4_5;
3130 xscale_common_t *xscale;
3132 u32 handler_address;
3136 LOG_ERROR("'xscale debug_handler <target#> <address>' command takes two required operands");
3140 if ((target = get_target_by_num(strtoul(args[0], NULL, 0))) == NULL)
3142 LOG_ERROR("no target '%s' configured", args[0]);
3146 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3151 handler_address = strtoul(args[1], NULL, 0);
3153 if (((handler_address >= 0x800) && (handler_address <= 0x1fef800)) ||
3154 ((handler_address >= 0xfe000800) && (handler_address <= 0xfffff800)))
3156 xscale->handler_address = handler_address;
3160 LOG_ERROR("xscale debug_handler <address> must be between 0x800 and 0x1fef800 or between 0xfe000800 and 0xfffff800");
3166 int xscale_handle_cache_clean_address_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
3168 target_t *target = NULL;
3169 armv4_5_common_t *armv4_5;
3170 xscale_common_t *xscale;
3172 u32 cache_clean_address;
3176 LOG_ERROR("'xscale cache_clean_address <target#> <address>' command takes two required operands");
3180 if ((target = get_target_by_num(strtoul(args[0], NULL, 0))) == NULL)
3182 LOG_ERROR("no target '%s' configured", args[0]);
3186 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3191 cache_clean_address = strtoul(args[1], NULL, 0);
3193 if (cache_clean_address & 0xffff)
3195 LOG_ERROR("xscale cache_clean_address <address> must be 64kb aligned");
3199 xscale->cache_clean_address = cache_clean_address;
3205 int xscale_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
3207 target_t *target = get_current_target(cmd_ctx);
3208 armv4_5_common_t *armv4_5;
3209 xscale_common_t *xscale;
3211 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3216 return armv4_5_handle_cache_info_command(cmd_ctx, &xscale->armv4_5_mmu.armv4_5_cache);
3219 static int xscale_virt2phys(struct target_s *target, u32 virtual, u32 *physical)
3221 armv4_5_common_t *armv4_5;
3222 xscale_common_t *xscale;
3230 if ((retval = xscale_get_arch_pointers(target, &armv4_5, &xscale)) != ERROR_OK)
3234 u32 ret = armv4_5_mmu_translate_va(target, &xscale->armv4_5_mmu, virtual, &type, &cb, &domain, &ap);
3243 static int xscale_mmu(struct target_s *target, int *enabled)
3245 armv4_5_common_t *armv4_5 = target->arch_info;
3246 xscale_common_t *xscale = armv4_5->arch_info;
3248 if (target->state != TARGET_HALTED)
3250 LOG_ERROR("Target not halted");
3251 return ERROR_TARGET_INVALID;
3253 *enabled = xscale->armv4_5_mmu.mmu_enabled;
3258 int xscale_handle_mmu_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
3260 target_t *target = get_current_target(cmd_ctx);
3261 armv4_5_common_t *armv4_5;
3262 xscale_common_t *xscale;
3264 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3269 if (target->state != TARGET_HALTED)
3271 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
3277 if (strcmp("enable", args[0]) == 0)
3279 xscale_enable_mmu_caches(target, 1, 0, 0);
3280 xscale->armv4_5_mmu.mmu_enabled = 1;
3282 else if (strcmp("disable", args[0]) == 0)
3284 xscale_disable_mmu_caches(target, 1, 0, 0);
3285 xscale->armv4_5_mmu.mmu_enabled = 0;
3289 command_print(cmd_ctx, "mmu %s", (xscale->armv4_5_mmu.mmu_enabled) ? "enabled" : "disabled");
3294 int xscale_handle_idcache_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
3296 target_t *target = get_current_target(cmd_ctx);
3297 armv4_5_common_t *armv4_5;
3298 xscale_common_t *xscale;
3299 int icache = 0, dcache = 0;
3301 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3306 if (target->state != TARGET_HALTED)
3308 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
3312 if (strcmp(cmd, "icache") == 0)
3314 else if (strcmp(cmd, "dcache") == 0)
3319 if (strcmp("enable", args[0]) == 0)
3321 xscale_enable_mmu_caches(target, 0, dcache, icache);
3324 xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 1;
3326 xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 1;
3328 else if (strcmp("disable", args[0]) == 0)
3330 xscale_disable_mmu_caches(target, 0, dcache, icache);
3333 xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
3335 xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
3340 command_print(cmd_ctx, "icache %s", (xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled) ? "enabled" : "disabled");
3343 command_print(cmd_ctx, "dcache %s", (xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) ? "enabled" : "disabled");
3348 int xscale_handle_vector_catch_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
3350 target_t *target = get_current_target(cmd_ctx);
3351 armv4_5_common_t *armv4_5;
3352 xscale_common_t *xscale;
3354 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3361 command_print(cmd_ctx, "usage: xscale vector_catch [mask]");
3365 xscale->vector_catch = strtoul(args[0], NULL, 0);
3366 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 8, xscale->vector_catch);
3367 xscale_write_dcsr(target, -1, -1);
3370 command_print(cmd_ctx, "vector catch mask: 0x%2.2x", xscale->vector_catch);
3375 int xscale_handle_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
3377 target_t *target = get_current_target(cmd_ctx);
3378 armv4_5_common_t *armv4_5;
3379 xscale_common_t *xscale;
3381 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3386 if ((argc >= 1) && (strcmp("enable", args[0]) == 0))
3388 xscale->force_hw_bkpts = 1;
3390 else if ((argc >= 1) && (strcmp("disable", args[0]) == 0))
3392 xscale->force_hw_bkpts = 0;
3396 command_print(cmd_ctx, "usage: xscale force_hw_bkpts <enable|disable>");
3399 command_print(cmd_ctx, "force hardware breakpoints %s", (xscale->force_hw_bkpts) ? "enabled" : "disabled");
3404 int xscale_handle_trace_buffer_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
3406 target_t *target = get_current_target(cmd_ctx);
3407 armv4_5_common_t *armv4_5;
3408 xscale_common_t *xscale;
3411 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3416 if (target->state != TARGET_HALTED)
3418 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
3422 if ((argc >= 1) && (strcmp("enable", args[0]) == 0))
3424 xscale_trace_data_t *td, *next_td;
3425 xscale->trace.buffer_enabled = 1;
3427 /* free old trace data */
3428 td = xscale->trace.data;
3438 xscale->trace.data = NULL;
3440 else if ((argc >= 1) && (strcmp("disable", args[0]) == 0))
3442 xscale->trace.buffer_enabled = 0;
3445 if ((argc >= 2) && (strcmp("fill", args[1]) == 0))
3448 xscale->trace.buffer_fill = strtoul(args[2], NULL, 0);
3450 xscale->trace.buffer_fill = 1;
3452 else if ((argc >= 2) && (strcmp("wrap", args[1]) == 0))
3454 xscale->trace.buffer_fill = -1;
3457 if (xscale->trace.buffer_enabled)
3459 /* if we enable the trace buffer in fill-once
3460 * mode we know the address of the first instruction */
3461 xscale->trace.pc_ok = 1;
3462 xscale->trace.current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
3466 /* otherwise the address is unknown, and we have no known good PC */
3467 xscale->trace.pc_ok = 0;
3470 command_print(cmd_ctx, "trace buffer %s (%s)",
3471 (xscale->trace.buffer_enabled) ? "enabled" : "disabled",
3472 (xscale->trace.buffer_fill > 0) ? "fill" : "wrap");
3474 dcsr_value = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 0, 32);
3475 if (xscale->trace.buffer_fill >= 0)
3476 xscale_write_dcsr_sw(target, (dcsr_value & 0xfffffffc) | 2);
3478 xscale_write_dcsr_sw(target, dcsr_value & 0xfffffffc);
3483 int xscale_handle_trace_image_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
3486 armv4_5_common_t *armv4_5;
3487 xscale_common_t *xscale;
3491 command_print(cmd_ctx, "usage: xscale trace_image <file> [base address] [type]");
3495 target = get_current_target(cmd_ctx);
3497 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3502 if (xscale->trace.image)
3504 image_close(xscale->trace.image);
3505 free(xscale->trace.image);
3506 command_print(cmd_ctx, "previously loaded image found and closed");
3509 xscale->trace.image = malloc(sizeof(image_t));
3510 xscale->trace.image->base_address_set = 0;
3511 xscale->trace.image->start_address_set = 0;
3513 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
3516 xscale->trace.image->base_address_set = 1;
3517 xscale->trace.image->base_address = strtoul(args[1], NULL, 0);
3521 xscale->trace.image->base_address_set = 0;
3524 if (image_open(xscale->trace.image, args[0], (argc >= 3) ? args[2] : NULL) != ERROR_OK)
3526 free(xscale->trace.image);
3527 xscale->trace.image = NULL;
3534 int xscale_handle_dump_trace_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
3536 target_t *target = get_current_target(cmd_ctx);
3537 armv4_5_common_t *armv4_5;
3538 xscale_common_t *xscale;
3539 xscale_trace_data_t *trace_data;
3542 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3547 if (target->state != TARGET_HALTED)
3549 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
3555 command_print(cmd_ctx, "usage: xscale dump_trace <file>");
3559 trace_data = xscale->trace.data;
3563 command_print(cmd_ctx, "no trace data collected");
3567 if (fileio_open(&file, args[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
3576 fileio_write_u32(&file, trace_data->chkpt0);
3577 fileio_write_u32(&file, trace_data->chkpt1);
3578 fileio_write_u32(&file, trace_data->last_instruction);
3579 fileio_write_u32(&file, trace_data->depth);
3581 for (i = 0; i < trace_data->depth; i++)
3582 fileio_write_u32(&file, trace_data->entries[i].data | ((trace_data->entries[i].type & 0xffff) << 16));
3584 trace_data = trace_data->next;
3587 fileio_close(&file);
3592 int xscale_handle_analyze_trace_buffer_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
3594 target_t *target = get_current_target(cmd_ctx);
3595 armv4_5_common_t *armv4_5;
3596 xscale_common_t *xscale;
3598 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3603 xscale_analyze_trace(target, cmd_ctx);
3608 int xscale_handle_cp15(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
3610 target_t *target = get_current_target(cmd_ctx);
3611 armv4_5_common_t *armv4_5;
3612 xscale_common_t *xscale;
3614 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3619 if (target->state != TARGET_HALTED)
3621 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
3628 reg_no = strtoul(args[0], NULL, 0);
3629 /*translate from xscale cp15 register no to openocd register*/
3633 reg_no = XSCALE_MAINID;
3636 reg_no = XSCALE_CTRL;
3639 reg_no = XSCALE_TTB;
3642 reg_no = XSCALE_DAC;
3645 reg_no = XSCALE_FSR;
3648 reg_no = XSCALE_FAR;
3651 reg_no = XSCALE_PID;
3654 reg_no = XSCALE_CPACCESS;
3657 command_print(cmd_ctx, "invalid register number");
3658 return ERROR_INVALID_ARGUMENTS;
3660 reg = &xscale->reg_cache->reg_list[reg_no];
3667 /* read cp15 control register */
3668 xscale_get_reg(reg);
3669 value = buf_get_u32(reg->value, 0, 32);
3670 command_print(cmd_ctx, "%s (/%i): 0x%x", reg->name, reg->size, value);
3675 u32 value = strtoul(args[1], NULL, 0);
3677 /* send CP write request (command 0x41) */
3678 xscale_send_u32(target, 0x41);
3680 /* send CP register number */
3681 xscale_send_u32(target, reg_no);
3683 /* send CP register value */
3684 xscale_send_u32(target, value);
3686 /* execute cpwait to ensure outstanding operations complete */
3687 xscale_send_u32(target, 0x53);
3691 command_print(cmd_ctx, "usage: cp15 [register]<, [value]>");
3697 int xscale_register_commands(struct command_context_s *cmd_ctx)
3699 command_t *xscale_cmd;
3701 xscale_cmd = register_command(cmd_ctx, NULL, "xscale", NULL, COMMAND_ANY, "xscale specific commands");
3703 register_command(cmd_ctx, xscale_cmd, "debug_handler", xscale_handle_debug_handler_command, COMMAND_ANY, "'xscale debug_handler <target#> <address>' command takes two required operands");
3704 register_command(cmd_ctx, xscale_cmd, "cache_clean_address", xscale_handle_cache_clean_address_command, COMMAND_ANY, NULL);
3706 register_command(cmd_ctx, xscale_cmd, "cache_info", xscale_handle_cache_info_command, COMMAND_EXEC, NULL);
3707 register_command(cmd_ctx, xscale_cmd, "mmu", xscale_handle_mmu_command, COMMAND_EXEC, "['enable'|'disable'] the MMU");
3708 register_command(cmd_ctx, xscale_cmd, "icache", xscale_handle_idcache_command, COMMAND_EXEC, "['enable'|'disable'] the ICache");
3709 register_command(cmd_ctx, xscale_cmd, "dcache", xscale_handle_idcache_command, COMMAND_EXEC, "['enable'|'disable'] the DCache");
3711 register_command(cmd_ctx, xscale_cmd, "vector_catch", xscale_handle_idcache_command, COMMAND_EXEC, "<mask> of vectors that should be catched");
3713 register_command(cmd_ctx, xscale_cmd, "trace_buffer", xscale_handle_trace_buffer_command, COMMAND_EXEC, "<enable|disable> ['fill' [n]|'wrap']");
3715 register_command(cmd_ctx, xscale_cmd, "dump_trace", xscale_handle_dump_trace_command, COMMAND_EXEC, "dump content of trace buffer to <file>");
3716 register_command(cmd_ctx, xscale_cmd, "analyze_trace", xscale_handle_analyze_trace_buffer_command, COMMAND_EXEC, "analyze content of trace buffer");
3717 register_command(cmd_ctx, xscale_cmd, "trace_image", xscale_handle_trace_image_command,
3718 COMMAND_EXEC, "load image from <file> [base address]");
3720 register_command(cmd_ctx, xscale_cmd, "cp15", xscale_handle_cp15, COMMAND_EXEC, "access coproc 15 <register> [value]");
3722 armv4_5_register_commands(cmd_ctx);