1 /***************************************************************************
2 * Copyright (C) 2006, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "replacements.h"
31 #include "arm_simulator.h"
32 #include "arm_disassembler.h"
35 #include "binarybuffer.h"
36 #include "time_support.h"
37 #include "breakpoints.h"
43 #include <sys/types.h>
49 int xscale_register_commands(struct command_context_s *cmd_ctx);
51 /* forward declarations */
52 int xscale_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
53 int xscale_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
56 int xscale_arch_state(struct target_s *target);
57 int xscale_poll(target_t *target);
58 int xscale_halt(target_t *target);
59 int xscale_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution);
60 int xscale_step(struct target_s *target, int current, u32 address, int handle_breakpoints);
61 int xscale_debug_entry(target_t *target);
62 int xscale_restore_context(target_t *target);
64 int xscale_assert_reset(target_t *target);
65 int xscale_deassert_reset(target_t *target);
66 int xscale_soft_reset_halt(struct target_s *target);
68 int xscale_set_reg_u32(reg_t *reg, u32 value);
70 int xscale_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode);
71 int xscale_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, u32 value);
73 int xscale_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
74 int xscale_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
75 int xscale_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer);
76 int xscale_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum);
78 int xscale_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
79 int xscale_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
80 int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
81 int xscale_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
82 int xscale_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
83 int xscale_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
84 void xscale_enable_watchpoints(struct target_s *target);
85 void xscale_enable_breakpoints(struct target_s *target);
86 static int xscale_virt2phys(struct target_s *target, u32 virtual, u32 *physical);
87 static int xscale_mmu(struct target_s *target, int *enabled);
89 int xscale_read_trace(target_t *target);
91 target_type_t xscale_target =
96 .arch_state = xscale_arch_state,
98 .target_request_data = NULL,
101 .resume = xscale_resume,
104 .assert_reset = xscale_assert_reset,
105 .deassert_reset = xscale_deassert_reset,
106 .soft_reset_halt = xscale_soft_reset_halt,
108 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
110 .read_memory = xscale_read_memory,
111 .write_memory = xscale_write_memory,
112 .bulk_write_memory = xscale_bulk_write_memory,
113 .checksum_memory = xscale_checksum_memory,
115 .run_algorithm = armv4_5_run_algorithm,
117 .add_breakpoint = xscale_add_breakpoint,
118 .remove_breakpoint = xscale_remove_breakpoint,
119 .add_watchpoint = xscale_add_watchpoint,
120 .remove_watchpoint = xscale_remove_watchpoint,
122 .register_commands = xscale_register_commands,
123 .target_command = xscale_target_command,
124 .init_target = xscale_init_target,
127 .virt2phys = xscale_virt2phys,
131 char* xscale_reg_list[] =
133 "XSCALE_MAINID", /* 0 */
143 "XSCALE_IBCR0", /* 10 */
153 "XSCALE_RX", /* 20 */
157 xscale_reg_t xscale_reg_arch_info[] =
159 {XSCALE_MAINID, NULL},
160 {XSCALE_CACHETYPE, NULL},
162 {XSCALE_AUXCTRL, NULL},
168 {XSCALE_CPACCESS, NULL},
169 {XSCALE_IBCR0, NULL},
170 {XSCALE_IBCR1, NULL},
173 {XSCALE_DBCON, NULL},
174 {XSCALE_TBREG, NULL},
175 {XSCALE_CHKPT0, NULL},
176 {XSCALE_CHKPT1, NULL},
177 {XSCALE_DCSR, NULL}, /* DCSR accessed via JTAG or SW */
178 {-1, NULL}, /* TX accessed via JTAG */
179 {-1, NULL}, /* RX accessed via JTAG */
180 {-1, NULL}, /* TXRXCTRL implicit access via JTAG */
183 int xscale_reg_arch_type = -1;
185 int xscale_get_reg(reg_t *reg);
186 int xscale_set_reg(reg_t *reg, u8 *buf);
188 int xscale_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, xscale_common_t **xscale_p)
190 armv4_5_common_t *armv4_5 = target->arch_info;
191 xscale_common_t *xscale = armv4_5->arch_info;
193 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
195 LOG_ERROR("target isn't an XScale target");
199 if (xscale->common_magic != XSCALE_COMMON_MAGIC)
201 LOG_ERROR("target isn't an XScale target");
205 *armv4_5_p = armv4_5;
211 int xscale_jtag_set_instr(int chain_pos, u32 new_instr)
213 jtag_device_t *device = jtag_get_device(chain_pos);
215 if (buf_get_u32(device->cur_instr, 0, device->ir_length) != new_instr)
219 field.device = chain_pos;
220 field.num_bits = device->ir_length;
221 field.out_value = calloc(CEIL(field.num_bits, 8), 1);
222 buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
223 field.out_mask = NULL;
224 field.in_value = NULL;
225 jtag_set_check_value(&field, device->expected, device->expected_mask, NULL);
227 jtag_add_ir_scan(1, &field, -1);
229 free(field.out_value);
235 int xscale_read_dcsr(target_t *target)
237 armv4_5_common_t *armv4_5 = target->arch_info;
238 xscale_common_t *xscale = armv4_5->arch_info;
242 scan_field_t fields[3];
244 u8 field0_check_value = 0x2;
245 u8 field0_check_mask = 0x7;
247 u8 field2_check_value = 0x0;
248 u8 field2_check_mask = 0x1;
250 jtag_add_end_state(TAP_PD);
251 xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dcsr);
253 buf_set_u32(&field0, 1, 1, xscale->hold_rst);
254 buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
256 fields[0].device = xscale->jtag_info.chain_pos;
257 fields[0].num_bits = 3;
258 fields[0].out_value = &field0;
259 fields[0].out_mask = NULL;
260 fields[0].in_value = NULL;
261 jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL);
263 fields[1].device = xscale->jtag_info.chain_pos;
264 fields[1].num_bits = 32;
265 fields[1].out_value = NULL;
266 fields[1].out_mask = NULL;
267 fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
268 fields[1].in_handler = NULL;
269 fields[1].in_handler_priv = NULL;
270 fields[1].in_check_value = NULL;
271 fields[1].in_check_mask = NULL;
273 fields[2].device = xscale->jtag_info.chain_pos;
274 fields[2].num_bits = 1;
275 fields[2].out_value = &field2;
276 fields[2].out_mask = NULL;
277 fields[2].in_value = NULL;
278 jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
280 jtag_add_dr_scan(3, fields, -1);
282 if ((retval = jtag_execute_queue()) != ERROR_OK)
284 LOG_ERROR("JTAG error while reading DCSR");
288 xscale->reg_cache->reg_list[XSCALE_DCSR].dirty = 0;
289 xscale->reg_cache->reg_list[XSCALE_DCSR].valid = 1;
291 /* write the register with the value we just read
292 * on this second pass, only the first bit of field0 is guaranteed to be 0)
294 field0_check_mask = 0x1;
295 fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
296 fields[1].in_value = NULL;
298 jtag_add_end_state(TAP_RTI);
300 jtag_add_dr_scan(3, fields, -1);
302 /* DANGER!!! this must be here. It will make sure that the arguments
303 * to jtag_set_check_value() does not go out of scope! */
304 return jtag_execute_queue();
307 int xscale_receive(target_t *target, u32 *buffer, int num_words)
310 return ERROR_INVALID_ARGUMENTS;
313 armv4_5_common_t *armv4_5 = target->arch_info;
314 xscale_common_t *xscale = armv4_5->arch_info;
316 enum tap_state path[3];
317 scan_field_t fields[3];
319 u8 *field0 = malloc(num_words * 1);
320 u8 field0_check_value = 0x2;
321 u8 field0_check_mask = 0x6;
322 u32 *field1 = malloc(num_words * 4);
323 u8 field2_check_value = 0x0;
324 u8 field2_check_mask = 0x1;
326 int words_scheduled = 0;
334 fields[0].device = xscale->jtag_info.chain_pos;
335 fields[0].num_bits = 3;
336 fields[0].out_value = NULL;
337 fields[0].out_mask = NULL;
338 fields[0].in_value = NULL;
339 jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL);
341 fields[1].device = xscale->jtag_info.chain_pos;
342 fields[1].num_bits = 32;
343 fields[1].out_value = NULL;
344 fields[1].out_mask = NULL;
345 fields[1].in_value = NULL;
346 fields[1].in_handler = NULL;
347 fields[1].in_handler_priv = NULL;
348 fields[1].in_check_value = NULL;
349 fields[1].in_check_mask = NULL;
353 fields[2].device = xscale->jtag_info.chain_pos;
354 fields[2].num_bits = 1;
355 fields[2].out_value = NULL;
356 fields[2].out_mask = NULL;
357 fields[2].in_value = NULL;
358 jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
360 jtag_add_end_state(TAP_RTI);
361 xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dbgtx);
362 jtag_add_runtest(1, -1); /* ensures that we're in the TAP_RTI state as the above could be a no-op */
364 /* repeat until all words have been collected */
366 while (words_done < num_words)
370 for (i = words_done; i < num_words; i++)
372 fields[0].in_value = &field0[i];
373 fields[1].in_handler = buf_to_u32_handler;
374 fields[1].in_handler_priv = (u8*)&field1[i];
376 jtag_add_pathmove(3, path);
377 jtag_add_dr_scan(3, fields, TAP_RTI);
381 if ((retval = jtag_execute_queue()) != ERROR_OK)
383 LOG_ERROR("JTAG error while receiving data from debug handler");
387 /* examine results */
388 for (i = words_done; i < num_words; i++)
390 if (!(field0[0] & 1))
392 /* move backwards if necessary */
394 for (j = i; j < num_words - 1; j++)
396 field0[j] = field0[j+1];
397 field1[j] = field1[j+1];
402 if (words_scheduled==0)
404 if (attempts++==1000)
406 LOG_ERROR("Failed to receiving data from debug handler after 1000 attempts");
407 retval=ERROR_TARGET_TIMEOUT;
412 words_done += words_scheduled;
415 for (i = 0; i < num_words; i++)
416 *(buffer++) = buf_get_u32((u8*)&field1[i], 0, 32);
423 int xscale_read_tx(target_t *target, int consume)
425 armv4_5_common_t *armv4_5 = target->arch_info;
426 xscale_common_t *xscale = armv4_5->arch_info;
427 enum tap_state path[3];
428 enum tap_state noconsume_path[6];
431 struct timeval timeout, now;
433 scan_field_t fields[3];
435 u8 field0_check_value = 0x2;
436 u8 field0_check_mask = 0x6;
437 u8 field2_check_value = 0x0;
438 u8 field2_check_mask = 0x1;
440 jtag_add_end_state(TAP_RTI);
442 xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dbgtx);
448 noconsume_path[0] = TAP_SDS;
449 noconsume_path[1] = TAP_CD;
450 noconsume_path[2] = TAP_E1D;
451 noconsume_path[3] = TAP_PD;
452 noconsume_path[4] = TAP_E2D;
453 noconsume_path[5] = TAP_SD;
455 fields[0].device = xscale->jtag_info.chain_pos;
456 fields[0].num_bits = 3;
457 fields[0].out_value = NULL;
458 fields[0].out_mask = NULL;
459 fields[0].in_value = &field0_in;
460 jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL);
462 fields[1].device = xscale->jtag_info.chain_pos;
463 fields[1].num_bits = 32;
464 fields[1].out_value = NULL;
465 fields[1].out_mask = NULL;
466 fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_TX].value;
467 fields[1].in_handler = NULL;
468 fields[1].in_handler_priv = NULL;
469 fields[1].in_check_value = NULL;
470 fields[1].in_check_mask = NULL;
474 fields[2].device = xscale->jtag_info.chain_pos;
475 fields[2].num_bits = 1;
476 fields[2].out_value = NULL;
477 fields[2].out_mask = NULL;
478 fields[2].in_value = NULL;
479 jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
481 gettimeofday(&timeout, NULL);
482 timeval_add_time(&timeout, 1, 0);
487 for (i=0; i<100; i++)
489 /* if we want to consume the register content (i.e. clear TX_READY),
490 * we have to go straight from Capture-DR to Shift-DR
491 * otherwise, we go from Capture-DR to Exit1-DR to Pause-DR
494 jtag_add_pathmove(3, path);
497 jtag_add_pathmove(sizeof(noconsume_path)/sizeof(*noconsume_path), noconsume_path);
500 jtag_add_dr_scan(3, fields, TAP_RTI);
502 if ((retval = jtag_execute_queue()) != ERROR_OK)
504 LOG_ERROR("JTAG error while reading TX");
505 return ERROR_TARGET_TIMEOUT;
508 gettimeofday(&now, NULL);
509 if ((now.tv_sec > timeout.tv_sec) || ((now.tv_sec == timeout.tv_sec)&& (now.tv_usec > timeout.tv_usec)))
511 LOG_ERROR("time out reading TX register");
512 return ERROR_TARGET_TIMEOUT;
514 if (!((!(field0_in & 1)) && consume))
519 LOG_DEBUG("waiting 10ms");
520 usleep(10*1000); /* avoid flooding the logs */
524 if (!(field0_in & 1))
525 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
530 int xscale_write_rx(target_t *target)
532 armv4_5_common_t *armv4_5 = target->arch_info;
533 xscale_common_t *xscale = armv4_5->arch_info;
536 struct timeval timeout, now;
538 scan_field_t fields[3];
541 u8 field0_check_value = 0x2;
542 u8 field0_check_mask = 0x6;
544 u8 field2_check_value = 0x0;
545 u8 field2_check_mask = 0x1;
547 jtag_add_end_state(TAP_RTI);
549 xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dbgrx);
551 fields[0].device = xscale->jtag_info.chain_pos;
552 fields[0].num_bits = 3;
553 fields[0].out_value = &field0_out;
554 fields[0].out_mask = NULL;
555 fields[0].in_value = &field0_in;
556 jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL);
558 fields[1].device = xscale->jtag_info.chain_pos;
559 fields[1].num_bits = 32;
560 fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_RX].value;
561 fields[1].out_mask = NULL;
562 fields[1].in_value = NULL;
563 fields[1].in_handler = NULL;
564 fields[1].in_handler_priv = NULL;
565 fields[1].in_check_value = NULL;
566 fields[1].in_check_mask = NULL;
570 fields[2].device = xscale->jtag_info.chain_pos;
571 fields[2].num_bits = 1;
572 fields[2].out_value = &field2;
573 fields[2].out_mask = NULL;
574 fields[2].in_value = NULL;
575 jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
577 gettimeofday(&timeout, NULL);
578 timeval_add_time(&timeout, 1, 0);
580 /* poll until rx_read is low */
581 LOG_DEBUG("polling RX");
587 jtag_add_dr_scan(3, fields, TAP_RTI);
589 if ((retval = jtag_execute_queue()) != ERROR_OK)
591 LOG_ERROR("JTAG error while writing RX");
595 gettimeofday(&now, NULL);
596 if ((now.tv_sec > timeout.tv_sec) || ((now.tv_sec == timeout.tv_sec)&& (now.tv_usec > timeout.tv_usec)))
598 LOG_ERROR("time out writing RX register");
599 return ERROR_TARGET_TIMEOUT;
601 if (!(field0_in & 1))
604 LOG_DEBUG("waiting 10ms");
605 usleep(10*1000); /* wait 10ms to avoid flooding the logs */
611 jtag_add_dr_scan(3, fields, TAP_RTI);
613 if ((retval = jtag_execute_queue()) != ERROR_OK)
615 LOG_ERROR("JTAG error while writing RX");
622 /* send count elements of size byte to the debug handler */
623 int xscale_send(target_t *target, u8 *buffer, int count, int size)
625 armv4_5_common_t *armv4_5 = target->arch_info;
626 xscale_common_t *xscale = armv4_5->arch_info;
633 u8 output[4] = {0, 0, 0, 0};
635 scan_field_t fields[3];
637 u8 field0_check_value = 0x2;
638 u8 field0_check_mask = 0x6;
640 u8 field2_check_value = 0x0;
641 u8 field2_check_mask = 0x1;
643 jtag_add_end_state(TAP_RTI);
645 xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dbgrx);
647 fields[0].device = xscale->jtag_info.chain_pos;
648 fields[0].num_bits = 3;
649 fields[0].out_value = &field0_out;
650 fields[0].out_mask = NULL;
651 fields[0].in_handler = NULL;
652 fields[0].in_value = NULL;
653 if (!xscale->fast_memory_access)
655 jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL);
658 fields[1].device = xscale->jtag_info.chain_pos;
659 fields[1].num_bits = 32;
660 fields[1].out_value = output;
661 fields[1].out_mask = NULL;
662 fields[1].in_value = NULL;
663 fields[1].in_handler = NULL;
664 fields[1].in_handler_priv = NULL;
665 fields[1].in_check_value = NULL;
666 fields[1].in_check_mask = NULL;
670 fields[2].device = xscale->jtag_info.chain_pos;
671 fields[2].num_bits = 1;
672 fields[2].out_value = &field2;
673 fields[2].out_mask = NULL;
674 fields[2].in_value = NULL;
675 fields[2].in_handler = NULL;
676 if (!xscale->fast_memory_access)
678 jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
688 int endianness = target->endianness;
689 while (done_count++ < count)
694 if (endianness == TARGET_LITTLE_ENDIAN)
696 t[1]=le_to_h_u32(buffer);
699 t[1]=be_to_h_u32(buffer);
703 if (endianness == TARGET_LITTLE_ENDIAN)
705 t[1]=le_to_h_u16(buffer);
708 t[1]=be_to_h_u16(buffer);
715 LOG_ERROR("BUG: size neither 4, 2 nor 1");
718 jtag_add_dr_out(xscale->jtag_info.chain_pos,
728 if ((retval = jtag_execute_queue()) != ERROR_OK)
730 LOG_ERROR("JTAG error while sending data to debug handler");
737 int xscale_send_u32(target_t *target, u32 value)
739 armv4_5_common_t *armv4_5 = target->arch_info;
740 xscale_common_t *xscale = armv4_5->arch_info;
742 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_RX].value, 0, 32, value);
743 return xscale_write_rx(target);
746 int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk)
748 armv4_5_common_t *armv4_5 = target->arch_info;
749 xscale_common_t *xscale = armv4_5->arch_info;
753 scan_field_t fields[3];
755 u8 field0_check_value = 0x2;
756 u8 field0_check_mask = 0x7;
758 u8 field2_check_value = 0x0;
759 u8 field2_check_mask = 0x1;
762 xscale->hold_rst = hold_rst;
764 if (ext_dbg_brk != -1)
765 xscale->external_debug_break = ext_dbg_brk;
767 jtag_add_end_state(TAP_RTI);
768 xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dcsr);
770 buf_set_u32(&field0, 1, 1, xscale->hold_rst);
771 buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
773 fields[0].device = xscale->jtag_info.chain_pos;
774 fields[0].num_bits = 3;
775 fields[0].out_value = &field0;
776 fields[0].out_mask = NULL;
777 fields[0].in_value = NULL;
778 jtag_set_check_value(fields+0, &field0_check_value, &field0_check_mask, NULL);
780 fields[1].device = xscale->jtag_info.chain_pos;
781 fields[1].num_bits = 32;
782 fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
783 fields[1].out_mask = NULL;
784 fields[1].in_value = NULL;
785 fields[1].in_handler = NULL;
786 fields[1].in_handler_priv = NULL;
787 fields[1].in_check_value = NULL;
788 fields[1].in_check_mask = NULL;
792 fields[2].device = xscale->jtag_info.chain_pos;
793 fields[2].num_bits = 1;
794 fields[2].out_value = &field2;
795 fields[2].out_mask = NULL;
796 fields[2].in_value = NULL;
797 jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
799 jtag_add_dr_scan(3, fields, -1);
801 if ((retval = jtag_execute_queue()) != ERROR_OK)
803 LOG_ERROR("JTAG error while writing DCSR");
807 xscale->reg_cache->reg_list[XSCALE_DCSR].dirty = 0;
808 xscale->reg_cache->reg_list[XSCALE_DCSR].valid = 1;
813 /* parity of the number of bits 0 if even; 1 if odd. for 32 bit words */
814 unsigned int parity (unsigned int v)
821 LOG_DEBUG("parity of 0x%x is %i", ov, (0x6996 >> v) & 1);
822 return (0x6996 >> v) & 1;
825 int xscale_load_ic(target_t *target, int mini, u32 va, u32 buffer[8])
827 armv4_5_common_t *armv4_5 = target->arch_info;
828 xscale_common_t *xscale = armv4_5->arch_info;
833 scan_field_t fields[2];
835 LOG_DEBUG("loading miniIC at 0x%8.8x", va);
837 jtag_add_end_state(TAP_RTI);
838 xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.ldic); /* LDIC */
840 /* CMD is b010 for Main IC and b011 for Mini IC */
842 buf_set_u32(&cmd, 0, 3, 0x3);
844 buf_set_u32(&cmd, 0, 3, 0x2);
846 buf_set_u32(&cmd, 3, 3, 0x0);
848 /* virtual address of desired cache line */
849 buf_set_u32(packet, 0, 27, va >> 5);
851 fields[0].device = xscale->jtag_info.chain_pos;
852 fields[0].num_bits = 6;
853 fields[0].out_value = &cmd;
854 fields[0].out_mask = NULL;
855 fields[0].in_value = NULL;
856 fields[0].in_check_value = NULL;
857 fields[0].in_check_mask = NULL;
858 fields[0].in_handler = NULL;
859 fields[0].in_handler_priv = NULL;
861 fields[1].device = xscale->jtag_info.chain_pos;
862 fields[1].num_bits = 27;
863 fields[1].out_value = packet;
864 fields[1].out_mask = NULL;
865 fields[1].in_value = NULL;
866 fields[1].in_check_value = NULL;
867 fields[1].in_check_mask = NULL;
868 fields[1].in_handler = NULL;
869 fields[1].in_handler_priv = NULL;
871 jtag_add_dr_scan(2, fields, -1);
873 fields[0].num_bits = 32;
874 fields[0].out_value = packet;
876 fields[1].num_bits = 1;
877 fields[1].out_value = &cmd;
879 for (word = 0; word < 8; word++)
881 buf_set_u32(packet, 0, 32, buffer[word]);
882 cmd = parity(*((u32*)packet));
883 jtag_add_dr_scan(2, fields, -1);
886 jtag_execute_queue();
891 int xscale_invalidate_ic_line(target_t *target, u32 va)
893 armv4_5_common_t *armv4_5 = target->arch_info;
894 xscale_common_t *xscale = armv4_5->arch_info;
898 scan_field_t fields[2];
900 jtag_add_end_state(TAP_RTI);
901 xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.ldic); /* LDIC */
903 /* CMD for invalidate IC line b000, bits [6:4] b000 */
904 buf_set_u32(&cmd, 0, 6, 0x0);
906 /* virtual address of desired cache line */
907 buf_set_u32(packet, 0, 27, va >> 5);
909 fields[0].device = xscale->jtag_info.chain_pos;
910 fields[0].num_bits = 6;
911 fields[0].out_value = &cmd;
912 fields[0].out_mask = NULL;
913 fields[0].in_value = NULL;
914 fields[0].in_check_value = NULL;
915 fields[0].in_check_mask = NULL;
916 fields[0].in_handler = NULL;
917 fields[0].in_handler_priv = NULL;
919 fields[1].device = xscale->jtag_info.chain_pos;
920 fields[1].num_bits = 27;
921 fields[1].out_value = packet;
922 fields[1].out_mask = NULL;
923 fields[1].in_value = NULL;
924 fields[1].in_check_value = NULL;
925 fields[1].in_check_mask = NULL;
926 fields[1].in_handler = NULL;
927 fields[1].in_handler_priv = NULL;
929 jtag_add_dr_scan(2, fields, -1);
934 int xscale_update_vectors(target_t *target)
936 armv4_5_common_t *armv4_5 = target->arch_info;
937 xscale_common_t *xscale = armv4_5->arch_info;
941 u32 low_reset_branch, high_reset_branch;
943 for (i = 1; i < 8; i++)
945 /* if there's a static vector specified for this exception, override */
946 if (xscale->static_high_vectors_set & (1 << i))
948 xscale->high_vectors[i] = xscale->static_high_vectors[i];
952 retval=target_read_u32(target, 0xffff0000 + 4*i, &xscale->high_vectors[i]);
953 if (retval == ERROR_TARGET_TIMEOUT)
955 if (retval!=ERROR_OK)
957 /* Some of these reads will fail as part of normal execution */
958 xscale->high_vectors[i] = ARMV4_5_B(0xfffffe, 0);
963 for (i = 1; i < 8; i++)
965 if (xscale->static_low_vectors_set & (1 << i))
967 xscale->low_vectors[i] = xscale->static_low_vectors[i];
971 retval=target_read_u32(target, 0x0 + 4*i, &xscale->low_vectors[i]);
972 if (retval == ERROR_TARGET_TIMEOUT)
974 if (retval!=ERROR_OK)
976 /* Some of these reads will fail as part of normal execution */
977 xscale->low_vectors[i] = ARMV4_5_B(0xfffffe, 0);
982 /* calculate branches to debug handler */
983 low_reset_branch = (xscale->handler_address + 0x20 - 0x0 - 0x8) >> 2;
984 high_reset_branch = (xscale->handler_address + 0x20 - 0xffff0000 - 0x8) >> 2;
986 xscale->low_vectors[0] = ARMV4_5_B((low_reset_branch & 0xffffff), 0);
987 xscale->high_vectors[0] = ARMV4_5_B((high_reset_branch & 0xffffff), 0);
989 /* invalidate and load exception vectors in mini i-cache */
990 xscale_invalidate_ic_line(target, 0x0);
991 xscale_invalidate_ic_line(target, 0xffff0000);
993 xscale_load_ic(target, 1, 0x0, xscale->low_vectors);
994 xscale_load_ic(target, 1, 0xffff0000, xscale->high_vectors);
999 int xscale_arch_state(struct target_s *target)
1001 armv4_5_common_t *armv4_5 = target->arch_info;
1002 xscale_common_t *xscale = armv4_5->arch_info;
1006 "disabled", "enabled"
1009 char *arch_dbg_reason[] =
1011 "", "\n(processor reset)", "\n(trace buffer full)"
1014 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
1016 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
1020 LOG_USER("target halted in %s state due to %s, current mode: %s\n"
1021 "cpsr: 0x%8.8x pc: 0x%8.8x\n"
1022 "MMU: %s, D-Cache: %s, I-Cache: %s"
1024 armv4_5_state_strings[armv4_5->core_state],
1025 target_debug_reason_strings[target->debug_reason],
1026 armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
1027 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
1028 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
1029 state[xscale->armv4_5_mmu.mmu_enabled],
1030 state[xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
1031 state[xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled],
1032 arch_dbg_reason[xscale->arch_debug_reason]);
1037 int xscale_poll(target_t *target)
1039 int retval=ERROR_OK;
1040 armv4_5_common_t *armv4_5 = target->arch_info;
1041 xscale_common_t *xscale = armv4_5->arch_info;
1043 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_DEBUG_RUNNING))
1045 enum target_state previous_state = target->state;
1046 if ((retval = xscale_read_tx(target, 0)) == ERROR_OK)
1049 /* there's data to read from the tx register, we entered debug state */
1050 xscale->handler_running = 1;
1052 target->state = TARGET_HALTED;
1054 /* process debug entry, fetching current mode regs */
1055 retval = xscale_debug_entry(target);
1057 else if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
1059 LOG_USER("error while polling TX register, reset CPU");
1060 /* here we "lie" so GDB won't get stuck and a reset can be perfomed */
1061 target->state = TARGET_HALTED;
1064 /* debug_entry could have overwritten target state (i.e. immediate resume)
1065 * don't signal event handlers in that case
1067 if (target->state != TARGET_HALTED)
1070 /* if target was running, signal that we halted
1071 * otherwise we reentered from debug execution */
1072 if (previous_state == TARGET_RUNNING)
1073 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1075 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
1081 int xscale_debug_entry(target_t *target)
1083 armv4_5_common_t *armv4_5 = target->arch_info;
1084 xscale_common_t *xscale = armv4_5->arch_info;
1092 /* clear external dbg break (will be written on next DCSR read) */
1093 xscale->external_debug_break = 0;
1094 if ((retval=xscale_read_dcsr(target))!=ERROR_OK)
1097 /* get r0, pc, r1 to r7 and cpsr */
1098 if ((retval=xscale_receive(target, buffer, 10))!=ERROR_OK)
1101 /* move r0 from buffer to register cache */
1102 buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, buffer[0]);
1103 armv4_5->core_cache->reg_list[15].dirty = 1;
1104 armv4_5->core_cache->reg_list[15].valid = 1;
1105 LOG_DEBUG("r0: 0x%8.8x", buffer[0]);
1107 /* move pc from buffer to register cache */
1108 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, buffer[1]);
1109 armv4_5->core_cache->reg_list[15].dirty = 1;
1110 armv4_5->core_cache->reg_list[15].valid = 1;
1111 LOG_DEBUG("pc: 0x%8.8x", buffer[1]);
1113 /* move data from buffer to register cache */
1114 for (i = 1; i <= 7; i++)
1116 buf_set_u32(armv4_5->core_cache->reg_list[i].value, 0, 32, buffer[1 + i]);
1117 armv4_5->core_cache->reg_list[i].dirty = 1;
1118 armv4_5->core_cache->reg_list[i].valid = 1;
1119 LOG_DEBUG("r%i: 0x%8.8x", i, buffer[i + 1]);
1122 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, buffer[9]);
1123 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
1124 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1125 LOG_DEBUG("cpsr: 0x%8.8x", buffer[9]);
1127 armv4_5->core_mode = buffer[9] & 0x1f;
1128 if (armv4_5_mode_to_number(armv4_5->core_mode) == -1)
1130 target->state = TARGET_UNKNOWN;
1131 LOG_ERROR("cpsr contains invalid mode value - communication failure");
1132 return ERROR_TARGET_FAILURE;
1134 LOG_DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]);
1136 if (buffer[9] & 0x20)
1137 armv4_5->core_state = ARMV4_5_STATE_THUMB;
1139 armv4_5->core_state = ARMV4_5_STATE_ARM;
1141 /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
1142 if ((armv4_5->core_mode != ARMV4_5_MODE_USR) && (armv4_5->core_mode != ARMV4_5_MODE_SYS))
1144 xscale_receive(target, buffer, 8);
1145 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, buffer[7]);
1146 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
1147 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
1151 /* r8 to r14, but no spsr */
1152 xscale_receive(target, buffer, 7);
1155 /* move data from buffer to register cache */
1156 for (i = 8; i <= 14; i++)
1158 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, buffer[i - 8]);
1159 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0;
1160 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
1163 /* examine debug reason */
1164 xscale_read_dcsr(target);
1165 moe = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 2, 3);
1167 /* stored PC (for calculating fixup) */
1168 pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1172 case 0x0: /* Processor reset */
1173 target->debug_reason = DBG_REASON_DBGRQ;
1174 xscale->arch_debug_reason = XSCALE_DBG_REASON_RESET;
1177 case 0x1: /* Instruction breakpoint hit */
1178 target->debug_reason = DBG_REASON_BREAKPOINT;
1179 xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
1182 case 0x2: /* Data breakpoint hit */
1183 target->debug_reason = DBG_REASON_WATCHPOINT;
1184 xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
1187 case 0x3: /* BKPT instruction executed */
1188 target->debug_reason = DBG_REASON_BREAKPOINT;
1189 xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
1192 case 0x4: /* Ext. debug event */
1193 target->debug_reason = DBG_REASON_DBGRQ;
1194 xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
1197 case 0x5: /* Vector trap occured */
1198 target->debug_reason = DBG_REASON_BREAKPOINT;
1199 xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
1202 case 0x6: /* Trace buffer full break */
1203 target->debug_reason = DBG_REASON_DBGRQ;
1204 xscale->arch_debug_reason = XSCALE_DBG_REASON_TB_FULL;
1207 case 0x7: /* Reserved */
1209 LOG_ERROR("Method of Entry is 'Reserved'");
1214 /* apply PC fixup */
1215 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, pc);
1217 /* on the first debug entry, identify cache type */
1218 if (xscale->armv4_5_mmu.armv4_5_cache.ctype == -1)
1222 /* read cp15 cache type register */
1223 xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CACHETYPE]);
1224 cache_type_reg = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CACHETYPE].value, 0, 32);
1226 armv4_5_identify_cache(cache_type_reg, &xscale->armv4_5_mmu.armv4_5_cache);
1229 /* examine MMU and Cache settings */
1230 /* read cp15 control register */
1231 xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
1232 xscale->cp15_control_reg = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
1233 xscale->armv4_5_mmu.mmu_enabled = (xscale->cp15_control_reg & 0x1U) ? 1 : 0;
1234 xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (xscale->cp15_control_reg & 0x4U) ? 1 : 0;
1235 xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (xscale->cp15_control_reg & 0x1000U) ? 1 : 0;
1237 /* tracing enabled, read collected trace data */
1238 if (xscale->trace.buffer_enabled)
1240 xscale_read_trace(target);
1241 xscale->trace.buffer_fill--;
1243 /* resume if we're still collecting trace data */
1244 if ((xscale->arch_debug_reason == XSCALE_DBG_REASON_TB_FULL)
1245 && (xscale->trace.buffer_fill > 0))
1247 xscale_resume(target, 1, 0x0, 1, 0);
1251 xscale->trace.buffer_enabled = 0;
1258 int xscale_halt(target_t *target)
1260 armv4_5_common_t *armv4_5 = target->arch_info;
1261 xscale_common_t *xscale = armv4_5->arch_info;
1263 LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
1265 if (target->state == TARGET_HALTED)
1267 LOG_DEBUG("target was already halted");
1270 else if (target->state == TARGET_UNKNOWN)
1272 /* this must not happen for a xscale target */
1273 LOG_ERROR("target was in unknown state when halt was requested");
1274 return ERROR_TARGET_INVALID;
1276 else if (target->state == TARGET_RESET)
1278 LOG_DEBUG("target->state == TARGET_RESET");
1282 /* assert external dbg break */
1283 xscale->external_debug_break = 1;
1284 xscale_read_dcsr(target);
1286 target->debug_reason = DBG_REASON_DBGRQ;
1292 int xscale_enable_single_step(struct target_s *target, u32 next_pc)
1294 armv4_5_common_t *armv4_5 = target->arch_info;
1295 xscale_common_t *xscale= armv4_5->arch_info;
1296 reg_t *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0];
1298 if (xscale->ibcr0_used)
1300 breakpoint_t *ibcr0_bp = breakpoint_find(target, buf_get_u32(ibcr0->value, 0, 32) & 0xfffffffe);
1304 xscale_unset_breakpoint(target, ibcr0_bp);
1308 LOG_ERROR("BUG: xscale->ibcr0_used is set, but no breakpoint with that address found");
1313 xscale_set_reg_u32(ibcr0, next_pc | 0x1);
1318 int xscale_disable_single_step(struct target_s *target)
1320 armv4_5_common_t *armv4_5 = target->arch_info;
1321 xscale_common_t *xscale= armv4_5->arch_info;
1322 reg_t *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0];
1324 xscale_set_reg_u32(ibcr0, 0x0);
1329 int xscale_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
1331 armv4_5_common_t *armv4_5 = target->arch_info;
1332 xscale_common_t *xscale= armv4_5->arch_info;
1333 breakpoint_t *breakpoint = target->breakpoints;
1342 if (target->state != TARGET_HALTED)
1344 LOG_WARNING("target not halted");
1345 return ERROR_TARGET_NOT_HALTED;
1348 if (!debug_execution)
1350 target_free_all_working_areas(target);
1353 /* update vector tables */
1354 if ((retval=xscale_update_vectors(target))!=ERROR_OK)
1357 /* current = 1: continue on current pc, otherwise continue at <address> */
1359 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1361 current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1363 /* if we're at the reset vector, we have to simulate the branch */
1364 if (current_pc == 0x0)
1366 arm_simulate_step(target, NULL);
1367 current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1370 /* the front-end may request us not to handle breakpoints */
1371 if (handle_breakpoints)
1373 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1377 /* there's a breakpoint at the current PC, we have to step over it */
1378 LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
1379 xscale_unset_breakpoint(target, breakpoint);
1381 /* calculate PC of next instruction */
1382 if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
1385 target_read_u32(target, current_pc, ¤t_opcode);
1386 LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode);
1389 LOG_DEBUG("enable single-step");
1390 xscale_enable_single_step(target, next_pc);
1392 /* restore banked registers */
1393 xscale_restore_context(target);
1395 /* send resume request (command 0x30 or 0x31)
1396 * clean the trace buffer if it is to be enabled (0x62) */
1397 if (xscale->trace.buffer_enabled)
1399 xscale_send_u32(target, 0x62);
1400 xscale_send_u32(target, 0x31);
1403 xscale_send_u32(target, 0x30);
1406 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1407 LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1409 for (i = 7; i >= 0; i--)
1412 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1413 LOG_DEBUG("writing r%i with value 0x%8.8x", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1417 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1418 LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1420 /* wait for and process debug entry */
1421 xscale_debug_entry(target);
1423 LOG_DEBUG("disable single-step");
1424 xscale_disable_single_step(target);
1426 LOG_DEBUG("set breakpoint at 0x%8.8x", breakpoint->address);
1427 xscale_set_breakpoint(target, breakpoint);
1431 /* enable any pending breakpoints and watchpoints */
1432 xscale_enable_breakpoints(target);
1433 xscale_enable_watchpoints(target);
1435 /* restore banked registers */
1436 xscale_restore_context(target);
1438 /* send resume request (command 0x30 or 0x31)
1439 * clean the trace buffer if it is to be enabled (0x62) */
1440 if (xscale->trace.buffer_enabled)
1442 xscale_send_u32(target, 0x62);
1443 xscale_send_u32(target, 0x31);
1446 xscale_send_u32(target, 0x30);
1449 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1450 LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1452 for (i = 7; i >= 0; i--)
1455 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1456 LOG_DEBUG("writing r%i with value 0x%8.8x", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1460 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1461 LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1463 target->debug_reason = DBG_REASON_NOTHALTED;
1465 if (!debug_execution)
1467 /* registers are now invalid */
1468 armv4_5_invalidate_core_regs(target);
1469 target->state = TARGET_RUNNING;
1470 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1474 target->state = TARGET_DEBUG_RUNNING;
1475 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
1478 LOG_DEBUG("target resumed");
1480 xscale->handler_running = 1;
1485 int xscale_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
1487 armv4_5_common_t *armv4_5 = target->arch_info;
1488 xscale_common_t *xscale = armv4_5->arch_info;
1489 breakpoint_t *breakpoint = target->breakpoints;
1491 u32 current_pc, next_pc;
1495 if (target->state != TARGET_HALTED)
1497 LOG_WARNING("target not halted");
1498 return ERROR_TARGET_NOT_HALTED;
1501 /* current = 1: continue on current pc, otherwise continue at <address> */
1503 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1505 current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1507 /* if we're at the reset vector, we have to simulate the step */
1508 if (current_pc == 0x0)
1510 arm_simulate_step(target, NULL);
1511 current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1513 target->debug_reason = DBG_REASON_SINGLESTEP;
1514 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1519 /* the front-end may request us not to handle breakpoints */
1520 if (handle_breakpoints)
1521 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1523 xscale_unset_breakpoint(target, breakpoint);
1526 target->debug_reason = DBG_REASON_SINGLESTEP;
1528 /* calculate PC of next instruction */
1529 if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
1532 target_read_u32(target, current_pc, ¤t_opcode);
1533 LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode);
1536 LOG_DEBUG("enable single-step");
1537 xscale_enable_single_step(target, next_pc);
1539 /* restore banked registers */
1540 xscale_restore_context(target);
1542 /* send resume request (command 0x30 or 0x31)
1543 * clean the trace buffer if it is to be enabled (0x62) */
1544 if (xscale->trace.buffer_enabled)
1546 xscale_send_u32(target, 0x62);
1547 xscale_send_u32(target, 0x31);
1550 xscale_send_u32(target, 0x30);
1553 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1554 LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1556 for (i = 7; i >= 0; i--)
1559 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1560 LOG_DEBUG("writing r%i with value 0x%8.8x", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1564 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1565 LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1567 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1569 /* registers are now invalid */
1570 armv4_5_invalidate_core_regs(target);
1572 /* wait for and process debug entry */
1573 xscale_debug_entry(target);
1575 LOG_DEBUG("disable single-step");
1576 xscale_disable_single_step(target);
1578 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1582 xscale_set_breakpoint(target, breakpoint);
1585 LOG_DEBUG("target stepped");
1591 int xscale_assert_reset(target_t *target)
1593 armv4_5_common_t *armv4_5 = target->arch_info;
1594 xscale_common_t *xscale = armv4_5->arch_info;
1596 LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
1598 /* select DCSR instruction (set endstate to R-T-I to ensure we don't
1599 * end up in T-L-R, which would reset JTAG
1601 jtag_add_end_state(TAP_RTI);
1602 xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dcsr);
1604 /* set Hold reset, Halt mode and Trap Reset */
1605 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
1606 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1);
1607 xscale_write_dcsr(target, 1, 0);
1609 /* select BYPASS, because having DCSR selected caused problems on the PXA27x */
1610 xscale_jtag_set_instr(xscale->jtag_info.chain_pos, 0x7f);
1611 jtag_execute_queue();
1614 jtag_add_reset(0, 1);
1616 /* sleep 1ms, to be sure we fulfill any requirements */
1617 jtag_add_sleep(1000);
1618 jtag_execute_queue();
1620 target->state = TARGET_RESET;
1625 int xscale_deassert_reset(target_t *target)
1627 armv4_5_common_t *armv4_5 = target->arch_info;
1628 xscale_common_t *xscale = armv4_5->arch_info;
1630 fileio_t debug_handler;
1638 breakpoint_t *breakpoint = target->breakpoints;
1642 xscale->ibcr_available = 2;
1643 xscale->ibcr0_used = 0;
1644 xscale->ibcr1_used = 0;
1646 xscale->dbr_available = 2;
1647 xscale->dbr0_used = 0;
1648 xscale->dbr1_used = 0;
1650 /* mark all hardware breakpoints as unset */
1653 if (breakpoint->type == BKPT_HARD)
1655 breakpoint->set = 0;
1657 breakpoint = breakpoint->next;
1660 if (!xscale->handler_installed)
1663 jtag_add_reset(0, 0);
1665 /* wait 300ms; 150 and 100ms were not enough */
1666 jtag_add_sleep(300*1000);
1668 jtag_add_runtest(2030, TAP_RTI);
1669 jtag_execute_queue();
1671 /* set Hold reset, Halt mode and Trap Reset */
1672 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
1673 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1);
1674 xscale_write_dcsr(target, 1, 0);
1676 /* Load debug handler */
1677 if (fileio_open(&debug_handler, "xscale/debug_handler.bin", FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1682 if ((binary_size = debug_handler.size) % 4)
1684 LOG_ERROR("debug_handler.bin: size not a multiple of 4");
1688 if (binary_size > 0x800)
1690 LOG_ERROR("debug_handler.bin: larger than 2kb");
1694 binary_size = CEIL(binary_size, 32) * 32;
1696 address = xscale->handler_address;
1697 while (binary_size > 0)
1702 if ((retval = fileio_read(&debug_handler, 32, buffer, &buf_cnt)) != ERROR_OK)
1707 for (i = 0; i < buf_cnt; i += 4)
1709 /* convert LE buffer to host-endian u32 */
1710 cache_line[i / 4] = le_to_h_u32(&buffer[i]);
1713 for (; buf_cnt < 32; buf_cnt += 4)
1715 cache_line[buf_cnt / 4] = 0xe1a08008;
1718 /* only load addresses other than the reset vectors */
1719 if ((address % 0x400) != 0x0)
1721 xscale_load_ic(target, 1, address, cache_line);
1725 binary_size -= buf_cnt;
1728 xscale_load_ic(target, 1, 0x0, xscale->low_vectors);
1729 xscale_load_ic(target, 1, 0xffff0000, xscale->high_vectors);
1731 jtag_add_runtest(30, TAP_RTI);
1733 jtag_add_sleep(100000);
1735 /* set Hold reset, Halt mode and Trap Reset */
1736 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
1737 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1);
1738 xscale_write_dcsr(target, 1, 0);
1740 /* clear Hold reset to let the target run (should enter debug handler) */
1741 xscale_write_dcsr(target, 0, 1);
1742 target->state = TARGET_RUNNING;
1744 if ((target->reset_mode != RESET_HALT) && (target->reset_mode != RESET_INIT))
1746 jtag_add_sleep(10000);
1748 /* we should have entered debug now */
1749 xscale_debug_entry(target);
1750 target->state = TARGET_HALTED;
1752 /* resume the target */
1753 xscale_resume(target, 1, 0x0, 1, 0);
1756 fileio_close(&debug_handler);
1760 jtag_add_reset(0, 0);
1767 int xscale_soft_reset_halt(struct target_s *target)
1773 int xscale_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode)
1779 int xscale_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, u32 value)
1785 int xscale_full_context(target_t *target)
1787 armv4_5_common_t *armv4_5 = target->arch_info;
1795 if (target->state != TARGET_HALTED)
1797 LOG_WARNING("target not halted");
1798 return ERROR_TARGET_NOT_HALTED;
1801 buffer = malloc(4 * 8);
1803 /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
1804 * we can't enter User mode on an XScale (unpredictable),
1805 * but User shares registers with SYS
1807 for(i = 1; i < 7; i++)
1811 /* check if there are invalid registers in the current mode
1813 for (j = 0; j <= 16; j++)
1815 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1823 /* request banked registers */
1824 xscale_send_u32(target, 0x0);
1827 tmp_cpsr |= armv4_5_number_to_mode(i);
1828 tmp_cpsr |= 0xc0; /* I/F bits */
1830 /* send CPSR for desired mode */
1831 xscale_send_u32(target, tmp_cpsr);
1833 /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
1834 if ((armv4_5_number_to_mode(i) != ARMV4_5_MODE_USR) && (armv4_5_number_to_mode(i) != ARMV4_5_MODE_SYS))
1836 xscale_receive(target, buffer, 8);
1837 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, buffer[7]);
1838 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
1839 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1;
1843 xscale_receive(target, buffer, 7);
1846 /* move data from buffer to register cache */
1847 for (j = 8; j <= 14; j++)
1849 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value, 0, 32, buffer[j - 8]);
1850 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
1851 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1;
1861 int xscale_restore_context(target_t *target)
1863 armv4_5_common_t *armv4_5 = target->arch_info;
1869 if (target->state != TARGET_HALTED)
1871 LOG_WARNING("target not halted");
1872 return ERROR_TARGET_NOT_HALTED;
1875 /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
1876 * we can't enter User mode on an XScale (unpredictable),
1877 * but User shares registers with SYS
1879 for(i = 1; i < 7; i++)
1883 /* check if there are invalid registers in the current mode
1885 for (j = 8; j <= 14; j++)
1887 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty == 1)
1891 /* if not USR/SYS, check if the SPSR needs to be written */
1892 if ((armv4_5_number_to_mode(i) != ARMV4_5_MODE_USR) && (armv4_5_number_to_mode(i) != ARMV4_5_MODE_SYS))
1894 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty == 1)
1902 /* send banked registers */
1903 xscale_send_u32(target, 0x1);
1906 tmp_cpsr |= armv4_5_number_to_mode(i);
1907 tmp_cpsr |= 0xc0; /* I/F bits */
1909 /* send CPSR for desired mode */
1910 xscale_send_u32(target, tmp_cpsr);
1912 /* send banked registers, r8 to r14, and spsr if not in USR/SYS mode */
1913 for (j = 8; j <= 14; j++)
1915 xscale_send_u32(target, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, j).value, 0, 32));
1916 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
1919 if ((armv4_5_number_to_mode(i) != ARMV4_5_MODE_USR) && (armv4_5_number_to_mode(i) != ARMV4_5_MODE_SYS))
1921 xscale_send_u32(target, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32));
1922 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
1930 int xscale_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1932 armv4_5_common_t *armv4_5 = target->arch_info;
1933 xscale_common_t *xscale = armv4_5->arch_info;
1938 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1940 if (target->state != TARGET_HALTED)
1942 LOG_WARNING("target not halted");
1943 return ERROR_TARGET_NOT_HALTED;
1946 /* sanitize arguments */
1947 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1948 return ERROR_INVALID_ARGUMENTS;
1950 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1951 return ERROR_TARGET_UNALIGNED_ACCESS;
1953 /* send memory read request (command 0x1n, n: access size) */
1954 if ((retval=xscale_send_u32(target, 0x10 | size))!=ERROR_OK)
1957 /* send base address for read request */
1958 if ((retval=xscale_send_u32(target, address))!=ERROR_OK)
1961 /* send number of requested data words */
1962 if ((retval=xscale_send_u32(target, count))!=ERROR_OK)
1965 /* receive data from target (count times 32-bit words in host endianness) */
1966 buf32 = malloc(4 * count);
1967 if ((retval=xscale_receive(target, buf32, count))!=ERROR_OK)
1970 /* extract data from host-endian buffer into byte stream */
1971 for (i = 0; i < count; i++)
1976 target_buffer_set_u32(target, buffer, buf32[i]);
1980 target_buffer_set_u16(target, buffer, buf32[i] & 0xffff);
1984 *buffer++ = buf32[i] & 0xff;
1987 LOG_ERROR("should never get here");
1994 /* examine DCSR, to see if Sticky Abort (SA) got set */
1995 if ((retval=xscale_read_dcsr(target))!=ERROR_OK)
1997 if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1)
2000 if ((retval=xscale_send_u32(target, 0x60))!=ERROR_OK)
2003 return ERROR_TARGET_DATA_ABORT;
2009 int xscale_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
2011 armv4_5_common_t *armv4_5 = target->arch_info;
2012 xscale_common_t *xscale = armv4_5->arch_info;
2015 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
2017 if (target->state != TARGET_HALTED)
2019 LOG_WARNING("target not halted");
2020 return ERROR_TARGET_NOT_HALTED;
2023 /* sanitize arguments */
2024 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
2025 return ERROR_INVALID_ARGUMENTS;
2027 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
2028 return ERROR_TARGET_UNALIGNED_ACCESS;
2030 /* send memory write request (command 0x2n, n: access size) */
2031 if ((retval=xscale_send_u32(target, 0x20 | size))!=ERROR_OK)
2034 /* send base address for read request */
2035 if ((retval=xscale_send_u32(target, address))!=ERROR_OK)
2038 /* send number of requested data words to be written*/
2039 if ((retval=xscale_send_u32(target, count))!=ERROR_OK)
2042 /* extract data from host-endian buffer into byte stream */
2044 for (i = 0; i < count; i++)
2049 value = target_buffer_get_u32(target, buffer);
2050 xscale_send_u32(target, value);
2054 value = target_buffer_get_u16(target, buffer);
2055 xscale_send_u32(target, value);
2060 xscale_send_u32(target, value);
2064 LOG_ERROR("should never get here");
2069 if ((retval=xscale_send(target, buffer, count, size))!=ERROR_OK)
2072 /* examine DCSR, to see if Sticky Abort (SA) got set */
2073 if ((retval=xscale_read_dcsr(target))!=ERROR_OK)
2075 if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1)
2078 if ((retval=xscale_send_u32(target, 0x60))!=ERROR_OK)
2081 return ERROR_TARGET_DATA_ABORT;
2087 int xscale_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
2089 return xscale_write_memory(target, address, 4, count, buffer);
2092 int xscale_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
2094 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2097 u32 xscale_get_ttb(target_t *target)
2099 armv4_5_common_t *armv4_5 = target->arch_info;
2100 xscale_common_t *xscale = armv4_5->arch_info;
2103 xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_TTB]);
2104 ttb = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_TTB].value, 0, 32);
2109 void xscale_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
2111 armv4_5_common_t *armv4_5 = target->arch_info;
2112 xscale_common_t *xscale = armv4_5->arch_info;
2115 /* read cp15 control register */
2116 xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
2117 cp15_control = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
2120 cp15_control &= ~0x1U;
2125 xscale_send_u32(target, 0x50);
2126 xscale_send_u32(target, xscale->cache_clean_address);
2128 /* invalidate DCache */
2129 xscale_send_u32(target, 0x51);
2131 cp15_control &= ~0x4U;
2136 /* invalidate ICache */
2137 xscale_send_u32(target, 0x52);
2138 cp15_control &= ~0x1000U;
2141 /* write new cp15 control register */
2142 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_CTRL], cp15_control);
2144 /* execute cpwait to ensure outstanding operations complete */
2145 xscale_send_u32(target, 0x53);
2148 void xscale_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
2150 armv4_5_common_t *armv4_5 = target->arch_info;
2151 xscale_common_t *xscale = armv4_5->arch_info;
2154 /* read cp15 control register */
2155 xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
2156 cp15_control = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
2159 cp15_control |= 0x1U;
2162 cp15_control |= 0x4U;
2165 cp15_control |= 0x1000U;
2167 /* write new cp15 control register */
2168 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_CTRL], cp15_control);
2170 /* execute cpwait to ensure outstanding operations complete */
2171 xscale_send_u32(target, 0x53);
2174 int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
2176 armv4_5_common_t *armv4_5 = target->arch_info;
2177 xscale_common_t *xscale = armv4_5->arch_info;
2179 if (target->state != TARGET_HALTED)
2181 LOG_WARNING("target not halted");
2182 return ERROR_TARGET_NOT_HALTED;
2185 if (xscale->force_hw_bkpts)
2186 breakpoint->type = BKPT_HARD;
2188 if (breakpoint->set)
2190 LOG_WARNING("breakpoint already set");
2194 if (breakpoint->type == BKPT_HARD)
2196 u32 value = breakpoint->address | 1;
2197 if (!xscale->ibcr0_used)
2199 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR0], value);
2200 xscale->ibcr0_used = 1;
2201 breakpoint->set = 1; /* breakpoint set on first breakpoint register */
2203 else if (!xscale->ibcr1_used)
2205 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR1], value);
2206 xscale->ibcr1_used = 1;
2207 breakpoint->set = 2; /* breakpoint set on second breakpoint register */
2211 LOG_ERROR("BUG: no hardware comparator available");
2215 else if (breakpoint->type == BKPT_SOFT)
2217 if (breakpoint->length == 4)
2219 /* keep the original instruction in target endianness */
2220 target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
2221 /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
2222 target_write_u32(target, breakpoint->address, xscale->arm_bkpt);
2226 /* keep the original instruction in target endianness */
2227 target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
2228 /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
2229 target_write_u32(target, breakpoint->address, xscale->thumb_bkpt);
2231 breakpoint->set = 1;
2238 int xscale_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
2240 armv4_5_common_t *armv4_5 = target->arch_info;
2241 xscale_common_t *xscale = armv4_5->arch_info;
2243 if (target->state != TARGET_HALTED)
2245 LOG_WARNING("target not halted");
2246 return ERROR_TARGET_NOT_HALTED;
2249 if (xscale->force_hw_bkpts)
2251 LOG_DEBUG("forcing use of hardware breakpoint at address 0x%8.8x", breakpoint->address);
2252 breakpoint->type = BKPT_HARD;
2255 if ((breakpoint->type == BKPT_HARD) && (xscale->ibcr_available < 1))
2257 LOG_INFO("no breakpoint unit available for hardware breakpoint");
2258 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2262 xscale->ibcr_available--;
2265 if ((breakpoint->length != 2) && (breakpoint->length != 4))
2267 LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
2268 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2274 int xscale_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
2276 armv4_5_common_t *armv4_5 = target->arch_info;
2277 xscale_common_t *xscale = armv4_5->arch_info;
2279 if (target->state != TARGET_HALTED)
2281 LOG_WARNING("target not halted");
2282 return ERROR_TARGET_NOT_HALTED;
2285 if (!breakpoint->set)
2287 LOG_WARNING("breakpoint not set");
2291 if (breakpoint->type == BKPT_HARD)
2293 if (breakpoint->set == 1)
2295 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR0], 0x0);
2296 xscale->ibcr0_used = 0;
2298 else if (breakpoint->set == 2)
2300 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR1], 0x0);
2301 xscale->ibcr1_used = 0;
2303 breakpoint->set = 0;
2307 /* restore original instruction (kept in target endianness) */
2308 if (breakpoint->length == 4)
2310 target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
2314 target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
2316 breakpoint->set = 0;
2322 int xscale_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
2324 armv4_5_common_t *armv4_5 = target->arch_info;
2325 xscale_common_t *xscale = armv4_5->arch_info;
2327 if (target->state != TARGET_HALTED)
2329 LOG_WARNING("target not halted");
2330 return ERROR_TARGET_NOT_HALTED;
2333 if (breakpoint->set)
2335 xscale_unset_breakpoint(target, breakpoint);
2338 if (breakpoint->type == BKPT_HARD)
2339 xscale->ibcr_available++;
2344 int xscale_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
2346 armv4_5_common_t *armv4_5 = target->arch_info;
2347 xscale_common_t *xscale = armv4_5->arch_info;
2349 reg_t *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON];
2350 u32 dbcon_value = buf_get_u32(dbcon->value, 0, 32);
2352 if (target->state != TARGET_HALTED)
2354 LOG_WARNING("target not halted");
2355 return ERROR_TARGET_NOT_HALTED;
2358 xscale_get_reg(dbcon);
2360 switch (watchpoint->rw)
2372 LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
2375 if (!xscale->dbr0_used)
2377 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_DBR0], watchpoint->address);
2378 dbcon_value |= enable;
2379 xscale_set_reg_u32(dbcon, dbcon_value);
2380 watchpoint->set = 1;
2381 xscale->dbr0_used = 1;
2383 else if (!xscale->dbr1_used)
2385 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_DBR1], watchpoint->address);
2386 dbcon_value |= enable << 2;
2387 xscale_set_reg_u32(dbcon, dbcon_value);
2388 watchpoint->set = 2;
2389 xscale->dbr1_used = 1;
2393 LOG_ERROR("BUG: no hardware comparator available");
2400 int xscale_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
2402 armv4_5_common_t *armv4_5 = target->arch_info;
2403 xscale_common_t *xscale = armv4_5->arch_info;
2405 if (target->state != TARGET_HALTED)
2407 LOG_WARNING("target not halted");
2408 return ERROR_TARGET_NOT_HALTED;
2411 if (xscale->dbr_available < 1)
2413 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2416 if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4))
2418 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2421 xscale->dbr_available--;
2426 int xscale_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
2428 armv4_5_common_t *armv4_5 = target->arch_info;
2429 xscale_common_t *xscale = armv4_5->arch_info;
2430 reg_t *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON];
2431 u32 dbcon_value = buf_get_u32(dbcon->value, 0, 32);
2433 if (target->state != TARGET_HALTED)
2435 LOG_WARNING("target not halted");
2436 return ERROR_TARGET_NOT_HALTED;
2439 if (!watchpoint->set)
2441 LOG_WARNING("breakpoint not set");
2445 if (watchpoint->set == 1)
2447 dbcon_value &= ~0x3;
2448 xscale_set_reg_u32(dbcon, dbcon_value);
2449 xscale->dbr0_used = 0;
2451 else if (watchpoint->set == 2)
2453 dbcon_value &= ~0xc;
2454 xscale_set_reg_u32(dbcon, dbcon_value);
2455 xscale->dbr1_used = 0;
2457 watchpoint->set = 0;
2462 int xscale_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
2464 armv4_5_common_t *armv4_5 = target->arch_info;
2465 xscale_common_t *xscale = armv4_5->arch_info;
2467 if (target->state != TARGET_HALTED)
2469 LOG_WARNING("target not halted");
2470 return ERROR_TARGET_NOT_HALTED;
2473 if (watchpoint->set)
2475 xscale_unset_watchpoint(target, watchpoint);
2478 xscale->dbr_available++;
2483 void xscale_enable_watchpoints(struct target_s *target)
2485 watchpoint_t *watchpoint = target->watchpoints;
2489 if (watchpoint->set == 0)
2490 xscale_set_watchpoint(target, watchpoint);
2491 watchpoint = watchpoint->next;
2495 void xscale_enable_breakpoints(struct target_s *target)
2497 breakpoint_t *breakpoint = target->breakpoints;
2499 /* set any pending breakpoints */
2502 if (breakpoint->set == 0)
2503 xscale_set_breakpoint(target, breakpoint);
2504 breakpoint = breakpoint->next;
2508 int xscale_get_reg(reg_t *reg)
2510 xscale_reg_t *arch_info = reg->arch_info;
2511 target_t *target = arch_info->target;
2512 armv4_5_common_t *armv4_5 = target->arch_info;
2513 xscale_common_t *xscale = armv4_5->arch_info;
2515 /* DCSR, TX and RX are accessible via JTAG */
2516 if (strcmp(reg->name, "XSCALE_DCSR") == 0)
2518 return xscale_read_dcsr(arch_info->target);
2520 else if (strcmp(reg->name, "XSCALE_TX") == 0)
2522 /* 1 = consume register content */
2523 return xscale_read_tx(arch_info->target, 1);
2525 else if (strcmp(reg->name, "XSCALE_RX") == 0)
2527 /* can't read from RX register (host -> debug handler) */
2530 else if (strcmp(reg->name, "XSCALE_TXRXCTRL") == 0)
2532 /* can't (explicitly) read from TXRXCTRL register */
2535 else /* Other DBG registers have to be transfered by the debug handler */
2537 /* send CP read request (command 0x40) */
2538 xscale_send_u32(target, 0x40);
2540 /* send CP register number */
2541 xscale_send_u32(target, arch_info->dbg_handler_number);
2543 /* read register value */
2544 xscale_read_tx(target, 1);
2545 buf_cpy(xscale->reg_cache->reg_list[XSCALE_TX].value, reg->value, 32);
2554 int xscale_set_reg(reg_t *reg, u8* buf)
2556 xscale_reg_t *arch_info = reg->arch_info;
2557 target_t *target = arch_info->target;
2558 armv4_5_common_t *armv4_5 = target->arch_info;
2559 xscale_common_t *xscale = armv4_5->arch_info;
2560 u32 value = buf_get_u32(buf, 0, 32);
2562 /* DCSR, TX and RX are accessible via JTAG */
2563 if (strcmp(reg->name, "XSCALE_DCSR") == 0)
2565 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 0, 32, value);
2566 return xscale_write_dcsr(arch_info->target, -1, -1);
2568 else if (strcmp(reg->name, "XSCALE_RX") == 0)
2570 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_RX].value, 0, 32, value);
2571 return xscale_write_rx(arch_info->target);
2573 else if (strcmp(reg->name, "XSCALE_TX") == 0)
2575 /* can't write to TX register (debug-handler -> host) */
2578 else if (strcmp(reg->name, "XSCALE_TXRXCTRL") == 0)
2580 /* can't (explicitly) write to TXRXCTRL register */
2583 else /* Other DBG registers have to be transfered by the debug handler */
2585 /* send CP write request (command 0x41) */
2586 xscale_send_u32(target, 0x41);
2588 /* send CP register number */
2589 xscale_send_u32(target, arch_info->dbg_handler_number);
2591 /* send CP register value */
2592 xscale_send_u32(target, value);
2593 buf_set_u32(reg->value, 0, 32, value);
2599 /* convenience wrapper to access XScale specific registers */
2600 int xscale_set_reg_u32(reg_t *reg, u32 value)
2604 buf_set_u32(buf, 0, 32, value);
2606 return xscale_set_reg(reg, buf);
2609 int xscale_write_dcsr_sw(target_t *target, u32 value)
2611 /* get pointers to arch-specific information */
2612 armv4_5_common_t *armv4_5 = target->arch_info;
2613 xscale_common_t *xscale = armv4_5->arch_info;
2614 reg_t *dcsr = &xscale->reg_cache->reg_list[XSCALE_DCSR];
2615 xscale_reg_t *dcsr_arch_info = dcsr->arch_info;
2617 /* send CP write request (command 0x41) */
2618 xscale_send_u32(target, 0x41);
2620 /* send CP register number */
2621 xscale_send_u32(target, dcsr_arch_info->dbg_handler_number);
2623 /* send CP register value */
2624 xscale_send_u32(target, value);
2625 buf_set_u32(dcsr->value, 0, 32, value);
2630 int xscale_read_trace(target_t *target)
2632 /* get pointers to arch-specific information */
2633 armv4_5_common_t *armv4_5 = target->arch_info;
2634 xscale_common_t *xscale = armv4_5->arch_info;
2635 xscale_trace_data_t **trace_data_p;
2637 /* 258 words from debug handler
2638 * 256 trace buffer entries
2639 * 2 checkpoint addresses
2641 u32 trace_buffer[258];
2642 int is_address[256];
2645 if (target->state != TARGET_HALTED)
2647 LOG_WARNING("target must be stopped to read trace data");
2648 return ERROR_TARGET_NOT_HALTED;
2651 /* send read trace buffer command (command 0x61) */
2652 xscale_send_u32(target, 0x61);
2654 /* receive trace buffer content */
2655 xscale_receive(target, trace_buffer, 258);
2657 /* parse buffer backwards to identify address entries */
2658 for (i = 255; i >= 0; i--)
2661 if (((trace_buffer[i] & 0xf0) == 0x90) ||
2662 ((trace_buffer[i] & 0xf0) == 0xd0))
2665 is_address[--i] = 1;
2667 is_address[--i] = 1;
2669 is_address[--i] = 1;
2671 is_address[--i] = 1;
2676 /* search first non-zero entry */
2677 for (j = 0; (j < 256) && (trace_buffer[j] == 0) && (!is_address[j]); j++)
2682 LOG_DEBUG("no trace data collected");
2683 return ERROR_XSCALE_NO_TRACE_DATA;
2686 for (trace_data_p = &xscale->trace.data; *trace_data_p; trace_data_p = &(*trace_data_p)->next)
2689 *trace_data_p = malloc(sizeof(xscale_trace_data_t));
2690 (*trace_data_p)->next = NULL;
2691 (*trace_data_p)->chkpt0 = trace_buffer[256];
2692 (*trace_data_p)->chkpt1 = trace_buffer[257];
2693 (*trace_data_p)->last_instruction = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
2694 (*trace_data_p)->entries = malloc(sizeof(xscale_trace_entry_t) * (256 - j));
2695 (*trace_data_p)->depth = 256 - j;
2697 for (i = j; i < 256; i++)
2699 (*trace_data_p)->entries[i - j].data = trace_buffer[i];
2701 (*trace_data_p)->entries[i - j].type = XSCALE_TRACE_ADDRESS;
2703 (*trace_data_p)->entries[i - j].type = XSCALE_TRACE_MESSAGE;
2709 int xscale_read_instruction(target_t *target, arm_instruction_t *instruction)
2711 /* get pointers to arch-specific information */
2712 armv4_5_common_t *armv4_5 = target->arch_info;
2713 xscale_common_t *xscale = armv4_5->arch_info;
2720 if (!xscale->trace.image)
2721 return ERROR_TRACE_IMAGE_UNAVAILABLE;
2723 /* search for the section the current instruction belongs to */
2724 for (i = 0; i < xscale->trace.image->num_sections; i++)
2726 if ((xscale->trace.image->sections[i].base_address <= xscale->trace.current_pc) &&
2727 (xscale->trace.image->sections[i].base_address + xscale->trace.image->sections[i].size > xscale->trace.current_pc))
2736 /* current instruction couldn't be found in the image */
2737 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
2740 if (xscale->trace.core_state == ARMV4_5_STATE_ARM)
2743 if ((retval = image_read_section(xscale->trace.image, section,
2744 xscale->trace.current_pc - xscale->trace.image->sections[section].base_address,
2745 4, buf, &size_read)) != ERROR_OK)
2747 LOG_ERROR("error while reading instruction: %i", retval);
2748 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
2750 opcode = target_buffer_get_u32(target, buf);
2751 arm_evaluate_opcode(opcode, xscale->trace.current_pc, instruction);
2753 else if (xscale->trace.core_state == ARMV4_5_STATE_THUMB)
2756 if ((retval = image_read_section(xscale->trace.image, section,
2757 xscale->trace.current_pc - xscale->trace.image->sections[section].base_address,
2758 2, buf, &size_read)) != ERROR_OK)
2760 LOG_ERROR("error while reading instruction: %i", retval);
2761 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
2763 opcode = target_buffer_get_u16(target, buf);
2764 thumb_evaluate_opcode(opcode, xscale->trace.current_pc, instruction);
2768 LOG_ERROR("BUG: unknown core state encountered");
2775 int xscale_branch_address(xscale_trace_data_t *trace_data, int i, u32 *target)
2777 /* if there are less than four entries prior to the indirect branch message
2778 * we can't extract the address */
2784 *target = (trace_data->entries[i-1].data) | (trace_data->entries[i-2].data << 8) |
2785 (trace_data->entries[i-3].data << 16) | (trace_data->entries[i-4].data << 24);
2790 int xscale_analyze_trace(target_t *target, command_context_t *cmd_ctx)
2792 /* get pointers to arch-specific information */
2793 armv4_5_common_t *armv4_5 = target->arch_info;
2794 xscale_common_t *xscale = armv4_5->arch_info;
2797 xscale_trace_data_t *trace_data = xscale->trace.data;
2806 xscale->trace.core_state = ARMV4_5_STATE_ARM;
2811 for (i = 0; i < trace_data->depth; i++)
2817 if (trace_data->entries[i].type == XSCALE_TRACE_ADDRESS)
2820 switch ((trace_data->entries[i].data & 0xf0) >> 4)
2822 case 0: /* Exceptions */
2830 exception = (trace_data->entries[i].data & 0x70) >> 4;
2832 next_pc = (trace_data->entries[i].data & 0xf0) >> 2;
2833 command_print(cmd_ctx, "--- exception %i ---", (trace_data->entries[i].data & 0xf0) >> 4);
2835 case 8: /* Direct Branch */
2838 case 9: /* Indirect Branch */
2840 if (xscale_branch_address(trace_data, i, &next_pc) == 0)
2845 case 13: /* Checkpointed Indirect Branch */
2846 if (xscale_branch_address(trace_data, i, &next_pc) == 0)
2849 if (((chkpt == 0) && (next_pc != trace_data->chkpt0))
2850 || ((chkpt == 1) && (next_pc != trace_data->chkpt1)))
2851 LOG_WARNING("checkpointed indirect branch target address doesn't match checkpoint");
2853 /* explicit fall-through */
2854 case 12: /* Checkpointed Direct Branch */
2859 next_pc = trace_data->chkpt0;
2862 else if (chkpt == 1)
2865 next_pc = trace_data->chkpt0;
2870 LOG_WARNING("more than two checkpointed branches encountered");
2873 case 15: /* Roll-over */
2876 default: /* Reserved */
2877 command_print(cmd_ctx, "--- reserved trace message ---");
2878 LOG_ERROR("BUG: trace message %i is reserved", (trace_data->entries[i].data & 0xf0) >> 4);
2882 if (xscale->trace.pc_ok)
2884 int executed = (trace_data->entries[i].data & 0xf) + rollover * 16;
2885 arm_instruction_t instruction;
2887 if ((exception == 6) || (exception == 7))
2889 /* IRQ or FIQ exception, no instruction executed */
2893 while (executed-- >= 0)
2895 if ((retval = xscale_read_instruction(target, &instruction)) != ERROR_OK)
2897 /* can't continue tracing with no image available */
2898 if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
2902 else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE)
2904 /* TODO: handle incomplete images */
2908 /* a precise abort on a load to the PC is included in the incremental
2909 * word count, other instructions causing data aborts are not included
2911 if ((executed == 0) && (exception == 4)
2912 && ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_LDM)))
2914 if ((instruction.type == ARM_LDM)
2915 && ((instruction.info.load_store_multiple.register_list & 0x8000) == 0))
2919 else if (((instruction.type >= ARM_LDR) && (instruction.type <= ARM_LDRSH))
2920 && (instruction.info.load_store.Rd != 15))
2926 /* only the last instruction executed
2927 * (the one that caused the control flow change)
2928 * could be a taken branch
2930 if (((executed == -1) && (branch == 1)) &&
2931 (((instruction.type == ARM_B) ||
2932 (instruction.type == ARM_BL) ||
2933 (instruction.type == ARM_BLX)) &&
2934 (instruction.info.b_bl_bx_blx.target_address != -1)))
2936 xscale->trace.current_pc = instruction.info.b_bl_bx_blx.target_address;
2940 xscale->trace.current_pc += (xscale->trace.core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
2942 command_print(cmd_ctx, "%s", instruction.text);
2950 xscale->trace.current_pc = next_pc;
2951 xscale->trace.pc_ok = 1;
2955 for (; xscale->trace.current_pc < trace_data->last_instruction; xscale->trace.current_pc += (xscale->trace.core_state == ARMV4_5_STATE_ARM) ? 4 : 2)
2957 arm_instruction_t instruction;
2958 if ((retval = xscale_read_instruction(target, &instruction)) != ERROR_OK)
2960 /* can't continue tracing with no image available */
2961 if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
2965 else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE)
2967 /* TODO: handle incomplete images */
2970 command_print(cmd_ctx, "%s", instruction.text);
2973 trace_data = trace_data->next;
2979 void xscale_build_reg_cache(target_t *target)
2981 /* get pointers to arch-specific information */
2982 armv4_5_common_t *armv4_5 = target->arch_info;
2983 xscale_common_t *xscale = armv4_5->arch_info;
2985 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
2986 xscale_reg_t *arch_info = malloc(sizeof(xscale_reg_arch_info));
2988 int num_regs = sizeof(xscale_reg_arch_info) / sizeof(xscale_reg_t);
2990 (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
2991 armv4_5->core_cache = (*cache_p);
2993 /* register a register arch-type for XScale dbg registers only once */
2994 if (xscale_reg_arch_type == -1)
2995 xscale_reg_arch_type = register_reg_arch_type(xscale_get_reg, xscale_set_reg);
2997 (*cache_p)->next = malloc(sizeof(reg_cache_t));
2998 cache_p = &(*cache_p)->next;
3000 /* fill in values for the xscale reg cache */
3001 (*cache_p)->name = "XScale registers";
3002 (*cache_p)->next = NULL;
3003 (*cache_p)->reg_list = malloc(num_regs * sizeof(reg_t));
3004 (*cache_p)->num_regs = num_regs;
3006 for (i = 0; i < num_regs; i++)
3008 (*cache_p)->reg_list[i].name = xscale_reg_list[i];
3009 (*cache_p)->reg_list[i].value = calloc(4, 1);
3010 (*cache_p)->reg_list[i].dirty = 0;
3011 (*cache_p)->reg_list[i].valid = 0;
3012 (*cache_p)->reg_list[i].size = 32;
3013 (*cache_p)->reg_list[i].bitfield_desc = NULL;
3014 (*cache_p)->reg_list[i].num_bitfields = 0;
3015 (*cache_p)->reg_list[i].arch_info = &arch_info[i];
3016 (*cache_p)->reg_list[i].arch_type = xscale_reg_arch_type;
3017 arch_info[i] = xscale_reg_arch_info[i];
3018 arch_info[i].target = target;
3021 xscale->reg_cache = (*cache_p);
3024 int xscale_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
3035 int xscale_init_arch_info(target_t *target, xscale_common_t *xscale, int chain_pos, char *variant)
3037 armv4_5_common_t *armv4_5;
3038 u32 high_reset_branch, low_reset_branch;
3041 armv4_5 = &xscale->armv4_5_common;
3043 /* store architecture specfic data (none so far) */
3044 xscale->arch_info = NULL;
3045 xscale->common_magic = XSCALE_COMMON_MAGIC;
3047 /* remember the variant (PXA25x, PXA27x, IXP42x, ...) */
3048 xscale->variant = strdup(variant);
3050 /* prepare JTAG information for the new target */
3051 xscale->jtag_info.chain_pos = chain_pos;
3053 xscale->jtag_info.dbgrx = 0x02;
3054 xscale->jtag_info.dbgtx = 0x10;
3055 xscale->jtag_info.dcsr = 0x09;
3056 xscale->jtag_info.ldic = 0x07;
3058 if ((strcmp(xscale->variant, "pxa250") == 0) ||
3059 (strcmp(xscale->variant, "pxa255") == 0) ||
3060 (strcmp(xscale->variant, "pxa26x") == 0))
3062 xscale->jtag_info.ir_length = 5;
3064 else if ((strcmp(xscale->variant, "pxa27x") == 0) ||
3065 (strcmp(xscale->variant, "ixp42x") == 0) ||
3066 (strcmp(xscale->variant, "ixp45x") == 0) ||
3067 (strcmp(xscale->variant, "ixp46x") == 0))
3069 xscale->jtag_info.ir_length = 7;
3072 /* the debug handler isn't installed (and thus not running) at this time */
3073 xscale->handler_installed = 0;
3074 xscale->handler_running = 0;
3075 xscale->handler_address = 0xfe000800;
3077 /* clear the vectors we keep locally for reference */
3078 memset(xscale->low_vectors, 0, sizeof(xscale->low_vectors));
3079 memset(xscale->high_vectors, 0, sizeof(xscale->high_vectors));
3081 /* no user-specified vectors have been configured yet */
3082 xscale->static_low_vectors_set = 0x0;
3083 xscale->static_high_vectors_set = 0x0;
3085 /* calculate branches to debug handler */
3086 low_reset_branch = (xscale->handler_address + 0x20 - 0x0 - 0x8) >> 2;
3087 high_reset_branch = (xscale->handler_address + 0x20 - 0xffff0000 - 0x8) >> 2;
3089 xscale->low_vectors[0] = ARMV4_5_B((low_reset_branch & 0xffffff), 0);
3090 xscale->high_vectors[0] = ARMV4_5_B((high_reset_branch & 0xffffff), 0);
3092 for (i = 1; i <= 7; i++)
3094 xscale->low_vectors[i] = ARMV4_5_B(0xfffffe, 0);
3095 xscale->high_vectors[i] = ARMV4_5_B(0xfffffe, 0);
3098 /* 64kB aligned region used for DCache cleaning */
3099 xscale->cache_clean_address = 0xfffe0000;
3101 xscale->hold_rst = 0;
3102 xscale->external_debug_break = 0;
3104 xscale->force_hw_bkpts = 1;
3106 xscale->ibcr_available = 2;
3107 xscale->ibcr0_used = 0;
3108 xscale->ibcr1_used = 0;
3110 xscale->dbr_available = 2;
3111 xscale->dbr0_used = 0;
3112 xscale->dbr1_used = 0;
3114 xscale->arm_bkpt = ARMV5_BKPT(0x0);
3115 xscale->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff;
3117 xscale->vector_catch = 0x1;
3119 xscale->trace.capture_status = TRACE_IDLE;
3120 xscale->trace.data = NULL;
3121 xscale->trace.image = NULL;
3122 xscale->trace.buffer_enabled = 0;
3123 xscale->trace.buffer_fill = 0;
3125 /* prepare ARMv4/5 specific information */
3126 armv4_5->arch_info = xscale;
3127 armv4_5->read_core_reg = xscale_read_core_reg;
3128 armv4_5->write_core_reg = xscale_write_core_reg;
3129 armv4_5->full_context = xscale_full_context;
3131 armv4_5_init_arch_info(target, armv4_5);
3133 xscale->armv4_5_mmu.armv4_5_cache.ctype = -1;
3134 xscale->armv4_5_mmu.get_ttb = xscale_get_ttb;
3135 xscale->armv4_5_mmu.read_memory = xscale_read_memory;
3136 xscale->armv4_5_mmu.write_memory = xscale_write_memory;
3137 xscale->armv4_5_mmu.disable_mmu_caches = xscale_disable_mmu_caches;
3138 xscale->armv4_5_mmu.enable_mmu_caches = xscale_enable_mmu_caches;
3139 xscale->armv4_5_mmu.has_tiny_pages = 1;
3140 xscale->armv4_5_mmu.mmu_enabled = 0;
3142 xscale->fast_memory_access = 0;
3147 /* target xscale <endianess> <startup_mode> <chain_pos> <variant> */
3148 int xscale_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
3151 char *variant = NULL;
3152 xscale_common_t *xscale = malloc(sizeof(xscale_common_t));
3153 memset(xscale, 0, sizeof(*xscale));
3157 LOG_ERROR("'target xscale' requires four arguments: <endianess> <startup_mode> <chain_pos> <variant>");
3161 chain_pos = strtoul(args[3], NULL, 0);
3165 xscale_init_arch_info(target, xscale, chain_pos, variant);
3166 xscale_build_reg_cache(target);
3171 int xscale_handle_debug_handler_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
3173 target_t *target = NULL;
3174 armv4_5_common_t *armv4_5;
3175 xscale_common_t *xscale;
3177 u32 handler_address;
3181 LOG_ERROR("'xscale debug_handler <target#> <address>' command takes two required operands");
3185 if ((target = get_target_by_num(strtoul(args[0], NULL, 0))) == NULL)
3187 LOG_ERROR("no target '%s' configured", args[0]);
3191 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3196 handler_address = strtoul(args[1], NULL, 0);
3198 if (((handler_address >= 0x800) && (handler_address <= 0x1fef800)) ||
3199 ((handler_address >= 0xfe000800) && (handler_address <= 0xfffff800)))
3201 xscale->handler_address = handler_address;
3205 LOG_ERROR("xscale debug_handler <address> must be between 0x800 and 0x1fef800 or between 0xfe000800 and 0xfffff800");
3211 int xscale_handle_cache_clean_address_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
3213 target_t *target = NULL;
3214 armv4_5_common_t *armv4_5;
3215 xscale_common_t *xscale;
3217 u32 cache_clean_address;
3221 LOG_ERROR("'xscale cache_clean_address <target#> <address>' command takes two required operands");
3225 if ((target = get_target_by_num(strtoul(args[0], NULL, 0))) == NULL)
3227 LOG_ERROR("no target '%s' configured", args[0]);
3231 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3236 cache_clean_address = strtoul(args[1], NULL, 0);
3238 if (cache_clean_address & 0xffff)
3240 LOG_ERROR("xscale cache_clean_address <address> must be 64kb aligned");
3244 xscale->cache_clean_address = cache_clean_address;
3250 int xscale_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
3252 target_t *target = get_current_target(cmd_ctx);
3253 armv4_5_common_t *armv4_5;
3254 xscale_common_t *xscale;
3256 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3261 return armv4_5_handle_cache_info_command(cmd_ctx, &xscale->armv4_5_mmu.armv4_5_cache);
3264 static int xscale_virt2phys(struct target_s *target, u32 virtual, u32 *physical)
3266 armv4_5_common_t *armv4_5;
3267 xscale_common_t *xscale;
3275 if ((retval = xscale_get_arch_pointers(target, &armv4_5, &xscale)) != ERROR_OK)
3279 u32 ret = armv4_5_mmu_translate_va(target, &xscale->armv4_5_mmu, virtual, &type, &cb, &domain, &ap);
3288 static int xscale_mmu(struct target_s *target, int *enabled)
3290 armv4_5_common_t *armv4_5 = target->arch_info;
3291 xscale_common_t *xscale = armv4_5->arch_info;
3293 if (target->state != TARGET_HALTED)
3295 LOG_ERROR("Target not halted");
3296 return ERROR_TARGET_INVALID;
3298 *enabled = xscale->armv4_5_mmu.mmu_enabled;
3303 int xscale_handle_mmu_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
3305 target_t *target = get_current_target(cmd_ctx);
3306 armv4_5_common_t *armv4_5;
3307 xscale_common_t *xscale;
3309 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3314 if (target->state != TARGET_HALTED)
3316 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
3322 if (strcmp("enable", args[0]) == 0)
3324 xscale_enable_mmu_caches(target, 1, 0, 0);
3325 xscale->armv4_5_mmu.mmu_enabled = 1;
3327 else if (strcmp("disable", args[0]) == 0)
3329 xscale_disable_mmu_caches(target, 1, 0, 0);
3330 xscale->armv4_5_mmu.mmu_enabled = 0;
3334 command_print(cmd_ctx, "mmu %s", (xscale->armv4_5_mmu.mmu_enabled) ? "enabled" : "disabled");
3339 int xscale_handle_idcache_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
3341 target_t *target = get_current_target(cmd_ctx);
3342 armv4_5_common_t *armv4_5;
3343 xscale_common_t *xscale;
3344 int icache = 0, dcache = 0;
3346 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3351 if (target->state != TARGET_HALTED)
3353 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
3357 if (strcmp(cmd, "icache") == 0)
3359 else if (strcmp(cmd, "dcache") == 0)
3364 if (strcmp("enable", args[0]) == 0)
3366 xscale_enable_mmu_caches(target, 0, dcache, icache);
3369 xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 1;
3371 xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 1;
3373 else if (strcmp("disable", args[0]) == 0)
3375 xscale_disable_mmu_caches(target, 0, dcache, icache);
3378 xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
3380 xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
3385 command_print(cmd_ctx, "icache %s", (xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled) ? "enabled" : "disabled");
3388 command_print(cmd_ctx, "dcache %s", (xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) ? "enabled" : "disabled");
3393 int xscale_handle_vector_catch_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
3395 target_t *target = get_current_target(cmd_ctx);
3396 armv4_5_common_t *armv4_5;
3397 xscale_common_t *xscale;
3399 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3406 command_print(cmd_ctx, "usage: xscale vector_catch [mask]");
3410 xscale->vector_catch = strtoul(args[0], NULL, 0);
3411 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 8, xscale->vector_catch);
3412 xscale_write_dcsr(target, -1, -1);
3415 command_print(cmd_ctx, "vector catch mask: 0x%2.2x", xscale->vector_catch);
3420 int xscale_handle_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
3422 target_t *target = get_current_target(cmd_ctx);
3423 armv4_5_common_t *armv4_5;
3424 xscale_common_t *xscale;
3426 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3431 if ((argc >= 1) && (strcmp("enable", args[0]) == 0))
3433 xscale->force_hw_bkpts = 1;
3435 else if ((argc >= 1) && (strcmp("disable", args[0]) == 0))
3437 xscale->force_hw_bkpts = 0;
3441 command_print(cmd_ctx, "usage: xscale force_hw_bkpts <enable|disable>");
3444 command_print(cmd_ctx, "force hardware breakpoints %s", (xscale->force_hw_bkpts) ? "enabled" : "disabled");
3449 int xscale_handle_trace_buffer_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
3451 target_t *target = get_current_target(cmd_ctx);
3452 armv4_5_common_t *armv4_5;
3453 xscale_common_t *xscale;
3456 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3461 if (target->state != TARGET_HALTED)
3463 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
3467 if ((argc >= 1) && (strcmp("enable", args[0]) == 0))
3469 xscale_trace_data_t *td, *next_td;
3470 xscale->trace.buffer_enabled = 1;
3472 /* free old trace data */
3473 td = xscale->trace.data;
3483 xscale->trace.data = NULL;
3485 else if ((argc >= 1) && (strcmp("disable", args[0]) == 0))
3487 xscale->trace.buffer_enabled = 0;
3490 if ((argc >= 2) && (strcmp("fill", args[1]) == 0))
3493 xscale->trace.buffer_fill = strtoul(args[2], NULL, 0);
3495 xscale->trace.buffer_fill = 1;
3497 else if ((argc >= 2) && (strcmp("wrap", args[1]) == 0))
3499 xscale->trace.buffer_fill = -1;
3502 if (xscale->trace.buffer_enabled)
3504 /* if we enable the trace buffer in fill-once
3505 * mode we know the address of the first instruction */
3506 xscale->trace.pc_ok = 1;
3507 xscale->trace.current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
3511 /* otherwise the address is unknown, and we have no known good PC */
3512 xscale->trace.pc_ok = 0;
3515 command_print(cmd_ctx, "trace buffer %s (%s)",
3516 (xscale->trace.buffer_enabled) ? "enabled" : "disabled",
3517 (xscale->trace.buffer_fill > 0) ? "fill" : "wrap");
3519 dcsr_value = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 0, 32);
3520 if (xscale->trace.buffer_fill >= 0)
3521 xscale_write_dcsr_sw(target, (dcsr_value & 0xfffffffc) | 2);
3523 xscale_write_dcsr_sw(target, dcsr_value & 0xfffffffc);
3528 int xscale_handle_trace_image_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
3531 armv4_5_common_t *armv4_5;
3532 xscale_common_t *xscale;
3536 command_print(cmd_ctx, "usage: xscale trace_image <file> [base address] [type]");
3540 target = get_current_target(cmd_ctx);
3542 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3547 if (xscale->trace.image)
3549 image_close(xscale->trace.image);
3550 free(xscale->trace.image);
3551 command_print(cmd_ctx, "previously loaded image found and closed");
3554 xscale->trace.image = malloc(sizeof(image_t));
3555 xscale->trace.image->base_address_set = 0;
3556 xscale->trace.image->start_address_set = 0;
3558 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
3561 xscale->trace.image->base_address_set = 1;
3562 xscale->trace.image->base_address = strtoul(args[1], NULL, 0);
3566 xscale->trace.image->base_address_set = 0;
3569 if (image_open(xscale->trace.image, args[0], (argc >= 3) ? args[2] : NULL) != ERROR_OK)
3571 free(xscale->trace.image);
3572 xscale->trace.image = NULL;
3579 int xscale_handle_dump_trace_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
3581 target_t *target = get_current_target(cmd_ctx);
3582 armv4_5_common_t *armv4_5;
3583 xscale_common_t *xscale;
3584 xscale_trace_data_t *trace_data;
3587 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3592 if (target->state != TARGET_HALTED)
3594 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
3600 command_print(cmd_ctx, "usage: xscale dump_trace <file>");
3604 trace_data = xscale->trace.data;
3608 command_print(cmd_ctx, "no trace data collected");
3612 if (fileio_open(&file, args[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
3621 fileio_write_u32(&file, trace_data->chkpt0);
3622 fileio_write_u32(&file, trace_data->chkpt1);
3623 fileio_write_u32(&file, trace_data->last_instruction);
3624 fileio_write_u32(&file, trace_data->depth);
3626 for (i = 0; i < trace_data->depth; i++)
3627 fileio_write_u32(&file, trace_data->entries[i].data | ((trace_data->entries[i].type & 0xffff) << 16));
3629 trace_data = trace_data->next;
3632 fileio_close(&file);
3637 int xscale_handle_analyze_trace_buffer_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
3639 target_t *target = get_current_target(cmd_ctx);
3640 armv4_5_common_t *armv4_5;
3641 xscale_common_t *xscale;
3643 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3648 xscale_analyze_trace(target, cmd_ctx);
3653 int xscale_handle_cp15(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
3655 target_t *target = get_current_target(cmd_ctx);
3656 armv4_5_common_t *armv4_5;
3657 xscale_common_t *xscale;
3659 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3664 if (target->state != TARGET_HALTED)
3666 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
3673 reg_no = strtoul(args[0], NULL, 0);
3674 /*translate from xscale cp15 register no to openocd register*/
3678 reg_no = XSCALE_MAINID;
3681 reg_no = XSCALE_CTRL;
3684 reg_no = XSCALE_TTB;
3687 reg_no = XSCALE_DAC;
3690 reg_no = XSCALE_FSR;
3693 reg_no = XSCALE_FAR;
3696 reg_no = XSCALE_PID;
3699 reg_no = XSCALE_CPACCESS;
3702 command_print(cmd_ctx, "invalid register number");
3703 return ERROR_INVALID_ARGUMENTS;
3705 reg = &xscale->reg_cache->reg_list[reg_no];
3712 /* read cp15 control register */
3713 xscale_get_reg(reg);
3714 value = buf_get_u32(reg->value, 0, 32);
3715 command_print(cmd_ctx, "%s (/%i): 0x%x", reg->name, reg->size, value);
3720 u32 value = strtoul(args[1], NULL, 0);
3722 /* send CP write request (command 0x41) */
3723 xscale_send_u32(target, 0x41);
3725 /* send CP register number */
3726 xscale_send_u32(target, reg_no);
3728 /* send CP register value */
3729 xscale_send_u32(target, value);
3731 /* execute cpwait to ensure outstanding operations complete */
3732 xscale_send_u32(target, 0x53);
3736 command_print(cmd_ctx, "usage: cp15 [register]<, [value]>");
3742 int handle_xscale_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
3744 target_t *target = get_current_target(cmd_ctx);
3745 armv4_5_common_t *armv4_5;
3746 xscale_common_t *xscale;
3748 if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
3755 if (strcmp("enable", args[0]) == 0)
3757 xscale->fast_memory_access = 1;
3759 else if (strcmp("disable", args[0]) == 0)
3761 xscale->fast_memory_access = 0;
3765 return ERROR_COMMAND_SYNTAX_ERROR;
3769 return ERROR_COMMAND_SYNTAX_ERROR;
3772 command_print(cmd_ctx, "fast memory access is %s", (xscale->fast_memory_access) ? "enabled" : "disabled");
3777 int xscale_register_commands(struct command_context_s *cmd_ctx)
3779 command_t *xscale_cmd;
3781 xscale_cmd = register_command(cmd_ctx, NULL, "xscale", NULL, COMMAND_ANY, "xscale specific commands");
3783 register_command(cmd_ctx, xscale_cmd, "debug_handler", xscale_handle_debug_handler_command, COMMAND_ANY, "'xscale debug_handler <target#> <address>' command takes two required operands");
3784 register_command(cmd_ctx, xscale_cmd, "cache_clean_address", xscale_handle_cache_clean_address_command, COMMAND_ANY, NULL);
3786 register_command(cmd_ctx, xscale_cmd, "cache_info", xscale_handle_cache_info_command, COMMAND_EXEC, NULL);
3787 register_command(cmd_ctx, xscale_cmd, "mmu", xscale_handle_mmu_command, COMMAND_EXEC, "['enable'|'disable'] the MMU");
3788 register_command(cmd_ctx, xscale_cmd, "icache", xscale_handle_idcache_command, COMMAND_EXEC, "['enable'|'disable'] the ICache");
3789 register_command(cmd_ctx, xscale_cmd, "dcache", xscale_handle_idcache_command, COMMAND_EXEC, "['enable'|'disable'] the DCache");
3791 register_command(cmd_ctx, xscale_cmd, "vector_catch", xscale_handle_idcache_command, COMMAND_EXEC, "<mask> of vectors that should be catched");
3793 register_command(cmd_ctx, xscale_cmd, "trace_buffer", xscale_handle_trace_buffer_command, COMMAND_EXEC, "<enable|disable> ['fill' [n]|'wrap']");
3795 register_command(cmd_ctx, xscale_cmd, "dump_trace", xscale_handle_dump_trace_command, COMMAND_EXEC, "dump content of trace buffer to <file>");
3796 register_command(cmd_ctx, xscale_cmd, "analyze_trace", xscale_handle_analyze_trace_buffer_command, COMMAND_EXEC, "analyze content of trace buffer");
3797 register_command(cmd_ctx, xscale_cmd, "trace_image", xscale_handle_trace_image_command,
3798 COMMAND_EXEC, "load image from <file> [base address]");
3800 register_command(cmd_ctx, xscale_cmd, "cp15", xscale_handle_cp15, COMMAND_EXEC, "access coproc 15 <register> [value]");
3801 register_command(cmd_ctx, xscale_cmd, "fast_memory_access", handle_xscale_fast_memory_access_command,
3802 COMMAND_ANY, "use fast memory accesses instead of slower but potentially unsafe slow accesses <enable|disable>");
3805 armv4_5_register_commands(cmd_ctx);