2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/compiler.h>
13 #include <asm/processor.h>
14 #include <asm/cache.h>
15 #include <asm/immap_85xx.h>
16 #include <asm/fsl_fdt.h>
17 #include <asm/fsl_law.h>
18 #include <asm/fsl_serdes.h>
19 #include <asm/fsl_portals.h>
20 #include <asm/fsl_liodn.h>
22 #include "../common/sleep.h"
26 DECLARE_GLOBAL_DATA_PTR;
30 struct cpu_type *cpu = gd->arch.cpu;
33 #ifdef CONFIG_T104XD4RDB
34 printf("Board: %sD4RDB\n", cpu->name);
36 printf("Board: %sRDB\n", cpu->name);
38 printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
39 CPLD_READ(hw_ver), CPLD_READ(sw_ver));
41 sw = CPLD_READ(flash_ctl_status);
42 sw = ((sw & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
44 printf("vBank: %d\n", sw);
49 int board_early_init_f(void)
51 #if defined(CONFIG_DEEP_SLEEP)
53 fsl_dp_disable_console();
59 int board_early_init_r(void)
61 #ifdef CONFIG_SYS_FLASH_BASE
62 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
63 int flash_esel = find_tlb_idx((void *)flashbase, 1);
66 * Remap Boot flash region to caching-inhibited
67 * so that flash can be erased properly.
70 /* Flush d-cache and invalidate i-cache of any FLASH data */
74 if (flash_esel == -1) {
75 /* very unlikely unless something is messed up */
76 puts("Error: Could not find TLB for FLASH BASE\n");
77 flash_esel = 2; /* give our best effort to continue */
79 /* invalidate existing TLB entry for flash */
80 disable_tlb(flash_esel);
83 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
84 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
85 0, flash_esel, BOOKE_PAGESZ_256M, 1);
88 #ifdef CONFIG_SYS_DPAA_QBMAN
97 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
100 srds_s1 = in_be32(&gur->rcwsr[4]) >> 24;
102 printf("SERDES Reference : 0x%X\n", srds_s1);
106 CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) |
109 /* select SGMII and Aurora*/
111 CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) |
112 MISC_CTL_SG_SEL | MISC_CTL_AURORA_SEL);
114 #if defined(CONFIG_T1040D4RDB)
115 if (hwconfig("qe-tdm")) {
116 CPLD_WRITE(sfp_ctl_status, CPLD_READ(sfp_ctl_status) |
118 printf("QECSR : 0x%02x, mux to qe-tdm\n",
119 CPLD_READ(sfp_ctl_status));
121 /* Mask all CPLD interrupt sources, except QSGMII interrupts */
122 if (CPLD_READ(sw_ver) < 0x03) {
123 debug("CPLD SW version 0x%02x doesn't support int_mask\n",
126 CPLD_WRITE(int_mask, CPLD_INT_MASK_ALL &
127 ~(CPLD_INT_MASK_QSGMII1 | CPLD_INT_MASK_QSGMII2));
134 int ft_board_setup(void *blob, bd_t *bd)
139 ft_cpu_setup(blob, bd);
141 base = getenv_bootm_low();
142 size = getenv_bootm_size();
144 fdt_fixup_memory(blob, (u64)base, (u64)size);
147 pci_of_setup(blob, bd);
150 fdt_fixup_liodn(blob);
152 #ifdef CONFIG_HAS_FSL_DR_USB
153 fdt_fixup_dr_usb(blob, bd);
156 #ifdef CONFIG_SYS_DPAA_FMAN
157 fdt_fixup_fman_ethernet(blob);
160 if (hwconfig("qe-tdm"))