2 * Copyright 2015 Freescale Semiconductor, Inc.
4 * Author: Chunhe Lan <Chunhe.Lan@freescale.com>
6 * SPDX-License-Identifier: GPL-2.0+
15 #include <fsl_esdhc.h>
20 #define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
22 DECLARE_GLOBAL_DATA_PTR;
24 phys_size_t get_effective_memsize(void)
26 return CONFIG_SYS_L3_SIZE;
29 unsigned long get_board_sys_clk(void)
31 return CONFIG_SYS_CLK_FREQ;
34 unsigned long get_board_ddr_clk(void)
36 return CONFIG_DDR_CLK_FREQ;
39 void board_init_f(ulong bootflag)
41 u32 plat_ratio, sys_clk, ccb_clk;
42 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
44 /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
45 memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
47 /* Update GD pointer */
48 gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
50 /* compiler optimization barrier needed for GCC >= 3.4 */
51 __asm__ __volatile__("" : : : "memory");
55 /* initialize selected port with appropriate baud rate */
56 sys_clk = get_board_sys_clk();
57 plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
58 ccb_clk = sys_clk * plat_ratio / 2;
60 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
61 ccb_clk / 16 / CONFIG_BAUDRATE);
63 puts("\nSD boot...\n");
65 relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
68 void board_init_r(gd_t *gd, ulong dest_addr)
72 bd = (bd_t *)(gd + sizeof(gd_t));
73 memset(bd, 0, sizeof(bd_t));
75 bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
76 bd->bi_memsize = CONFIG_SYS_L3_SIZE;
80 mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
81 CONFIG_SPL_RELOC_MALLOC_SIZE);
84 mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
85 (uchar *)CONFIG_ENV_ADDR);
87 gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
92 gd->ram_size = initdram(0);