1 ################################################################################
3 # Generated for Atmel AT91SAM9RL-EK evaluation board using Atmel SAM-ICE (J-Link) V6
5 # Atmel AT91SAM9RL : PLL = 200 MHz, MCK = 100 MHz
6 # OSCSEL configured for external 32.768 kHz crystal
8 # 32-bit SDRAM : 2 x Micron MT48LC16M16A2, 4M x 16Bit x 4 Banks
10 ################################################################################
12 # We add to the minimal configuration.
13 source [find target/at91sam9rl.cfg]
15 $_TARGETNAME configure -event reset-start {
16 # At reset CPU runs at 32.768 kHz.
17 # JTAG Frequency must be 6 times slower if RCLK is not supported.
20 # RSTC_MR : enable user reset, MMU may be enabled... use physical address
21 mww phys 0xfffffd08 0xa5000501
24 $_TARGETNAME configure -event reset-init {
25 mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog
27 mww 0xfffffc20 0x00004001 ;# CKGR_MOR : enable the main oscillator
28 sleep 20 ;# wait 20 ms
29 mww 0xfffffc30 0x00000001 ;# PMC_MCKR : switch to main oscillator
30 sleep 10 ;# wait 10 ms
31 mww 0xfffffc28 0x2031bf03 ;# CKGR_PLLR: Set PLL Register for 200 MHz
32 sleep 20 ;# wait 20 ms
33 mww 0xfffffc30 0x00000101 ;# PMC_MCKR : Select prescaler (divide by 2)
34 sleep 10 ;# wait 10 ms
35 mww 0xfffffc30 0x00000102 ;# PMC_MCKR : Clock from PLL is selected (100 MHz)
36 sleep 10 ;# wait 10 ms
38 # Increase JTAG Speed to 6 MHz if RCLK is not supported
41 arm7_9 dcc_downloads enable ;# Enable faster DCC downloads
43 mww 0xfffff670 0xffff0000 ;# PIO_ASR : Select peripheral function for D16..D31 (PIOB)
44 mww 0xfffff604 0xffff0000 ;# PIO_PDR : Disable PIO function for D16..D31 (PIOB)
46 mww 0xffffef20 0x00010002 ;# EBI_CSA : Assign EBI Chip Select 1 to SDRAM, VDDIOMSEL set for +3V3 memory
48 mww 0xffffea08 0x85227259 ;# SDRAMC_CR : Configure SDRAM (2 x Micron MT48LC16M16A2 : 4M x 16Bit x 4 Banks)
50 mww 0xffffea00 0x1 ;# SDRAMC_MR : issue a NOP command
52 mww 0xffffea00 0x2 ;# SDRAMC_MR : issue an 'All Banks Precharge' command
54 mww 0xffffea00 0x4 ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
70 mww 0xffffea00 0x3 ;# SDRAMC_MR : issue a 'Load Mode Register' command
72 mww 0xffffea00 0x0 ;# SDRAMC_MR : normal mode
74 mww 0xffffea04 0x2b6 ;# SDRAMC_TR : Set refresh timer count to 7us