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arm720t: virt2phys callback added
[openocd] / tcl / board / topas910.cfg
1 ######################################
2 # Target:    Toshiba TOPAS910 -- TMPA910 Starterkit
3 #
4 ######################################
5
6 # We add to the minimal configuration.
7 source [find target/tmpa910.cfg]
8
9 ######################
10 # Target configuration
11 ######################
12
13 #$_TARGETNAME configure -event gdb-attach { reset init }
14 $_TARGETNAME configure -event reset-init { topas910_init }
15
16 proc topas910_init { } {
17 # Init PLL
18 # my settings
19         mww 0xf005000c 0x00000007
20         mww 0xf0050010 0x00000065
21         mww 0xf005000c 0x000000a7
22         sleep 10
23         mdw 0xf0050008
24         mww 0xf0050008 0x00000002
25         mww 0xf0050004 0x00000000
26 # NEW: set CLKCR5
27         mww 0xf0050054 0x00000040
28 #
29         sleep 10
30 # Init SDRAM
31 #  _PMCDRV          = 0x00000071;
32 #  //
33 #  // Initialize SDRAM timing paramater
34 #  //
35 #  _DMC_CAS_LATENCY = 0x00000006;
36 #  _DMC_T_DQSS      = 0x00000000;
37 #  _DMC_T_MRD       = 0x00000002;
38 #  _DMC_T_RAS       = 0x00000007;
39 #
40 #  _DMC_T_RC        = 0x0000000A;
41 #  _DMC_T_RCD       = 0x00000013;
42 #
43 #  _DMC_T_RFC       = 0x0000010A;
44 #
45 #  _DMC_T_RP        = 0x00000013;
46 #  _DMC_T_RRD       = 0x00000002;
47 #  _DMC_T_WR        = 0x00000002;
48 #  _DMC_T_WTR       = 0x00000001;
49 #  _DMC_T_XP        = 0x0000000A;
50 #  _DMC_T_XSR       = 0x0000000B;
51 #  _DMC_T_ESR       = 0x00000014;
52 #
53 #  //
54 #  // Configure SDRAM type parameter
55 #  _DMC_MEMORY_CFG  = 0x00008011;
56 #  _DMC_USER_CONFIG = 0x00000011;
57 #  // 32 bit memory interface
58 #
59 #
60 #  _DMC_REFRESH_PRD = 0x00000A60;
61 #  _DMC_CHIP_0_CFG  = 0x000140FC;
62 #
63 #  _DMC_DIRECT_CMD  = 0x000C0000;
64 #  _DMC_DIRECT_CMD  = 0x00000000;
65 #
66 #  _DMC_DIRECT_CMD  = 0x00040000;
67 #  _DMC_DIRECT_CMD  = 0x00040000;
68 #  _DMC_DIRECT_CMD  = 0x00080031;
69 #  //
70 #  // Finally start SDRAM
71 #  //
72 #  _DMC_MEMC_CMD    = MEMC_CMD_GO;
73 #  */
74
75         mww 0xf0020260 0x00000071
76         mww 0xf4300014 0x00000006
77         mww 0xf4300018 0x00000000
78         mww 0xf430001C 0x00000002
79         mww 0xf4300020 0x00000007
80         mww 0xf4300024 0x0000000A
81         mww 0xf4300028 0x00000013
82         mww 0xf430002C 0x0000010A
83         mww 0xf4300030 0x00000013
84         mww 0xf4300034 0x00000002
85         mww 0xf4300038 0x00000002
86         mww 0xf430003C 0x00000001
87         mww 0xf4300040 0x0000000A
88         mww 0xf4300044 0x0000000B
89         mww 0xf4300048 0x00000014
90         mww 0xf430000C 0x00008011
91         mww 0xf4300304 0x00000011
92         mww 0xf4300010 0x00000A60
93         mww 0xf4300200 0x000140FC
94         mww 0xf4300008 0x000C0000
95         mww 0xf4300008 0x00000000
96         mww 0xf4300008 0x00040000
97         mww 0xf4300008 0x00040000
98         mww 0xf4300008 0x00080031
99         mww 0xf4300004 0x00000000
100
101         sleep 10
102 #       jtag_khz NNNN
103
104 # remap off in case of IROM boot
105         mww 0xf0000004 0x00000001
106
107 }
108
109 # comment the following out if usinf J-Link, it soes not support DCC
110 arm7_9 dcc_downloads enable       # Enable faster DCC downloads
111
112
113 #####################
114 # Flash configuration
115 #####################
116
117 #flash bank cfi <base> <size> <chip width> <bus width> <target#>
118 set _FLASHNAME $_CHIPNAME.flash
119 flash bank $_FLASHNAME cfi 0x20000000 0x2000000 2 2 0