1 # NXP LPC1788 Cortex-M3 with 512kB Flash and 64kB Local On-Chip SRAM,
3 set CPUTAPID 0x4ba00477
7 # After reset the chip is clocked by the ~12MHz internal RC oscillator.
8 # When board-specific code (reset-init handler or device firmware)
9 # configures another oscillator and/or PLL0, set CCLK to match; if
10 # you don't, then flash erase and write operations may misbehave.
11 # (The ROM code doing those updates cares about core clock speed...)
13 # CCLK is the core clock frequency in KHz
16 #Include the main configuration file.
17 source [find target/lpc17xx.cfg];
19 # if srst is not fitted, use SYSRESETREQ to perform a soft reset
20 cortex_m3 reset_config sysresetreq