1 # Texas Instruments OMAP 2420
2 # http://www.ti.com/omap
4 if { [info exists CHIPNAME] } {
5 set _CHIPNAME $CHIPNAME
10 # NOTE: likes slowish clock on reset (1.5 MBit/s or less) or use RCLK
12 # Subsidiary TAP: ARM7TDMIr4 plus imaging ... must add via ICEpick (addr 6).
13 jtag newtap $_CHIPNAME iva -irlen 4 -ircapture 0x1 -irmask 0x3f -disable
15 # Subsidiary TAP: C55x DSP ... must add via ICEpick (addr 2).
16 jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x1 -irmask 0x3f -disable
18 # Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
19 if { [info exists ETB_TAPID ] } {
20 set _ETB_TAPID $ETB_TAPID
22 set _ETB_TAPID 0x2b900f0f
24 jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_ETB_TAPID
26 # Subsidiary TAP: ARM1136jf-s with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
27 if { [info exists CPU_TAPID ] } {
28 set _CPU_TAPID $CPU_TAPID
30 set _CPU_TAPID 0x07b3602f
32 jtag newtap $_CHIPNAME arm -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPU_TAPID
34 # Primary TAP: ICEpick-B (JTAG route controller) and boundary scan
35 if { [info exists JRC_TAPID ] } {
36 set _JRC_TAPID $JRC_TAPID
38 set _JRC_TAPID 0x01ce4801
40 jtag newtap $_CHIPNAME jrc -irlen 2 -ircapture 0x1 -irmask 0x3 -expected-id $_JRC_TAPID
42 # GDB target: the ARM.
43 set _TARGETNAME $_CHIPNAME.arm
44 target create $_TARGETNAME arm11 -chain-position $_TARGETNAME
46 # scratch: framebuffer, may be initially unavailable in some chips
47 $_TARGETNAME configure -work-area-phys 0x40210000
48 $_TARGETNAME configure -work-area-size 0x00081000
49 $_TARGETNAME configure -work-area-backup 0
52 # REVISIT ... as of 12-June-2009, OpenOCD's ETM code can't talk to ARM11 cores.
53 #etm config $_TARGETNAME 16 normal full etb
54 #etb config $_TARGETNAME $_CHIPNAME.etb