2 # http://focus.ti.com/docs/prod/folders/print/omap3530.html
3 # Other OMAP3 chips remove DSP and/or the OpenGL support
5 if { [info exists CHIPNAME] } {
6 set _CHIPNAME $CHIPNAME
11 # ICEpick-C ... used to route Cortex, DSP, and more not shown here
12 source [find target/icepick.cfg]
14 # Subsidiary TAP: C64x+ DSP ... must enable via ICEpick
15 jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable
17 # Subsidiary TAP: CoreSight Debug Access Port (DAP)
18 if { [info exists DAP_TAPID ] } {
19 set _DAP_TAPID $DAP_TAPID
21 set _DAP_TAPID 0x0b6d602f
23 jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf \
24 -expected-id $_DAP_TAPID -disable
25 jtag configure $_CHIPNAME.dap -event tap-enable \
26 "icepick_c_tapenable $_CHIPNAME.jrc 3"
28 # Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
29 if { [info exists JRC_TAPID ] } {
30 set _JRC_TAPID $JRC_TAPID
32 set _JRC_TAPID 0x0b7ae02f
34 jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
35 -expected-id $_JRC_TAPID
37 # GDB target: Cortex-A8, using DAP
38 set _TARGETNAME $_CHIPNAME.cpu
39 target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap
43 # the reset sequence is event-driven
44 # and kind of finicky...
46 # some TCK tycles are required to activate the DEBUG power domain
47 jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
49 # have the DAP "always" be active
50 jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
52 proc omap3_dbginit {target} {
53 # General Cortex A8 debug initialisation
55 # Enable DBGU signal for OMAP353x
56 $target mww 0x5401d030 0x00002000
59 # be absolutely certain the JTAG clock will work with the worst-case
60 # 16.8MHz/2 = 8.4MHz core clock, even before a bootloader kicks in.
61 # OK to speed up *after* PLL and clock tree setup.
63 $_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 }
65 # REVISIT This assumes that SRST is unavailable, so we must assert reset
66 # ourselves using PRM_RSTCTRL. RST_GS (2) is a warm reset, like ICEpick
67 # would issue. RST_DPLL3 (4) is a cold reset.
68 set PRM_RSTCTRL 0x48307250
69 $_TARGETNAME configure -event reset-assert-pre "$_TARGETNAME mww $PRM_RSTCTRL 2"
71 $_TARGETNAME configure -event reset-assert-post "omap3_dbginit $_TARGETNAME"