2 # http://focus.ti.com/docs/prod/folders/print/omap3530.html
3 # Other OMAP3 chips remove DSP and/or the OpenGL support
5 if { [info exists CHIPNAME] } {
6 set _CHIPNAME $CHIPNAME
11 # ICEpick-C ... used to route Cortex, DSP, and more not shown here
12 source [find target/icepick.cfg]
14 # Subsidiary TAP: C64x+ DSP ... must enable via ICEpick
15 jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable
17 # Subsidiary TAP: CoreSight Debug Access Port (DAP)
18 if { [info exists DAP_TAPID ] } {
19 set _DAP_TAPID $DAP_TAPID
21 set _DAP_TAPID 0x0b6d602f
23 jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf \
24 -expected-id $_DAP_TAPID -disable
25 jtag configure $_CHIPNAME.dap -event tap-enable \
26 "icepick_c_tapenable $_CHIPNAME.jrc 3"
28 # Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
29 if { [info exists JRC_TAPID ] } {
30 set _JRC_TAPID $JRC_TAPID
32 set _JRC_TAPID 0x0b7ae02f
34 jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
35 -expected-id $_JRC_TAPID
37 # GDB target: Cortex-A8, using DAP
39 # FIXME when we have A8 support, use it. A8 != M3 ...
40 target create omap3.cpu cortex_m3 -chain-position $_CHIPNAME.dap
42 # FIXME much of this should be in reset event handlers
43 proc omap3_dbginit { } {
47 jtag tapenable omap3530.dap
56 # 0xd401.1000 - Cortex-A8
57 # 0xd401.9000 - TPIU (traceport)
59 # 0xd401.d000 - DAPCTL
61 omap3.cpu mww 0x54011FB0 0xC5ACCE55
63 omap3.cpu mdw 0x54011314
64 omap3.cpu mdw 0x54011314
65 # omap3.cpu mdw 0x54011080
67 omap3.cpu mww 0x5401d030 0x00002000