3 if { [info exists CHIPNAME] } {
4 set _CHIPNAME $CHIPNAME
10 # Although the OMAP4430 supposedly has an ICEpick-D, only the
11 # ICEpick-C router commands seem to work.
12 # See http://processors.wiki.ti.com/index.php/ICEPICK
13 source [find target/icepick.cfg]
19 if { [info exists DAP_TAPID] } {
20 set _DAP_TAPID $DAP_TAPID
22 set _DAP_TAPID 0x3BA00477
25 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
26 -expected-id $_DAP_TAPID -disable
27 jtag configure $_CHIPNAME.cpu -event tap-enable \
28 "icepick_c_tapenable $_CHIPNAME.jrc 9"
32 # M3 DAPs, one per core
34 if { [info exists M3_DAP_TAPID] } {
35 set _M3_DAP_TAPID $M3_DAP_TAPID
37 set _M3_DAP_TAPID 0x4BA00477
40 jtag newtap $_CHIPNAME m31 -irlen 4 -ircapture 0x1 -irmask 0xf \
41 -expected-id $_M3_DAP_TAPID -disable
42 jtag configure $_CHIPNAME.m31 -event tap-enable \
43 "icepick_c_tapenable $_CHIPNAME.jrc 5"
45 jtag newtap $_CHIPNAME m30 -irlen 4 -ircapture 0x1 -irmask 0xf \
46 -expected-id $_M3_DAP_TAPID -disable
47 jtag configure $_CHIPNAME.m30 -event tap-enable \
48 "icepick_c_tapenable $_CHIPNAME.jrc 4"
52 # ICEpick-D JRC (JTAG route controller)
54 if { [info exists JRC_TAPID] } {
55 set _JRC_TAPID $JRC_TAPID
57 set _JRC_TAPID 0x3b95c02f
58 set _JRC_TAPID2 0x1b85202f
61 # PandaBoard REV EA1 (PEAP platforms)
62 if { [info exists JRC_TAPID2] } {
63 set _JRC_TAPID2 $JRC_TAPID2
65 set _JRC_TAPID2 0x1b85202f
70 jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
71 -expected-id $_JRC_TAPID -expected-id $_JRC_TAPID2
73 # Required by ICEpick to power-up the debug domain
74 jtag configure $_CHIPNAME.jrc -event post-reset "runtest 200"
78 # GDB target: Cortex-A9, using DAP
80 # The debugger can connect to either core of the A9, but currently
81 # not both simultaneously. Change -coreid to 1 to connect to the
84 set _TARGETNAME $_CHIPNAME.cpu
86 # APB DBGBASE reads 0x80040000, but this points to an empty ROM table.
87 # 0x80000000 is cpu0 coresight region
90 # CORTEX_A8_PADDRDBG_CPU_SHIFT 13
91 # 0x80000000 | (coreid << CORTEX_A8_PADDRDBG_CPU_SHIFT)
94 set _dbgbase [expr 0x80000000 | ($_coreid << 13)]
95 echo "Using dbgbase = [format 0x%x $_dbgbase]"
97 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
98 target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap \
99 -coreid 0 -dbgbase $_dbgbase
101 # SRAM: 56KiB at 0x4030.0000
102 $_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x1000
106 # M3 targets, separate TAP/DAP for each core
108 dap create $_CHIPNAME.m30_dap -chain-position $_CHIPNAME.m30
109 dap create $_CHIPNAME.m31_dap -chain-position $_CHIPNAME.m31
110 target create $_CHIPNAME.m30 cortex_m -dap $_CHIPNAME.m30_dap
111 target create $_CHIPNAME.m31 cortex_m -dap $_CHIPNAME.m31_dap
114 # Once the JRC is up, enable our TAPs
115 jtag configure $_CHIPNAME.jrc -event setup "
116 jtag tapenable $_CHIPNAME.cpu
117 jtag tapenable $_CHIPNAME.m30
118 jtag tapenable $_CHIPNAME.m31
121 # Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
122 # ourselves using PRM_RSTCTRL. 1 is a warm reset, 2 a cold reset.
123 set PRM_RSTCTRL 0x4A307B00
124 $_TARGETNAME configure -event reset-assert "$_TARGETNAME mww phys $PRM_RSTCTRL 0x1"
125 $_CHIPNAME.m30 configure -event reset-assert { }
126 $_CHIPNAME.m31 configure -event reset-assert { }
128 # Soft breakpoints don't currently work due to broken cache handling
129 gdb_breakpoint_override hard