2 # Silicon Laboratories SiM3x Cortex-M3
5 # SiM3x devices support both JTAG and SWD transports.
6 source [find target/swj-dp.tcl]
8 if { [info exists CHIPNAME] } {
9 set _CHIPNAME $CHIPNAME
14 if { [info exists CPUTAPID] } {
15 set _CPUTAPID $CPUTAPID
17 set _CPUTAPID 0x4ba00477
20 if { [info exists CPURAMSIZE] } {
21 set _CPURAMSIZE $CPURAMSIZE
23 # Minimum size of RAM in the Silicon Labs product matrix (8KB)
24 set _CPURAMSIZE 0x2000
27 if { [info exists CPUROMSIZE] } {
28 set _CPUROMSIZE $CPUROMSIZE
30 # Minimum size of FLASH in the Silicon Labs product matrix (32KB)
31 set _CPUROMSIZE 0x8000
34 if { [info exists WORKAREASIZE] } {
35 set _WORKAREASIZE $WORKAREASIZE
37 set _WORKAREASIZE $_CPURAMSIZE
40 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
42 set _TARGETNAME $_CHIPNAME.cpu
43 target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
45 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
47 set _FLASHNAME $_CHIPNAME.flash
48 flash bank $_FLASHNAME sim3x 0 $_CPUROMSIZE 0 0 $_TARGETNAME
52 adapter_nsrst_delay 100