3 if { [info exists CHIPNAME] } {
4 set _CHIPNAME $CHIPNAME
9 if { [info exists ENDIAN] } {
21 #use combined on interfaces or targets that can't set TRST/SRST separately
22 reset_config trst_and_srst
25 if { [info exists CPUTAPID ] } {
26 set _CPUTAPID $CPUTAPID
28 # See STM Document RM0008
30 set _CPUTAPID 0x3ba00477
32 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
34 if { [info exists BSTAPID ] } {
37 # See STM Document RM0008
39 # Low density devices, Rev A
40 set _BSTAPID1 0x06412041
41 # Medium density devices, Rev A
42 set _BSTAPID2 0x06410041
43 # Medium density devices, Rev B and Rev Z
44 set _BSTAPID3 0x16410041
45 # High density devices, Rev A
46 set _BSTAPID4 0x06414041
48 jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID1 -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 -expected-id $_BSTAPID4
50 set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
51 target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
53 $_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
55 flash bank stm32x 0 0 0 0 0
57 # For more information about the configuration files, take a look at: