1 # script for stm32f0x family
4 # stm32 devices support SWD transports only.
6 source [find target/swj-dp.tcl]
7 source [find mem_helper.tcl]
9 if { [info exists CHIPNAME] } {
10 set _CHIPNAME $CHIPNAME
12 set _CHIPNAME stm32f0x
17 # Work-area is a space in RAM used for flash programming
19 if { [info exists WORKAREASIZE] } {
20 set _WORKAREASIZE $WORKAREASIZE
22 set _WORKAREASIZE 0x1000
26 if { [info exists CPUTAPID] } {
27 set _CPUTAPID $CPUTAPID
29 # See STM Document RM0091
31 set _CPUTAPID 0x0bb11477
34 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
36 set _TARGETNAME $_CHIPNAME.cpu
37 target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
39 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
41 # flash size will be probed
42 set _FLASHNAME $_CHIPNAME.flash
43 flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME
45 # adapter speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
48 adapter_nsrst_delay 100
50 reset_config srst_nogate
53 # if srst is not fitted use SYSRESETREQ to
54 # perform a soft reset
55 cortex_m reset_config sysresetreq
58 proc stm32f0x_default_reset_start {} {
59 # Reset clock is HSI (8 MHz)
63 proc stm32f0x_default_examine_end {} {
64 # Enable debug during low power modes (uses more power)
65 mmw 0x40015804 0x00000006 0 ;# DBGMCU_CR |= DBG_STANDBY | DBG_STOP
67 # Stop watchdog counters during halt
68 mmw 0x40015808 0x00001800 0 ;# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
71 proc stm32f0x_default_reset_init {} {
72 # Configure PLL to boost clock to HSI x 6 (48 MHz)
73 mww 0x40021004 0x00100000 ;# RCC_CFGR = PLLMUL[2]
74 mmw 0x40021000 0x01000000 0 ;# RCC_CR[31:16] |= PLLON
75 mww 0x40022000 0x00000011 ;# FLASH_ACR = PRFTBE | LATENCY[0]
76 sleep 10 ;# Wait for PLL to lock
77 mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1]
79 # Boost JTAG frequency
84 $_TARGETNAME configure -event examine-end { stm32f0x_default_examine_end }
85 $_TARGETNAME configure -event reset-start { stm32f0x_default_reset_start }
86 $_TARGETNAME configure -event reset-init { stm32f0x_default_reset_init }