1 # script for stm32f1x family
4 # stm32 devices support both JTAG and SWD transports.
6 source [find target/swj-dp.tcl]
7 source [find mem_helper.tcl]
9 if { [info exists CHIPNAME] } {
10 set _CHIPNAME $CHIPNAME
12 set _CHIPNAME stm32f1x
17 # Work-area is a space in RAM used for flash programming
18 # By default use 4kB (as found on some STM32F100s)
19 if { [info exists WORKAREASIZE] } {
20 set _WORKAREASIZE $WORKAREASIZE
22 set _WORKAREASIZE 0x1000
25 # Allow overriding the Flash bank size
26 if { [info exists FLASH_SIZE] } {
27 set _FLASH_SIZE $FLASH_SIZE
34 if { [info exists CPUTAPID] } {
35 set _CPUTAPID $CPUTAPID
38 # See STM Document RM0008 Section 26.6.3
39 set _CPUTAPID 0x3ba00477
41 # this is the SW-DP tap id not the jtag tap id
42 set _CPUTAPID 0x1ba01477
46 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
47 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
50 jtag newtap $_CHIPNAME bs -irlen 5
53 set _TARGETNAME $_CHIPNAME.cpu
54 target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
56 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
58 # flash size will be probed
59 set _FLASHNAME $_CHIPNAME.flash
60 flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME
62 # JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
65 adapter_nsrst_delay 100
70 reset_config srst_nogate
73 # if srst is not fitted use SYSRESETREQ to
74 # perform a soft reset
75 cortex_m reset_config sysresetreq
78 $_TARGETNAME configure -event examine-end {
79 # DBGMCU_CR |= DBG_WWDG_STOP | DBG_IWDG_STOP |
80 # DBG_STANDBY | DBG_STOP | DBG_SLEEP
81 mmw 0xE0042004 0x00000307 0
84 $_TARGETNAME configure -event trace-config {
85 # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
86 # change this value accordingly to configure trace pins
88 mmw 0xE0042004 0x00000020 0