4 # stm32 devices support both JTAG and SWD transports.
6 source [find target/swj-dp.tcl]
8 if { [info exists CHIPNAME] } {
9 set _CHIPNAME $CHIPNAME
14 if { [info exists ENDIAN] } {
20 # Work-area is a space in RAM used for flash programming
22 if { [info exists WORKAREASIZE] } {
23 set _WORKAREASIZE $WORKAREASIZE
25 set _WORKAREASIZE 0x2800
28 # JTAG speed should be <= F_CPU/6.
29 # F_CPU after reset is 2MHz, so use F_JTAG max = 333kHz
32 adapter_nsrst_delay 100
38 if { [info exists CPUTAPID] } {
39 set _CPUTAPID $CPUTAPID
41 # See STM Document RM0038
43 set _CPUTAPID 0x4ba00477
46 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
48 if { [info exists BSTAPID] } {
49 # FIXME this never gets used to override defaults...
52 # See STM Document RM0038
54 set _BSTAPID 0x06416041
58 jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID
61 set _TARGETNAME $_CHIPNAME.cpu
62 target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
64 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
66 # flash size will be probed
67 set _FLASHNAME $_CHIPNAME.flash
68 flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
70 # if srst is not fitted use SYSRESETREQ to
71 # perform a soft reset
72 cortex_m reset_config sysresetreq
74 proc stm32l_enable_HSI {} {
75 # Enable HSI as clock source
76 echo "STM32L: Enabling HSI"
79 mww 0x40023800 0x00000101
82 mww 0x40023808 0x00000001
88 $_TARGETNAME configure -event reset-init {