2 # Texas Instruments DaVinci family: TMS320DM355
4 if { [info exists CHIPNAME] } {
5 set _CHIPNAME $CHIPNAME
9 if { [info exists ENDIAN] } {
15 # TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*
16 # after JTAG reset until ICEpick is used to route them in.
19 # With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without
20 # needing any ICEpick interaction.
23 source [find target/icepick.cfg]
26 # Also note: when running without RTCK before the PLLs are set up, you
27 # may need to slow the JTAG clock down quite a lot (under 2 MHz).
30 # Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
31 if { [info exists ETB_TAPID ] } {
32 set _ETB_TAPID $ETB_TAPID
34 set _ETB_TAPID 0x2b900f0f
36 jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf \
37 -expected-id $_ETB_TAPID $EMU01
38 jtag configure $_CHIPNAME.etb -event tap-enable \
39 "icepick_c_tapenable $_CHIPNAME.jrc 1"
41 # Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
42 if { [info exists CPU_TAPID ] } {
43 set _CPU_TAPID $CPU_TAPID
45 set _CPU_TAPID 0x07926001
47 jtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0xf \
48 -expected-id $_CPU_TAPID $EMU01
49 jtag configure $_CHIPNAME.arm -event tap-enable \
50 "icepick_c_tapenable $_CHIPNAME.jrc 0"
52 # Primary TAP: ICEpick (JTAG route controller) and boundary scan
53 if { [info exists JRC_TAPID ] } {
54 set _JRC_TAPID $JRC_TAPID
56 set _JRC_TAPID 0x0b73b02f
58 jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID
62 # various symbol definitions, to avoid hard-wiring addresses
63 # and enable some sharing of DaVinci-family utility code
65 set dm355 [ dict create ]
67 # Physical addresses for controllers and memory
68 # (Some of these are valid for many DaVinci family chips)
69 dict set dm355 sram0 0x00010000
70 dict set dm355 sram1 0x00014000
71 dict set dm355 sysbase 0x01c40000
72 dict set dm355 pllc1 0x01c40800
73 dict set dm355 pllc2 0x01c40c00
74 dict set dm355 psc 0x01c41000
75 dict set dm355 gpio 0x01c67000
76 dict set dm355 a_emif 0x01e10000
77 dict set dm355 a_emif_cs0 0x02000000
78 dict set dm355 a_emif_cs1 0x04000000
79 dict set dm355 ddr_emif 0x20000000
80 dict set dm355 ddr 0x80000000
81 dict set dm355 uart0 0x01c20000
82 dict set dm355 uart1 0x01c20400
83 dict set dm355 uart2 0x01e06000
85 source [find target/davinci.cfg]
88 # GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 16K)
89 # and the ETB memory (4K) are other options, while trace is unused.
90 set _TARGETNAME $_CHIPNAME.arm
92 target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
94 # NOTE that work-area-virt presumes a Linux 2.6.30-rc2+ kernel,
95 # and that the work area is used only with a kernel mmu context ...
96 $_TARGETNAME configure \
97 -work-area-virt [expr 0xfffe0000 + 0x4000] \
98 -work-area-phys [dict get $dm355 sram1] \
99 -work-area-size 0x4000 \
102 # be absolutely certain the JTAG clock will work with the worst-case
103 # CLKIN = 24 MHz (best case: 36 MHz) even when no bootloader turns
104 # on the PLL and starts using it. OK to speed up after clock setup.
106 $_TARGETNAME configure -event "reset-start" { jtag_rclk 1500 }
108 arm7_9 fast_memory_access enable
109 arm7_9 dcc_downloads enable
112 etm config $_TARGETNAME 16 normal full etb
113 etb config $_TARGETNAME $_CHIPNAME.etb