2 # Texas Instruments DaVinci family: TMS320DM6446
4 if { [info exists CHIPNAME] } {
5 set _CHIPNAME $CHIPNAME
11 # For now, expect EMU0/EMU1 jumpered LOW (not TI's default) so ARM and ETB
12 # are enabled without making ICEpick route ARM and ETB into the JTAG chain.
13 # Override by setting EMU01 to "-disable".
15 # Also note: when running without RTCK before the PLLs are set up, you
16 # may need to slow the JTAG clock down quite a lot (under 2 MHz).
18 source [find target/icepick.cfg]
22 # Subsidiary TAP: unknown ... must enable via ICEpick
23 jtag newtap $_CHIPNAME unknown -irlen 8 -ircapture 0xff -irmask 0xff -disable
24 jtag configure $_CHIPNAME.unknown -event tap-enable \
25 "icepick_c_tapenable $_CHIPNAME.jrc 3"
27 # Subsidiary TAP: C64x+ DSP ... must enable via ICEpick
28 jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable
29 jtag configure $_CHIPNAME.dsp -event tap-enable \
30 "icepick_c_tapenable $_CHIPNAME.jrc 2"
32 # Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
33 if { [info exists ETB_TAPID ] } {
34 set _ETB_TAPID $ETB_TAPID
36 set _ETB_TAPID 0x2b900f0f
38 jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf \
39 -expected-id $_ETB_TAPID $EMU01
40 jtag configure $_CHIPNAME.etb -event tap-enable \
41 "icepick_c_tapenable $_CHIPNAME.jrc 1"
43 # Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
44 if { [info exists CPU_TAPID ] } {
45 set _CPU_TAPID $CPU_TAPID
47 set _CPU_TAPID 0x07926001
49 jtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0xf \
50 -expected-id $_CPU_TAPID $EMU01
51 jtag configure $_CHIPNAME.arm -event tap-enable \
52 "icepick_c_tapenable $_CHIPNAME.jrc 0"
54 # Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
55 if { [info exists JRC_TAPID ] } {
56 set _JRC_TAPID $JRC_TAPID
58 set _JRC_TAPID 0x0b70002f
60 jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
61 -expected-id $_JRC_TAPID
63 # GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 8K)
64 # and the ETB memory (4K) are other options, while trace is unused.
65 # Little-endian; use the OpenOCD default.
66 set _TARGETNAME $_CHIPNAME.arm
68 target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
69 $_TARGETNAME configure -work-area-phys 0x0000a000 -work-area-size 0x2000
71 arm7_9 fast_memory_access enable
72 arm7_9 dcc_downloads enable
75 etm config $_TARGETNAME 16 normal full etb
76 etb config $_TARGETNAME $_CHIPNAME.etb