2 # Texas Instruments DaVinci family: TMS320DM6446
4 if { [info exists CHIPNAME] } {
5 set _CHIPNAME $CHIPNAME
9 if { [info exists ENDIAN] } {
16 # For now, expect EMU0/EMU1 jumpered LOW (not TI's default) so ARM and ETB
17 # are enabled without making ICEpick route ARM and ETB into the JTAG chain.
19 # Also note: when running without RTCK before the PLLs are set up, you
20 # may need to slow the JTAG clock down quite a lot (under 2 MHz).
23 # Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
24 if { [info exists ETB_TAPID ] } {
25 set _ETB_TAPID $ETB_TAPID
27 set _ETB_TAPID 0x2b900f0f
29 jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_ETB_TAPID
31 # Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
32 if { [info exists CPU_TAPID ] } {
33 set _CPU_TAPID $CPU_TAPID
35 set _CPU_TAPID 0x07926001
37 jtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPU_TAPID
39 # Subsidiary TAP: C64x+ DSP ... NOT CURRENTLY INCLUDED, must add via ICEpick.
40 # Documentation for DSP JTAG interfaces evidently needs NDAs.
42 # Primary TAP: ICEpick (JTAG route controller) and boundary scan
43 if { [info exists JRC_TAPID ] } {
44 set _JRC_TAPID $JRC_TAPID
46 set _JRC_TAPID 0x0b70002f
48 jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID
50 # GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 8K)
51 # and the ETB memory (4K) are other options, while trace is unused.
52 set _TARGETNAME $_CHIPNAME.arm
54 target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
55 $_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x0000a000 -work-area-size 0x2000 -work-area-backup 0
58 arm7_9 fast_memory_access enable
59 arm7_9 dcc_downloads enable
62 # FIXME we ought to be able to say "... config $_TARGETNAME ..."
63 # (not "config 0") facilitating additional targets (e.g. other chips)
64 etm config 0 16 normal full etb
65 etb config 0 $_CHIPNAME.etb