3 <title>Test results for revision 607</title>
8 <H2>Test case results</H2>
9 The test results are stored in seperate documents. One document for
10 each subversion number.
12 <tr><td>Test results</td><td>comment</td></tr>
13 <tr><td>607</a></td><td></td></tr>
14 <tr><td><a href="results/template.html">template</a></td><td>Test results template</td></tr>
26 <td>Initial state</td>
28 <td>Expected output</td>
29 <td>Actual output</td>
33 <td><a name="CON001"/>CON001</td>
36 <td>Telnet connection</td>
37 <td>Power on, jtag target attached</td>
38 <td>On console, type<br><code>telnet ip port</code></td>
39 <td><code>Open On-Chip Debugger<br>></code></td>
40 <td><code>Open On-Chip Debugger<br>></code></td>
44 <td><a name="CON002"/>CON002</td>
47 <td>GDB server connection</td>
48 <td>Power on, jtag target attached</td>
49 <td>On GDB console, type<br><code>target remote ip:port</code></td>
50 <td><code>Remote debugging using 10.0.0.73:3333</code></td>
51 <td><code>Remote debugging using 10.0.0.73:3333</code></td>
63 <td>Initial state</td>
65 <td>Expected output</td>
66 <td>Actual output</td>
70 <td><a name="RES001"/>RES001</td>
73 <td>Reset halt on a blank target</td>
74 <td>Erase all the content of the flash</td>
75 <td>Connect via the telnet interface and type <br><code>reset halt</code></td>
76 <td>Reset should return without error and the output should contain<br><code>target state: halted<br>pc = 0</code></td>
79 JTAG device found: 0x3f0f0f0f (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)<br>
80 nSRST pulls nTRST, falling back to "reset run_and_halt"<br>
81 target state: halted<br>
82 target halted in ARM state due to debug request, current mode: Supervisor<br>
83 cpsr: 0x60000013 pc: 0x00100178
89 <td><a name="RES002"/>RES002</td>
92 <td>Reset init on a blank target</td>
93 <td>Erase all the content of the flash</td>
94 <td>Connect via the telnet interface and type <br><code>reset init</code></td>
95 <td>Reset should return without error and the output should contain <br><code>executing reset script 'name_of_the_script'</code></td>
98 JTAG device found: 0x3f0f0f0f (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)<br>
99 nSRST pulls nTRST, falling back to "reset run_and_init"<br>
100 target state: halted<br>
101 target halted in ARM state due to debug request, current mode: Supervisor<br>
102 cpsr: 0x600000d3 pc: 0x00003e24<br>
103 executing reset script 'event/sam7s256_reset.script'
109 <td><a name="RES003"/>RES003</td>
112 <td>Reset after a power cycle of the target</td>
113 <td>Reset the target then power cycle the target</td>
114 <td>Connect via the telnet interface and type <br><code>reset halt</code> after the power was detected</td>
115 <td>Reset should return without error and the output should contain<br><code>target state: halted</code></td>
118 JTAG device found: 0x3f0f0f0f (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)<br>
119 nSRST pulls nTRST, falling back to "reset run_and_halt"<br>
120 target state: halted<br>
121 target halted in ARM state due to debug request, current mode: Supervisor<br>
122 cpsr: 0x300000d3 pc: 0x00003a38
136 <td>Initial state</td>
138 <td>Expected output</td>
139 <td>Actual output</td>
143 <td><a name="SPD001"/>RES001</td>
146 <td>16MHz on normal operation</td>
147 <td>Reset init the target according to RES002 </td>
148 <td>Exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
149 <td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
154 0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
155 0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
156 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
157 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
171 <td>Initial state</td>
173 <td>Expected output</td>
174 <td>Actual output</td>
178 <td><a name="DBG001"/>DBG001</td>
181 <td>Load is working</td>
182 <td>Reset init is working, RAM is accesible, GDB server is started</td>
183 <td>On the console of the OS: <br>
184 <code>arm-elf-gdb test_ram.elf</code><br>
185 <code>(gdb) target remote ip:port</code><br>
186 <code>(gdb) load</load>
188 <td>Load should return without error, typical output looks like:<br>
190 Loading section .text, size 0x14c lma 0x0<br>
191 Start address 0x40, load size 332<br>
192 Transfer rate: 180 bytes/sec, 332 bytes/write.<br>
197 Loading section .text, size 0x194 lma 0x200000<br>
198 Start address 0x200040, load size 404<br>
199 Transfer rate: 17470 bits/sec, 404 bytes/write.
204 <td><a name="DBG002"/>DBG002</td>
207 <td>Software breakpoint</td>
208 <td>Load the test_ram.elf application, use instructions from GDB001</td>
209 <td>In the GDB console:<br>
211 (gdb) monitor arm7_9 sw_bkpts enable<br>
212 software breakpoints enabled<br>
214 Breakpoint 1 at 0xec: file src/main.c, line 71.<br>
219 <td>The software breakpoint should be reached, a typical output looks like:<br>
221 target state: halted<br>
222 target halted in ARM state due to breakpoint, current mode: Supervisor<br>
223 cpsr: 0x000000d3 pc: 0x000000ec<br>
225 Breakpoint 1, main () at src/main.c:71<br>
232 Breakpoint 2 at 0x200134: file src/main.c, line 69.<br>
235 target state: halted<br>
236 target halted in ARM state due to breakpoint, current mode: Supervisor<br>
237 cpsr: 0x60000013 pc: 0x00200134<br>
239 Breakpoint 2, main () at src/main.c:69<br>
246 <td><a name="DBG003"/>DBG003</td>
249 <td>Single step in a RAM application</td>
250 <td>Load the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002</td>
251 <td>In GDB, type <br><code>(gdb) step</code></td>
252 <td>The next instruction should be reached, typical output:<br>
255 target state: halted<br>
256 target halted in ARM state due to single step, current mode: Abort<br>
257 cpsr: 0x20000097 pc: 0x000000f0<br>
258 target state: halted<br>
259 target halted in ARM state due to single step, current mode: Abort<br>
260 cpsr: 0x20000097 pc: 0x000000f4<br>
267 target state: halted<br>
268 target halted in ARM state due to single step, current mode: Abort<br>
269 cpsr: 0x20000097 pc: 0x000000f0<br>
270 target state: halted<br>
271 target halted in ARM state due to single step, current mode: Abort<br>
272 cpsr: 0x20000097 pc: 0x000000f4<br>
279 <td><a name="DBG004"/>DBG004</td>
282 <td>Software break points are working after a reset</td>
283 <td>Load the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002</td>
284 <td>In GDB, type <br><code>
285 (gdb) monitor reset<br>
289 <td>The breakpoint should be reached, typical output:<br>
291 target state: halted<br>
292 target halted in ARM state due to breakpoint, current mode: Supervisor<br>
293 cpsr: 0x000000d3 pc: 0x000000ec<br>
295 Breakpoint 1, main () at src/main.c:71<br>
301 JTAG device found: 0x3f0f0f0f (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)<br>
302 target state: halted<br>
303 target halted in ARM state due to debug request, current mode: Supervisor<br>
304 cpsr: 0x600000d3 pc: 0x00003e28<br>
305 executing reset script 'event/sam7s256_reset.script'<br>
307 Loading section .text, size 0x194 lma 0x200000<br>
308 Start address 0x200040, load size 404<br>
309 Transfer rate: 20455 bits/sec, 404 bytes/write.<br>
312 target state: halted<br>
313 target halted in ARM state due to breakpoint, current mode: Supervisor<br>
314 cpsr: 0x60000013 pc: 0x00200134<br>
316 Breakpoint 2, main () at src/main.c:69<br>
322 <td><a name="DBG005"/>DBG005</td>
325 <td>Hardware breakpoint</td>
326 <td>Flash the test_rom.elf application. Make this test after FLA004 has passed</td>
327 <td>Be sure that <code>gdb_memory_map</code> and <code>gdb_flash_program</code> are enabled. In GDB, type <br>
329 (gdb) monitor reset<br>
331 Loading section .text, size 0x194 lma 0x100000<br>
332 Start address 0x100040, load size 404<br>
333 Transfer rate: 179 bytes/sec, 404 bytes/write.<br>
334 (gdb) monitor arm7_9 force_hw_bkpts enable<br>
335 force hardware breakpoints enabled<br>
337 Breakpoint 1 at 0x100134: file src/main.c, line 69.<br>
341 <td>The breakpoint should be reached, typical output:<br>
345 Breakpoint 1, main () at src/main.c:69<br>
352 Breakpoint 1 at 0x100134: file src/main.c, line 69.<br>
355 target state: halted<br>
356 target halted in ARM state due to breakpoint, current mode: Supervisor<br>
357 cpsr: 0x60000013 pc: 0x00100134<br>
359 Breakpoint 1, main () at src/main.c:69<br>
366 <td><a name="DBG006"/>DBG006</td>
369 <td>Hardware breakpoint is set after a reset</td>
370 <td>Follow the instructions to flash and insert a hardware breakpoint from DBG005</td>
371 <td>In GDB, type <br>
373 (gdb) monitor reset<br>
374 (gdb) monitor reg pc 0x100000<br>
375 pc (/32): 0x00100000<br>
378 where the value inserted in PC is the start address of the application
380 <td>The breakpoint should be reached, typical output:<br>
384 Breakpoint 1, main () at src/main.c:69<br>
391 target state: halted<br>
392 target halted in ARM state due to single step, current mode: Supervisor<br>
393 cpsr: 0x60000013 pc: 0x00100040<br>
394 target state: halted<br>
395 target halted in ARM state due to breakpoint, current mode: Supervisor<br>
396 cpsr: 0x60000013 pc: 0x00100134<br>
398 Breakpoint 1, main () at src/main.c:69<br>
401 <b>Aren't there too many "halted" signs?</b>
406 <td><a name="DBG007"/>DBG007</td>
409 <td>Single step in ROM</td>
410 <td>Flash the test_rom.elf application and set a breakpoint in main, use DBG005. Make this test after FLA004 has passed</td>
411 <td>Be sure that <code>gdb_memory_map</code> and <code>gdb_flash_program</code> are enabled. In GDB, type <br>
413 (gdb) monitor reset<br>
415 Loading section .text, size 0x194 lma 0x100000<br>
416 Start address 0x100040, load size 404<br>
417 Transfer rate: 179 bytes/sec, 404 bytes/write.<br>
418 (gdb) monitor arm7_9 force_hw_bkpts enable<br>
419 force hardware breakpoints enabled<br>
421 Breakpoint 1 at 0x100134: file src/main.c, line 69.<br>
425 Breakpoint 1, main () at src/main.c:69<br>
430 <td>The breakpoint should be reached, typical output:<br>
432 target state: halted<br>
433 target halted in ARM state due to single step, current mode: Supervisor<br>
434 cpsr: 0x60000013 pc: 0x0010013c<br>
440 target state: halted<br>
441 target halted in ARM state due to single step, current mode: Supervisor<br>
442 cpsr: 0x60000013 pc: 0x00100138<br>
443 target state: halted<br>
444 target halted in ARM state due to single step, current mode: Supervisor<br>
445 cpsr: 0x60000013 pc: 0x0010013c<br>
453 Note: these tests are not designed to test/debug the target, but to test functionalities!
460 <td>Initial state</td>
462 <td>Expected output</td>
463 <td>Actual output</td>
467 <td><a name="RAM001"/>RAM001</td>
470 <td>32 bit Write/read RAM</td>
471 <td>Reset init is working</td>
472 <td>On the telnet interface<br>
473 <code> > mww ram_address 0xdeadbeef 16<br>
477 <td>The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 32bit long containing 0xdeadbeef.<br>
479 > mww 0x0 0xdeadbeef 16<br>
481 0x00000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
482 0x00000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
483 0x00000040: e1a00000 e59fa51c e59f051c e04aa000 00080017 00009388 00009388 00009388<br>
484 0x00000060: 00009388 0002c2c0 0002c2c0 000094f8 000094f4 00009388 00009388 00009388<br>
489 > mww 0x00200000 0xdeadbeef 16<br>
490 > mdw 0x00200000 32<br>
491 0x00200000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
492 0x00200020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
493 0x00200040: e59f10b4 e3a00902 e5810004 e59f00ac e59f10ac e5810000 e3e010ff e59f00a4<br>
494 0x00200060: e5810060 e59f10a0 e3e00000 e5810130 e5810124 e321f0db e59fd090 e321f0d7
500 <td><a name="RAM002"/>RAM002</td>
503 <td>16 bit Write/read RAM</td>
504 <td>Reset init is working</td>
505 <td>On the telnet interface<br>
506 <code> > mwh ram_address 0xbeef 16<br>
510 <td>The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 16bit long containing 0xbeef.<br>
512 > mwh 0x0 0xbeef 16<br>
514 0x00000000: beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef<br>
515 0x00000020: 00e0 0000 021c 0000 0240 0000 026c 0000 0288 0000 0000 0000 0388 0000 0350 0000<br>
520 > mwh 0x00200000 0xbeef 16<br>
521 > mdh 0x00200000 32<br>
522 0x00200000: beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef<br>
523 0x00200020: 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
528 <td><a name="RAM003"/>RAM003</td>
531 <td>8 bit Write/read RAM</td>
532 <td>Reset init is working</td>
533 <td>On the telnet interface<br>
534 <code> > mwb ram_address 0xab 16<br>
538 <td>The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 8bit long containing 0xab.<br>
540 > mwb ram_address 0xab 16<br>
541 > mdb ram_address 32<br>
542 0x00000000: ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
547 > mwb 0x00200000 0xab 16<br>
548 > mdb 0x00200000 32<br>
549 0x00200000: ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
557 <H2>Flash access</H2>
564 <td>Initial state</td>
566 <td>Expected output</td>
567 <td>Actual output</td>
571 <td><a name="FLA001"/>FLA001</td>
575 <td>Reset init is working</td>
576 <td>On the telnet interface:<br>
577 <code> > flash probe 0</code>
579 <td>The command should execute without error. The output should state the name of the flash and the starting address. An example of output:<br>
580 <code>flash 'ecosflash' found at 0x01000000</code>
585 flash 'at91sam7' found at 0x00100000
591 <td><a name="FLA002"/>FLA002</td>
595 <td>Reset init is working, flash is probed</td>
596 <td>On the telnet interface<br>
597 <code> > flash fillw 0x1000000 0xdeadbeef 16
600 <td>The commands should execute without error. The output looks like:<br>
602 wrote 64 bytes to 0x01000000 in 11.610000s (0.091516 kb/s)
604 To verify the contents of the flash:<br>
606 > mdw 0x1000000 32<br>
607 0x01000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
608 0x01000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
609 0x01000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
610 0x01000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
614 > flash fillw 0x100000 0xdeadbeef 16<br>
615 wrote 64 bytes to 0x00100000 in 1.110000s (0.957207 kb/s)<br>
616 > mdw 0x100000 32<br>
617 0x00100000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
618 0x00100020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
619 0x00100040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
620 0x00100060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
625 <td><a name="FLA003"/>FLA003</td>
629 <td>Reset init is working, flash is probed</td>
630 <td>On the telnet interface<br>
631 <code> > flash erase_address 0x1000000 0x2000
634 <td>The commands should execute without error.<br>
636 erased address 0x01000000 length 8192 in 4.970000s
638 To check that the flash has been erased, read at different addresses. The result should always be 0xff.
640 > mdw 0x1000000 32<br>
641 0x01000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
642 0x01000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
643 0x01000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
644 0x01000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
648 > flash erase_address 0x100000 0x2000<br>
649 erased address 0x00100000 length 8192 in 0.510000s<br>
650 > mdw 0x100000 32<br>
651 0x00100000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
652 0x00100020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
653 0x00100040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
654 0x00100060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
660 <td><a name="FLA004"/>FLA004</td>
663 <td>Loading to flash from GDB</td>
664 <td>Reset init is working, flash is probed, connectivity to GDB server is working</td>
665 <td>Start GDB using a ROM elf image, eg: arm-elf-gdb test_rom.elf. <br>
667 (gdb) target remote ip:port<br>
668 (gdb) monitor reset<br>
670 Loading section .text, size 0x194 lma 0x100000<br>
671 Start address 0x100040, load size 404<br>
672 Transfer rate: 179 bytes/sec, 404 bytes/write.
673 (gdb) monitor verify_image path_to_elf_file
676 <td>The output should look like:<br>
678 verified 404 bytes in 5.060000s
680 The failure message is something like:<br>
681 <code>Verify operation failed address 0x00200000. Was 0x00 instead of 0x18</code>
686 Loading section .text, size 0x194 lma 0x100000<br>
687 Start address 0x100040, load size 404<br>
688 Transfer rate: 1540 bits/sec, 404 bytes/write.<br>
689 (gdb) monitor verify_image /tftp/10.0.0.9/c:\workspace/ecosboard/ecosboard/phi/openocd/rep/testing/examples/SAM7S256Test/test_rom.elf<br>
690 verified 404 bytes in 4.860000s