1 /***********************************************************************************
2 * Copyright 2005 Anglia Design
3 * This demo code and associated components are provided as is and has no warranty,
4 * implied or otherwise. You are free to use/modify any of the provided
5 * code at your own risk in your applications with the expressed limitation
6 * of liability (see below)
8 * LIMITATION OF LIABILITY: ANGLIA OR ANGLIA DESIGNS SHALL NOT BE LIABLE FOR ANY
9 * LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA, INTERRUPTION OF BUSINESS, NOR FOR
10 * INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER
11 * THIS AGREEMENT OR OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
13 * Author : Spencer Oliver
14 * Web : www.anglia-designs.com
16 * mifi, 22.01.2008, small changes by the init of the C++ eabi constructors.
17 * Here I have replaced the eabi init by the normal init.
18 * Thanks to Spen for the startup code.
19 ***********************************************************************************/
21 /**** Startup Code (executed after Reset) ****/
23 /* Frequency values kHz */
24 /* set to suit target hardware */
28 /* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */
36 .equ Mode_SYS, 0x1F /* available on ARM Arch 4 and later */
38 .equ I_Bit, 0x80 /* when I bit is set, IRQ is disabled */
39 .equ F_Bit, 0x40 /* when F bit is set, FIQ is disabled */
45 /* --- System memory locations */
47 .equ SCRO_AHB_UMB, 0x5C002034 /* System configuration register 0 (unbuffered) */
49 .equ FMI_BASE_UMB, 0x54000000 /* Flash FMI base address (unbuffered) */
50 .equ BBSR_off_addr, 0x00
51 .equ NBBSR_off_addr, 0x04
52 .equ BBADR_off_addr, 0x0C
53 .equ NBBADR_off_addr, 0x10
54 .equ CR_off_addr, 0x18
60 /* Startup Code must be linked first at Address at which it expects to run. */
69 /* After remap this will be our reset handler */
75 NOP /* Wait for OSC stabilization */
85 /* Enable buffered mode */
88 MRC p15, 0, r0, c1, c0, 0 /* Read CP15 register 1 into r0 */
89 ORR r0, r0, #0x8 /* Enable Write Buffer on AHB */
90 MCR p15, 0, r0, c1, c0, 0 /* Write CP15 register 1 */
93 /* Remap Flash Bank 0 at address 0x0 and Bank 1 at address 0x80000, */
94 /* when the bank 0 is the boot bank, then enable the Bank 1. */
97 LDR r1, =0x4 /* configure 512KB Boot bank 0 */
98 STR r1, [r0, #BBSR_off_addr]
100 LDR r1, =0x2 /* configure 32KB Non Boot bank 1 */
101 STR r1, [r0, #NBBSR_off_addr]
103 LDR r1, =(0x00000000 >> 2) /* Boot Bank Base Address */
104 STR r1, [r0, #BBADR_off_addr]
106 LDR r1, =(0x00080000 >> 2) /* Non Boot Bank Base Address */
107 STR r1, [r0, #NBBADR_off_addr]
109 LDR r1, =0x18 /* Flash Banks 0 1 enabled */
110 STR r1, [r0, #CR_off_addr]
114 LDR r0, =SCRO_AHB_UMB
115 # LDR r1, =0x0196 /* prefetch disabled, default enabled */
116 LDR r1, =0x0187|SRAM96
119 /* Set bits 17-18 (Instruction/Data TCM order) of the */
120 /* Core Configuration Control Register */
123 MCR p15, 0x1, r0, c15, c1, 0
125 /* Setup Stack for each mode */
127 /* Enter Abort Mode and set its Stack Pointer */
129 MSR cpsr_c, #Mode_ABT|I_Bit|F_Bit
130 LDR sp, =__stack_abt_end__
132 /* Enter Undefined Instruction Mode and set its Stack Pointer */
134 MSR cpsr_c, #Mode_UND|I_Bit|F_Bit
135 LDR sp, =__stack_und_end__
137 /* Enter Supervisor Mode and set its Stack Pointer */
139 MSR cpsr_c, #Mode_SVC|I_Bit|F_Bit
140 LDR sp, =__stack_svc_end__
142 /* Enter FIQ Mode and set its Stack Pointer */
144 MSR cpsr_c, #Mode_FIQ|I_Bit|F_Bit
145 LDR sp, =__stack_fiq_end__
147 /* Enter IRQ Mode and set its Stack Pointer */
149 MSR cpsr_c, #Mode_IRQ|I_Bit|F_Bit
150 LDR sp, =__stack_irq_end__
152 /* Enter System/User Mode and set its Stack Pointer */
154 MSR cpsr_c, #Mode_SYS
155 LDR sp, =__stack_end__
157 /* Setup a default Stack Limit (when compiled with "-mapcs-stack-check") */
161 /* Relocate .data section (Copy from ROM to RAM) */
164 LDR r2, =__data_start
172 /* Clear .bss section (Zero init) */
175 LDR r1, =__bss_start__
182 /* Call C++ constructors */
184 LDR r0, =__ctors_start__
185 LDR r1, =__ctors_end__
196 /* Need to set up standard file handles */
197 /* Only used under simulator, normally overide syscall.c */
199 # BL initialise_monitor_handles
201 /* if we use debug version of str9lib this will call the init function */
206 /* Enter the C code, use B instruction so as to never return */
207 /* use BL main if you want to use c++ destructors below */
211 /* Return from main, loop forever. */
216 /* Fosc values, used by libstr9 */
218 _Main_Crystal: .long FOSC