2 * (C) Copyright 2003-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
8 * (C) Copyright 2004-2006
9 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
11 * SPDX-License-Identifier: GPL-2.0+
18 #include <asm/processor.h>
23 #ifdef CONFIG_VIDEO_SM501
27 #if defined(CONFIG_MPC5200_DDR)
28 #include "mt46v16m16-75.h"
30 #include "mt48lc16m16a2-75.h"
33 #ifdef CONFIG_OF_LIBFDT
34 #include <fdt_support.h>
35 #endif /* CONFIG_OF_LIBFDT */
37 DECLARE_GLOBAL_DATA_PTR;
40 void ps2mult_early_init(void);
43 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) && \
46 * EDID block has been generated using Phoenix EDID Designer 1.3.
47 * This tool creates a text file containing:
51 * 0x 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
52 * ------------------------------------------------
53 * 00 | 00 FF FF FF FF FF FF 00 04 21 00 00 00 00 00 00
54 * 10 | 01 00 01 03 00 00 00 00 00 00 00 00 00 00 00 00
55 * 20 | 00 00 00 21 00 00 01 01 01 01 01 01 01 01 01 01
56 * 30 | 01 01 01 01 01 01 64 00 00 00 00 00 00 00 00 00
57 * 40 | 00 00 00 00 00 00 00 00 00 00 00 10 00 00 00 00
58 * 50 | 00 00 00 00 00 00 00 00 00 00 00 00 00 10 00 00
59 * 60 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10
60 * 70 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 17
62 * Then this data has been manually converted to the char
65 static unsigned char edid_buf[128] = {
66 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
67 0x04, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
68 0x01, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00,
69 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
70 0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x01, 0x01,
71 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
72 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x64, 0x00,
73 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
74 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
75 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00,
76 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
77 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
78 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
79 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
80 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
81 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x17,
85 #ifndef CONFIG_SYS_RAMBOOT
86 static void sdram_start (int hi_addr)
88 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
90 /* unlock mode register */
91 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
93 __asm__ volatile ("sync");
95 /* precharge all banks */
96 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
98 __asm__ volatile ("sync");
101 /* set mode register: extended mode */
102 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
103 __asm__ volatile ("sync");
105 /* set mode register: reset DLL */
106 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
107 __asm__ volatile ("sync");
110 /* precharge all banks */
111 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
113 __asm__ volatile ("sync");
116 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
118 __asm__ volatile ("sync");
120 /* set mode register */
121 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
122 __asm__ volatile ("sync");
124 /* normal operation */
125 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
126 __asm__ volatile ("sync");
131 * ATTENTION: Although partially referenced initdram does NOT make real use
132 * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
133 * is something else than 0x00000000.
136 phys_size_t initdram (int board_type)
142 #ifndef CONFIG_SYS_RAMBOOT
145 /* setup SDRAM chip selects */
146 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
147 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
148 __asm__ volatile ("sync");
150 /* setup config registers */
151 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
152 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
153 __asm__ volatile ("sync");
157 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
158 __asm__ volatile ("sync");
161 /* find RAM size using SDRAM CS0 only */
163 test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
165 test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
173 /* memory smaller than 1MB is impossible */
174 if (dramsize < (1 << 20)) {
178 /* set SDRAM CS0 size according to the amount of RAM found */
180 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
181 __builtin_ffs(dramsize >> 20) - 1;
183 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
186 /* let SDRAM CS1 start right after CS0 */
187 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */
189 /* find RAM size using SDRAM CS1 only */
192 test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
195 test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
204 /* memory smaller than 1MB is impossible */
205 if (dramsize2 < (1 << 20)) {
209 /* set SDRAM CS1 size according to the amount of RAM found */
211 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
212 | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
214 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
217 #else /* CONFIG_SYS_RAMBOOT */
219 /* retrieve size of memory connected to SDRAM CS0 */
220 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
221 if (dramsize >= 0x13) {
222 dramsize = (1 << (dramsize - 0x13)) << 20;
227 /* retrieve size of memory connected to SDRAM CS1 */
228 dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
229 if (dramsize2 >= 0x13) {
230 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
234 #endif /* CONFIG_SYS_RAMBOOT */
237 * On MPC5200B we need to set the special configuration delay in the
238 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
239 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
241 * "The SDelay should be written to a value of 0x00000004. It is
242 * required to account for changes caused by normal wafer processing
247 if ((SVR_MJREV(svr) >= 2) &&
248 (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
250 *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
251 __asm__ volatile ("sync");
254 #if defined(CONFIG_TQM5200_B)
255 return dramsize + dramsize2;
258 #endif /* CONFIG_TQM5200_B */
261 int checkboard (void)
263 #if defined(CONFIG_TQM5200S)
264 # define MODULE_NAME "TQM5200S"
266 # define MODULE_NAME "TQM5200"
269 #if defined(CONFIG_STK52XX)
270 # define CARRIER_NAME "STK52xx"
271 #elif defined(CONFIG_CAM5200)
272 # define CARRIER_NAME "CAM5200"
273 #elif defined(CONFIG_FO300)
274 # define CARRIER_NAME "FO300"
275 #elif defined(CONFIG_CHARON)
276 # define CARRIER_NAME "CHARON"
281 puts ( "Board: " MODULE_NAME " (TQ-Components GmbH)\n"
282 " on a " CARRIER_NAME " carrier board\n");
290 void flash_preinit(void)
293 * Now, when we are in RAM, enable flash write
294 * access for detection process.
295 * Note that CS_BOOT cannot be cleared when
296 * executing in flash.
298 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
303 static struct pci_controller hose;
305 extern void pci_mpc5xxx_init(struct pci_controller *);
307 void pci_init_board(void)
309 pci_mpc5xxx_init(&hose);
313 #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
315 #if defined (CONFIG_MINIFAP)
316 #define SM501_POWER_MODE0_GATE 0x00000040UL
317 #define SM501_POWER_MODE1_GATE 0x00000048UL
318 #define POWER_MODE_GATE_GPIO_PWM_I2C 0x00000040UL
319 #define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL
320 #define SM501_GPIO_DATA_HIGH 0x00010004UL
321 #define SM501_GPIO_51 0x00080000UL
322 #endif /* CONFIG MINIFAP */
324 void init_ide_reset (void)
326 debug ("init_ide_reset\n");
328 #if defined (CONFIG_MINIFAP)
329 /* Configure GPIO_51 of the SM501 grafic controller as ATA reset */
331 /* enable GPIO control (in both power modes) */
332 *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |=
333 POWER_MODE_GATE_GPIO_PWM_I2C;
334 *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |=
335 POWER_MODE_GATE_GPIO_PWM_I2C;
336 /* configure GPIO51 as output */
337 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |=
340 /* Configure PSC1_4 as GPIO output for ATA reset */
341 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
342 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
344 /* by default the ATA reset is de-asserted */
345 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
349 void ide_set_reset (int idereset)
351 debug ("ide_reset(%d)\n", idereset);
353 #if defined (CONFIG_MINIFAP)
355 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
358 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
363 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
365 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
373 * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
374 * is left open, no keypress is detected.
376 int post_hotkeys_pressed(void)
378 #ifdef CONFIG_STK52XX
379 struct mpc5xxx_gpio *gpio;
381 gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO;
384 * Configure PSC6_0 through PSC6_3 as GPIO.
386 gpio->port_config &= ~(0x00700000);
388 /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
389 gpio->simple_gpioe |= 0x20000000;
391 /* Configure GPIO_IRDA_1 as input */
392 gpio->simple_ddr &= ~(0x20000000);
394 return ((gpio->simple_ival & 0x20000000) ? 0 : 1);
401 #ifdef CONFIG_BOARD_EARLY_INIT_R
402 int board_early_init_r (void)
405 extern int usb_cpu_init(void);
407 #ifdef CONFIG_PS2MULT
408 ps2mult_early_init();
409 #endif /* CONFIG_PS2MULT */
411 #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
412 /* Low level USB init, required for proper kernel operation */
421 int silent_boot (void)
423 vu_long timer3_status;
425 /* Configure GPT3 as GPIO input */
426 *(vu_long *)MPC5XXX_GPT3_ENABLE = 0x00000004;
428 /* Read in TIMER_3 pin status */
429 timer3_status = *(vu_long *)MPC5XXX_GPT3_STATUS;
431 #ifdef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED
432 /* Force silent console mode if S1 switch
433 * is in closed position (TIMER_3 pin status is LOW). */
434 if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 0)
437 /* Force silent console mode if S1 switch
438 * is in open position (TIMER_3 pin status is HIGH). */
439 if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 1)
446 int board_early_init_f (void)
449 gd->flags |= GD_FLG_SILENT;
453 #endif /* CONFIG_FO300 */
455 #if defined(CONFIG_CHARON)
459 /* The TFP410 registers */
460 #define TFP410_REG_VEN_ID_L 0x00
461 #define TFP410_REG_VEN_ID_H 0x01
462 #define TFP410_REG_DEV_ID_L 0x02
463 #define TFP410_REG_DEV_ID_H 0x03
464 #define TFP410_REG_REV_ID 0x04
466 #define TFP410_REG_CTL_1_MODE 0x08
467 #define TFP410_REG_CTL_2_MODE 0x09
468 #define TFP410_REG_CTL_3_MODE 0x0A
470 #define TFP410_REG_CFG 0x0B
472 #define TFP410_REG_DE_DLY 0x32
473 #define TFP410_REG_DE_CTL 0x33
474 #define TFP410_REG_DE_TOP 0x34
475 #define TFP410_REG_DE_CNT_L 0x36
476 #define TFP410_REG_DE_CNT_H 0x37
477 #define TFP410_REG_DE_LIN_L 0x38
478 #define TFP410_REG_DE_LIN_H 0x39
480 #define TFP410_REG_H_RES_L 0x3A
481 #define TFP410_REG_H_RES_H 0x3B
482 #define TFP410_REG_V_RES_L 0x3C
483 #define TFP410_REG_V_RES_H 0x3D
485 static int tfp410_read_reg(int reg, uchar *buf)
487 if (i2c_read(CONFIG_SYS_TFP410_ADDR, reg, 1, buf, 1) != 0) {
488 puts ("Error reading the chip.\n");
494 static int tfp410_write_reg(int reg, uchar buf)
496 if (i2c_write(CONFIG_SYS_TFP410_ADDR, reg, 1, &buf, 1) != 0) {
497 puts ("Error writing the chip.\n");
503 typedef struct _tfp410_config {
508 static TFP410_CONFIG tfp410_configtbl[] = {
509 {TFP410_REG_CTL_1_MODE, 0x37},
510 {TFP410_REG_CTL_2_MODE, 0x20},
511 {TFP410_REG_CTL_3_MODE, 0x80},
512 {TFP410_REG_DE_DLY, 0x90},
513 {TFP410_REG_DE_CTL, 0x00},
514 {TFP410_REG_DE_TOP, 0x23},
515 {TFP410_REG_DE_CNT_H, 0x02},
516 {TFP410_REG_DE_CNT_L, 0x80},
517 {TFP410_REG_DE_LIN_H, 0x01},
518 {TFP410_REG_DE_LIN_L, 0xe0},
522 static int charon_last_stage_init(void)
524 volatile struct mpc5xxx_lpb *lpb =
525 (struct mpc5xxx_lpb *) MPC5XXX_LPB;
526 int oldbus = i2c_get_bus_num();
530 i2c_set_bus_num(CONFIG_SYS_TFP410_BUS);
533 if (tfp410_read_reg(TFP410_REG_DEV_ID_H, &buf) != 0)
537 if (tfp410_read_reg(TFP410_REG_DEV_ID_L, &buf) != 0)
541 /* OK, now init the chip */
542 while (tfp410_configtbl[i].reg != -1) {
545 ret = tfp410_write_reg(tfp410_configtbl[i].reg,
546 tfp410_configtbl[i].val);
551 printf("TFP410 initialized.\n");
552 i2c_set_bus_num(oldbus);
554 /* set deadcycle for cs3 to 0 */
555 setbits_be32(&lpb->cs_deadcycle, 0xffffcfff);
560 int last_stage_init (void)
563 * auto scan for really existing devices and re-set chip select
570 * Check for SRAM and SRAM size
573 /* save original SRAM content */
574 save = *(volatile u16 *)CONFIG_SYS_CS2_START;
577 /* write test pattern to SRAM */
578 *(volatile u16 *)CONFIG_SYS_CS2_START = 0xA5A5;
579 __asm__ volatile ("sync");
581 * Put a different pattern on the data lines: otherwise they may float
582 * long enough to read back what we wrote.
584 tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
586 puts ("!! possible error in SRAM detection\n");
588 if (*(volatile u16 *)CONFIG_SYS_CS2_START != 0xA5A5) {
589 /* no SRAM at all, disable cs */
590 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18);
591 *(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF;
592 *(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF;
594 __asm__ volatile ("sync");
595 } else if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0xA5A5) {
596 /* make sure that we access a mirrored address */
597 *(volatile u16 *)CONFIG_SYS_CS2_START = 0x1111;
598 __asm__ volatile ("sync");
599 if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0x1111) {
600 /* SRAM size = 512 kByte */
601 *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CONFIG_SYS_CS2_START,
603 __asm__ volatile ("sync");
604 puts ("SRAM: 512 kB\n");
607 puts ("!! possible error in SRAM detection\n");
609 puts ("SRAM: 1 MB\n");
611 /* restore origianl SRAM content */
613 *(volatile u16 *)CONFIG_SYS_CS2_START = save;
614 __asm__ volatile ("sync");
617 #ifndef CONFIG_TQM5200S /* The TQM5200S has no SM501 grafic controller */
619 * Check for Grafic Controller
622 /* save origianl FB content */
623 save = *(volatile u16 *)CONFIG_SYS_CS1_START;
626 /* write test pattern to FB memory */
627 *(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5;
628 __asm__ volatile ("sync");
630 * Put a different pattern on the data lines: otherwise they may float
631 * long enough to read back what we wrote.
633 tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
635 puts ("!! possible error in grafic controller detection\n");
637 if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) {
638 /* no grafic controller at all, disable cs */
639 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17);
640 *(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF;
641 *(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF;
643 __asm__ volatile ("sync");
645 puts ("VGA: SMI501 (Voyager) with 8 MB\n");
647 /* restore origianl FB content */
649 *(volatile u16 *)CONFIG_SYS_CS1_START = save;
650 __asm__ volatile ("sync");
655 setenv("bootdelay", "0");
659 #endif /* !CONFIG_TQM5200S */
661 #if defined(CONFIG_CHARON)
662 charon_last_stage_init();
667 #ifdef CONFIG_VIDEO_SM501
670 #define DISPLAY_WIDTH 800
672 #define DISPLAY_WIDTH 640
674 #define DISPLAY_HEIGHT 480
676 #ifdef CONFIG_VIDEO_SM501_8BPP
677 #error CONFIG_VIDEO_SM501_8BPP not supported.
678 #endif /* CONFIG_VIDEO_SM501_8BPP */
680 #ifdef CONFIG_VIDEO_SM501_16BPP
681 #error CONFIG_VIDEO_SM501_16BPP not supported.
682 #endif /* CONFIG_VIDEO_SM501_16BPP */
683 #ifdef CONFIG_VIDEO_SM501_32BPP
684 static const SMI_REGS init_regs [] =
688 {0x00048, 0x00021807},
689 {0x0004C, 0x10090a01},
691 {0x00040, 0x00021807},
692 {0x00044, 0x10090a01},
694 {0x80200, 0x00010000},
696 {0x80208, 0x0A000A00},
697 {0x8020C, 0x02fa027f},
698 {0x80210, 0x004a028b},
699 {0x80214, 0x020c01df},
700 {0x80218, 0x000201e9},
701 {0x80200, 0x00013306},
702 #else /* panel + CRT */
705 {0x00048, 0x00021807},
706 {0x0004C, 0x301a0a01},
708 {0x00040, 0x00021807},
709 {0x00044, 0x091a0a01},
711 {0x80000, 0x0f013106},
712 {0x80004, 0xc428bb17},
713 {0x8000C, 0x00000000},
714 {0x80010, 0x0C800C80},
715 {0x80014, 0x03200000},
716 {0x80018, 0x01e00000},
717 {0x8001C, 0x00000000},
718 {0x80020, 0x01e00320},
719 {0x80024, 0x042a031f},
720 {0x80028, 0x0086034a},
721 {0x8002C, 0x020c01df},
722 {0x80030, 0x000201ea},
723 {0x80200, 0x00010000},
726 {0x00048, 0x00021807},
727 {0x0004C, 0x091a0a01},
729 {0x00040, 0x00021807},
730 {0x00044, 0x091a0a01},
732 {0x80000, 0x0f013106},
733 {0x80004, 0xc428bb17},
734 {0x8000C, 0x00000000},
735 {0x80010, 0x0a000a00},
736 {0x80014, 0x02800000},
737 {0x80018, 0x01e00000},
738 {0x8001C, 0x00000000},
739 {0x80020, 0x01e00280},
740 {0x80024, 0x02fa027f},
741 {0x80028, 0x004a028b},
742 {0x8002C, 0x020c01df},
743 {0x80030, 0x000201e9},
744 {0x80200, 0x00010000},
745 #endif /* #ifdef CONFIG_FO300 */
749 #endif /* CONFIG_VIDEO_SM501_32BPP */
751 #ifdef CONFIG_CONSOLE_EXTRA_INFO
753 * Return text to be printed besides the logo.
755 void video_get_info_str (int line_number, char *info)
757 if (line_number == 1) {
758 strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
759 #if defined (CONFIG_CHARON) || defined (CONFIG_FO300) || \
760 defined(CONFIG_STK52XX)
761 } else if (line_number == 2) {
762 #if defined (CONFIG_CHARON)
763 strcpy (info, " on a CHARON carrier board");
765 #if defined (CONFIG_STK52XX)
766 strcpy (info, " on a STK52xx carrier board");
768 #if defined (CONFIG_FO300)
769 strcpy (info, " on a FO300 carrier board");
780 * Returns SM501 register base address. First thing called in the
781 * driver. Checks if SM501 is physically present.
783 unsigned int board_video_init (void)
789 * Check for Grafic Controller
792 /* save origianl FB content */
793 save = *(volatile u16 *)CONFIG_SYS_CS1_START;
796 /* write test pattern to FB memory */
797 *(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5;
798 __asm__ volatile ("sync");
800 * Put a different pattern on the data lines: otherwise they may float
801 * long enough to read back what we wrote.
803 tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
805 puts ("!! possible error in grafic controller detection\n");
807 if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) {
808 /* no grafic controller found */
812 ret = SM501_MMIO_BASE;
816 *(volatile u16 *)CONFIG_SYS_CS1_START = save;
817 __asm__ volatile ("sync");
823 * Returns SM501 framebuffer address
825 unsigned int board_video_get_fb (void)
827 return SM501_FB_BASE;
831 * Called after initializing the SM501 and before clearing the screen.
833 void board_validate_screen (unsigned int base)
838 * Return a pointer to the initialization sequence.
840 const SMI_REGS *board_get_regs (void)
845 int board_get_width (void)
847 return DISPLAY_WIDTH;
850 int board_get_height (void)
852 return DISPLAY_HEIGHT;
855 #endif /* CONFIG_VIDEO_SM501 */
857 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
858 int ft_board_setup(void *blob, bd_t *bd)
860 ft_cpu_setup(blob, bd);
861 #if defined(CONFIG_VIDEO)
862 fdt_add_edid(blob, "smi,sm501", edid_buf);
867 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
869 #if defined(CONFIG_RESET_PHY_R)
874 /* init Micrel KSZ8993 PHY */
875 miiphy_write("FEC", CONFIG_PHY_ADDR, 0x01, 0x09);
879 int board_eth_init(bd_t *bis)
881 cpu_eth_init(bis); /* Built in FEC comes first */
882 return pci_eth_init(bis);