- __asm volatile\r
- (\r
- " .syntax unified \n"\r
- " \n"\r
- " mrs r0, psp \n" /* Read PSP in r0. */\r
- #if( configENABLE_FPU == 1 )\r
- " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
- " it eq \n"\r
- " vstmdbeq r0!, {s16-s31} \n" /* Store the FPU registers which are not saved automatically. */\r
- #endif /* configENABLE_FPU */\r
- #if( configENABLE_MPU == 1 )\r
- " mrs r1, psplim \n" /* r1 = PSPLIM. */\r
- " mrs r2, control \n" /* r2 = CONTROL. */\r
- " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */\r
- " stmdb r0!, {r1-r11} \n" /* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */\r
- #else /* configENABLE_MPU */\r
- " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
- " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */\r
- " stmdb r0!, {r2-r11} \n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */\r
- #endif /* configENABLE_MPU */\r
- " \n"\r
- " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
- " ldr r1, [r2] \n" /* Read pxCurrentTCB. */\r
- " str r0, [r1] \n" /* Save the new top of stack in TCB. */\r
- " \n"\r
- " cpsid i \n"\r
- " bl vTaskSwitchContext \n"\r
- " cpsie i \n"\r
- " \n"\r
- " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
- " ldr r1, [r2] \n" /* Read pxCurrentTCB. */\r
- " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */\r
- " \n"\r
- #if( configENABLE_MPU == 1 )\r
- " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
- " ldr r3, [r1] \n" /* r3 = *r1 i.e. r3 = MAIR0. */\r
- " ldr r2, xMAIR0Const \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
- " str r3, [r2] \n" /* Program MAIR0. */\r
- " ldr r2, xRNRConst \n" /* r2 = 0xe000ed98 [Location of RNR]. */\r
- " movs r3, #4 \n" /* r3 = 4. */\r
- " str r3, [r2] \n" /* Program RNR = 4. */\r
- " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
- " ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */\r
- " ldmia r1!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
- " stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
- #endif /* configENABLE_MPU */\r
- " \n"\r
- #if( configENABLE_MPU == 1 )\r
- " ldmia r0!, {r1-r11} \n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */\r
- #else /* configENABLE_MPU */\r
- " ldmia r0!, {r2-r11} \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */\r
- #endif /* configENABLE_MPU */\r
- " \n"\r
- #if( configENABLE_FPU == 1 )\r
- " tst r3, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
- " it eq \n"\r
- " vldmiaeq r0!, {s16-s31} \n" /* Restore the FPU registers which are not restored automatically. */\r
- #endif /* configENABLE_FPU */\r
- " \n"\r
- #if( configENABLE_MPU == 1 )\r
- " msr psplim, r1 \n" /* Restore the PSPLIM register value for the task. */\r
- " msr control, r2 \n" /* Restore the CONTROL register value for the task. */\r
- #else /* configENABLE_MPU */\r
- " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */\r
- #endif /* configENABLE_MPU */\r
- " msr psp, r0 \n" /* Remember the new top of stack for the task. */\r
- " bx r3 \n"\r
- " \n"\r
- " .align 4 \n"\r
- "pxCurrentTCBConst: .word pxCurrentTCB \n"\r
- "xMAIR0Const: .word 0xe000edc0 \n"\r
- "xRNRConst: .word 0xe000ed98 \n"\r
- "xRBARConst: .word 0xe000ed9c \n"\r
- );\r
+ __asm volatile\r
+ (\r
+ " .syntax unified \n"\r
+ " \n"\r
+ " mrs r0, psp \n" /* Read PSP in r0. */\r
+ #if( configENABLE_FPU == 1 )\r
+ " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
+ " it eq \n"\r
+ " vstmdbeq r0!, {s16-s31} \n" /* Store the FPU registers which are not saved automatically. */\r
+ #endif /* configENABLE_FPU */\r
+ #if( configENABLE_MPU == 1 )\r
+ " mrs r1, psplim \n" /* r1 = PSPLIM. */\r
+ " mrs r2, control \n" /* r2 = CONTROL. */\r
+ " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */\r
+ " stmdb r0!, {r1-r11} \n" /* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */\r
+ #else /* configENABLE_MPU */\r
+ " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
+ " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */\r
+ " stmdb r0!, {r2-r11} \n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */\r
+ " str r0, [r1] \n" /* Save the new top of stack in TCB. */\r
+ " \n"\r
+ " cpsid i \n"\r
+ " bl vTaskSwitchContext \n"\r
+ " cpsie i \n"\r
+ " \n"\r
+ " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */\r
+ " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
+ " ldr r3, [r1] \n" /* r3 = *r1 i.e. r3 = MAIR0. */\r
+ " ldr r2, xMAIR0Const \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ " str r3, [r2] \n" /* Program MAIR0. */\r
+ " ldr r2, xRNRConst \n" /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ " movs r3, #4 \n" /* r3 = 4. */\r
+ " str r3, [r2] \n" /* Program RNR = 4. */\r
+ " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
+ " ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */\r
+ " ldmia r1!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
+ " stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " ldmia r0!, {r1-r11} \n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */\r
+ #else /* configENABLE_MPU */\r
+ " ldmia r0!, {r2-r11} \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ #if( configENABLE_FPU == 1 )\r
+ " tst r3, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
+ " it eq \n"\r
+ " vldmiaeq r0!, {s16-s31} \n" /* Restore the FPU registers which are not restored automatically. */\r
+ #endif /* configENABLE_FPU */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " msr psplim, r1 \n" /* Restore the PSPLIM register value for the task. */\r
+ " msr control, r2 \n" /* Restore the CONTROL register value for the task. */\r
+ #else /* configENABLE_MPU */\r
+ " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */\r
+ #endif /* configENABLE_MPU */\r
+ " msr psp, r0 \n" /* Remember the new top of stack for the task. */\r
+ " bx r3 \n"\r
+ " \n"\r
+ " .align 4 \n"\r
+ "pxCurrentTCBConst: .word pxCurrentTCB \n"\r
+ "xMAIR0Const: .word 0xe000edc0 \n"\r
+ "xRNRConst: .word 0xe000ed98 \n"\r
+ "xRBARConst: .word 0xe000ed9c \n"\r
+ );\r