*/\r
\r
/******************************************************************************\r
- See http://www.freertos.org/a00110.html for an explanation of the\r
- definitions contained in this file.\r
+ See http://www.freertos.org/a00110.html for an explanation of the\r
+ definitions contained in this file.\r
******************************************************************************/\r
\r
#ifndef FREERTOS_CONFIG_H\r
extern uint32_t SystemCoreClock;\r
\r
/* Cortex M33 port configuration. */\r
-#define configENABLE_MPU 1\r
-#define configENABLE_FPU 1\r
-#define configENABLE_TRUSTZONE 1\r
+#define configENABLE_MPU 1\r
+#define configENABLE_FPU 1\r
+#define configENABLE_TRUSTZONE 1\r
\r
/* Constants related to the behaviour or the scheduler. */\r
-#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0\r
-#define configUSE_PREEMPTION 1\r
-#define configUSE_TIME_SLICING 1\r
-#define configMAX_PRIORITIES ( 5 )\r
-#define configIDLE_SHOULD_YIELD 1\r
-#define configUSE_16_BIT_TICKS 0 /* Only for 8 and 16-bit hardware. */\r
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_TIME_SLICING 1\r
+#define configMAX_PRIORITIES ( 5 )\r
+#define configIDLE_SHOULD_YIELD 1\r
+#define configUSE_16_BIT_TICKS 0 /* Only for 8 and 16-bit hardware. */\r
\r
/* Constants that describe the hardware and memory usage. */\r
-#define configCPU_CLOCK_HZ SystemCoreClock\r
-#define configMINIMAL_STACK_SIZE ( ( uint16_t ) 128 )\r
-#define configMINIMAL_SECURE_STACK_SIZE ( 1024 )\r
-#define configMAX_TASK_NAME_LEN ( 12 )\r
-#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 50 * 1024 ) )\r
+#define configCPU_CLOCK_HZ SystemCoreClock\r
+#define configMINIMAL_STACK_SIZE ( ( uint16_t ) 128 )\r
+#define configMINIMAL_SECURE_STACK_SIZE ( 1024 )\r
+#define configMAX_TASK_NAME_LEN ( 12 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 50 * 1024 ) )\r
\r
/* Constants that build features in or out. */\r
-#define configUSE_MUTEXES 1\r
-#define configUSE_TICKLESS_IDLE 1\r
-#define configUSE_APPLICATION_TASK_TAG 0\r
-#define configUSE_NEWLIB_REENTRANT 0\r
-#define configUSE_CO_ROUTINES 0\r
-#define configUSE_COUNTING_SEMAPHORES 1\r
-#define configUSE_RECURSIVE_MUTEXES 1\r
-#define configUSE_QUEUE_SETS 0\r
-#define configUSE_TASK_NOTIFICATIONS 1\r
-#define configUSE_TRACE_FACILITY 1\r
+#define configUSE_MUTEXES 1\r
+#define configUSE_TICKLESS_IDLE 1\r
+#define configUSE_APPLICATION_TASK_TAG 0\r
+#define configUSE_NEWLIB_REENTRANT 0\r
+#define configUSE_CO_ROUTINES 0\r
+#define configUSE_COUNTING_SEMAPHORES 1\r
+#define configUSE_RECURSIVE_MUTEXES 1\r
+#define configUSE_QUEUE_SETS 0\r
+#define configUSE_TASK_NOTIFICATIONS 1\r
+#define configUSE_TRACE_FACILITY 1\r
\r
/* Constants that define which hook (callback) functions should be used. */\r
-#define configUSE_IDLE_HOOK 0\r
-#define configUSE_TICK_HOOK 0\r
-#define configUSE_MALLOC_FAILED_HOOK 0\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configUSE_MALLOC_FAILED_HOOK 0\r
\r
/* Constants provided for debugging and optimisation assistance. */\r
-#define configCHECK_FOR_STACK_OVERFLOW 2\r
-#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }\r
-#define configQUEUE_REGISTRY_SIZE 0\r
+#define configCHECK_FOR_STACK_OVERFLOW 2\r
+#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }\r
+#define configQUEUE_REGISTRY_SIZE 0\r
\r
/* Software timer definitions. */\r
-#define configUSE_TIMERS 1\r
-#define configTIMER_TASK_PRIORITY ( 3 )\r
-#define configTIMER_QUEUE_LENGTH 5\r
-#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE )\r
+#define configUSE_TIMERS 1\r
+#define configTIMER_TASK_PRIORITY ( 3 )\r
+#define configTIMER_QUEUE_LENGTH 5\r
+#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE )\r
\r
/* Set the following definitions to 1 to include the API function, or zero\r
* to exclude the API function. NOTE: Setting an INCLUDE_ parameter to 0 is\r
* only necessary if the linker does not automatically remove functions that are\r
* not referenced anyway. */\r
-#define INCLUDE_vTaskPrioritySet 1\r
-#define INCLUDE_uxTaskPriorityGet 1\r
-#define INCLUDE_vTaskDelete 1\r
-#define INCLUDE_vTaskCleanUpResources 0\r
-#define INCLUDE_vTaskSuspend 1\r
-#define INCLUDE_vTaskDelayUntil 1\r
-#define INCLUDE_vTaskDelay 1\r
-#define INCLUDE_uxTaskGetStackHighWaterMark 0\r
-#define INCLUDE_xTaskGetIdleTaskHandle 0\r
-#define INCLUDE_eTaskGetState 1\r
-#define INCLUDE_xTaskResumeFromISR 0\r
-#define INCLUDE_xTaskGetCurrentTaskHandle 1\r
-#define INCLUDE_xTaskGetSchedulerState 0\r
-#define INCLUDE_xSemaphoreGetMutexHolder 0\r
-#define INCLUDE_xTimerPendFunctionCall 1\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+#define INCLUDE_uxTaskGetStackHighWaterMark 0\r
+#define INCLUDE_xTaskGetIdleTaskHandle 0\r
+#define INCLUDE_eTaskGetState 1\r
+#define INCLUDE_xTaskResumeFromISR 0\r
+#define INCLUDE_xTaskGetCurrentTaskHandle 1\r
+#define INCLUDE_xTaskGetSchedulerState 0\r
+#define INCLUDE_xSemaphoreGetMutexHolder 0\r
+#define INCLUDE_xTimerPendFunctionCall 1\r
\r
/* This demo makes use of one or more example stats formatting functions. These\r
* format the raw data provided by the uxTaskGetSystemState() function in to\r
* human readable ASCII form. See the notes in the implementation of vTaskList()\r
* within FreeRTOS/Source/tasks.c for limitations. */\r
-#define configUSE_STATS_FORMATTING_FUNCTIONS 1\r
+#define configUSE_STATS_FORMATTING_FUNCTIONS 1\r
\r
/* Dimensions a buffer that can be used by the FreeRTOS+CLI command interpreter.\r
* See the FreeRTOS+CLI documentation for more information:\r
* http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_CLI/ */\r
-#define configCOMMAND_INT_MAX_OUTPUT_SIZE 2048\r
+#define configCOMMAND_INT_MAX_OUTPUT_SIZE 2048\r
\r
/* Interrupt priority configuration follows...................... */\r
\r
/* Use the system definition, if there is one. */\r
#ifdef __NVIC_PRIO_BITS\r
- #define configPRIO_BITS __NVIC_PRIO_BITS\r
+ #define configPRIO_BITS __NVIC_PRIO_BITS\r
#else\r
- #define configPRIO_BITS 3 /* 8 priority levels. */\r
+ #define configPRIO_BITS 3 /* 8 priority levels. */\r
#endif\r
\r
/* The lowest interrupt priority that can be used in a call to a "set priority"\r
* function. */\r
-#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x07\r
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x07\r
\r
/* The highest interrupt priority that can be used by any interrupt service\r
* routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT\r
* CALL INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A\r
* HIGHER PRIORITY THAN THIS! (higher priorities are lower numeric values). */\r
-#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5\r
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5\r
\r
/* Interrupt priorities used by the kernel port layer itself. These are generic\r
* to all Cortex-M ports, and do not rely on any particular library functions. */\r
-#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << ( 8 - configPRIO_BITS ) )\r
+#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << ( 8 - configPRIO_BITS ) )\r
\r
/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!\r
* See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */\r
-#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << ( 8 - configPRIO_BITS ) )\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << ( 8 - configPRIO_BITS ) )\r
\r
/* The #ifdef guards against the file being included from IAR assembly files. */\r
#ifndef __IASMARM__\r
\r
- /* Constants related to the generation of run time stats. */\r
- #define configGENERATE_RUN_TIME_STATS 0\r
- #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()\r
- #define portGET_RUN_TIME_COUNTER_VALUE() 0\r
- #define configTICK_RATE_HZ ( ( TickType_t ) 100 )\r
+ /* Constants related to the generation of run time stats. */\r
+ #define configGENERATE_RUN_TIME_STATS 0\r
+ #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()\r
+ #define portGET_RUN_TIME_COUNTER_VALUE() 0\r
+ #define configTICK_RATE_HZ ( ( TickType_t ) 100 )\r
\r
#endif /* __IASMARM__ */\r
\r
/* Enable static allocation. */\r
-#define configSUPPORT_STATIC_ALLOCATION 1\r
+#define configSUPPORT_STATIC_ALLOCATION 1\r
\r
#endif /* FREERTOS_CONFIG_H */\r
/* Externs needed by the MPU setup code. These must match the memory map as\r
* specified in Scatter-Loading description file (FreeRTOSDemo_ns.sct). */\r
/* Privileged flash. */\r
-const uint32_t * __privileged_functions_start__ = ( uint32_t * ) ( 0x00200000 );\r
-const uint32_t * __privileged_functions_end__ = ( uint32_t * ) ( 0x00208000 - 0x1 ); /* Last address in privileged Flash region. */\r
+const uint32_t * __privileged_functions_start__ = ( uint32_t * ) ( 0x00200000 );\r
+const uint32_t * __privileged_functions_end__ = ( uint32_t * ) ( 0x00208000 - 0x1 ); /* Last address in privileged Flash region. */\r
\r
/* Flash containing system calls. */\r
-const uint32_t * __syscalls_flash_start__ = ( uint32_t * ) ( 0x00208000 );\r
-const uint32_t * __syscalls_flash_end__ = ( uint32_t * ) ( 0x00209000 - 0x1 ); /* Last address in Flash region containing system calls. */\r
+const uint32_t * __syscalls_flash_start__ = ( uint32_t * ) ( 0x00208000 );\r
+const uint32_t * __syscalls_flash_end__ = ( uint32_t * ) ( 0x00209000 - 0x1 ); /* Last address in Flash region containing system calls. */\r
\r
/* Unprivileged flash. Note that the section containing\r
* system calls is unprivilged so that unprivleged tasks\r
* can make system calls. */\r
-const uint32_t * __unprivileged_flash_start__ = ( uint32_t * ) ( 0x00209000 );\r
-const uint32_t * __unprivileged_flash_end__ = ( uint32_t * ) ( 0x00400000 - 0x1 ); /* Last address in un-privileged Flash region. */\r
+const uint32_t * __unprivileged_flash_start__ = ( uint32_t * ) ( 0x00209000 );\r
+const uint32_t * __unprivileged_flash_end__ = ( uint32_t * ) ( 0x00400000 - 0x1 ); /* Last address in un-privileged Flash region. */\r
\r
/* 512 bytes (0x200) of RAM starting at 0x30008000 is\r
* priviledged access only. This contains kernel data. */\r
-const uint32_t * __privileged_sram_start__ = ( uint32_t * ) ( 0x20200000 );\r
-const uint32_t * __privileged_sram_end__ = ( uint32_t * ) ( 0x20201000 - 0x1 ); /* Last address in privileged RAM. */\r
+const uint32_t * __privileged_sram_start__ = ( uint32_t * ) ( 0x20200000 );\r
+const uint32_t * __privileged_sram_end__ = ( uint32_t * ) ( 0x20201000 - 0x1 ); /* Last address in privileged RAM. */\r
;\r
/* Unprivileged RAM. */\r
-const uint32_t * __unprivileged_sram_start__ = ( uint32_t * ) ( 0x20201000 );\r
-const uint32_t * __unprivileged_sram_end__ = ( uint32_t * ) ( 0x20220000 - 0x1 ); /* Last address in un-privileged RAM. */\r
+const uint32_t * __unprivileged_sram_start__ = ( uint32_t * ) ( 0x20201000 );\r
+const uint32_t * __unprivileged_sram_end__ = ( uint32_t * ) ( 0x20220000 - 0x1 ); /* Last address in un-privileged RAM. */\r
/*-----------------------------------------------------------*/\r
\r
/**\r
\r
static void prvCreateTasks( void )\r
{\r
- /* Create tasks for the MPU Demo. */\r
- vStartMPUDemo();\r
+ /* Create tasks for the MPU Demo. */\r
+ vStartMPUDemo();\r
\r
- /* Create tasks for the TZ Demo. */\r
- vStartTZDemo();\r
+ /* Create tasks for the TZ Demo. */\r
+ vStartTZDemo();\r
\r
}\r
/*-----------------------------------------------------------*/\r
/* Stack overflow hook. */\r
void vApplicationStackOverflowHook( TaskHandle_t xTask, signed char *pcTaskName )\r
{\r
- /* Force an assert. */\r
- configASSERT( pcTaskName == 0 );\r
+ /* Force an assert. */\r
+ configASSERT( pcTaskName == 0 );\r
}\r
/*-----------------------------------------------------------*/\r
\r
/* Non-Secure main. */\r
int main( void )\r
{\r
- /* Create tasks. */\r
- prvCreateTasks();\r
+ /* Create tasks. */\r
+ prvCreateTasks();\r
\r
- /* Start scheduler. */\r
- vTaskStartScheduler();\r
+ /* Start scheduler. */\r
+ vTaskStartScheduler();\r
\r
- /* Should not reach here as the schedular is already started. */\r
- for( ; ; )\r
- {\r
- }\r
+ /* Should not reach here as the schedular is already started. */\r
+ for( ; ; )\r
+ {\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
\r
/* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide an\r
* implementation of vApplicationGetIdleTaskMemory() to provide the memory that\r
* is used by the Idle task. */\r
-void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,\r
- StackType_t ** ppxIdleTaskStackBuffer,\r
- uint32_t * pulIdleTaskStackSize )\r
+void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,\r
+ StackType_t ** ppxIdleTaskStackBuffer,\r
+ uint32_t * pulIdleTaskStackSize )\r
{\r
- /* If the buffers to be provided to the Idle task are declared inside this\r
- * function then they must be declared static - otherwise they will be\r
- * allocated on the stack and so not exists after this function exits. */\r
- static StaticTask_t xIdleTaskTCB;\r
- static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__((aligned(32)));\r
-\r
- /* Pass out a pointer to the StaticTask_t structure in which the Idle\r
- * task's state will be stored. */\r
- *ppxIdleTaskTCBBuffer = &xIdleTaskTCB;\r
-\r
- /* Pass out the array that will be used as the Idle task's stack. */\r
- *ppxIdleTaskStackBuffer = uxIdleTaskStack;\r
-\r
- /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer.\r
- * Note that, as the array is necessarily of type StackType_t,\r
- * configMINIMAL_STACK_SIZE is specified in words, not bytes. */\r
- *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;\r
+ /* If the buffers to be provided to the Idle task are declared inside this\r
+ * function then they must be declared static - otherwise they will be\r
+ * allocated on the stack and so not exists after this function exits. */\r
+ static StaticTask_t xIdleTaskTCB;\r
+ static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__((aligned(32)));\r
+\r
+ /* Pass out a pointer to the StaticTask_t structure in which the Idle\r
+ * task's state will be stored. */\r
+ *ppxIdleTaskTCBBuffer = &xIdleTaskTCB;\r
+\r
+ /* Pass out the array that will be used as the Idle task's stack. */\r
+ *ppxIdleTaskStackBuffer = uxIdleTaskStack;\r
+\r
+ /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer.\r
+ * Note that, as the array is necessarily of type StackType_t,\r
+ * configMINIMAL_STACK_SIZE is specified in words, not bytes. */\r
+ *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;\r
}\r
/*-----------------------------------------------------------*/\r
\r
* application must provide an implementation of vApplicationGetTimerTaskMemory()\r
* to provide the memory that is used by the Timer service task. */\r
void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer,\r
- StackType_t ** ppxTimerTaskStackBuffer,\r
- uint32_t * pulTimerTaskStackSize )\r
+ StackType_t ** ppxTimerTaskStackBuffer,\r
+ uint32_t * pulTimerTaskStackSize )\r
{\r
- /* If the buffers to be provided to the Timer task are declared inside this\r
- * function then they must be declared static - otherwise they will be\r
- * allocated on the stack and so not exists after this function exits. */\r
- static StaticTask_t xTimerTaskTCB;\r
- static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ] __attribute__((aligned(32)));\r
-\r
- /* Pass out a pointer to the StaticTask_t structure in which the Timer\r
- * task's state will be stored. */\r
- *ppxTimerTaskTCBBuffer = &xTimerTaskTCB;\r
-\r
- /* Pass out the array that will be used as the Timer task's stack. */\r
- *ppxTimerTaskStackBuffer = uxTimerTaskStack;\r
-\r
- /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer.\r
- * Note that, as the array is necessarily of type StackType_t,\r
- * configTIMER_TASK_STACK_DEPTH is specified in words, not bytes. */\r
- *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;\r
+ /* If the buffers to be provided to the Timer task are declared inside this\r
+ * function then they must be declared static - otherwise they will be\r
+ * allocated on the stack and so not exists after this function exits. */\r
+ static StaticTask_t xTimerTaskTCB;\r
+ static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ] __attribute__((aligned(32)));\r
+\r
+ /* Pass out a pointer to the StaticTask_t structure in which the Timer\r
+ * task's state will be stored. */\r
+ *ppxTimerTaskTCBBuffer = &xTimerTaskTCB;\r
+\r
+ /* Pass out the array that will be used as the Timer task's stack. */\r
+ *ppxTimerTaskStackBuffer = uxTimerTaskStack;\r
+\r
+ /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer.\r
+ * Note that, as the array is necessarily of type StackType_t,\r
+ * configTIMER_TASK_STACK_DEPTH is specified in words, not bytes. */\r
+ *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;\r
}\r
/*-----------------------------------------------------------*/\r
\r
*/\r
void MemManage_Handler( void )\r
{\r
- __asm volatile\r
- (\r
- " tst lr, #4 \n"\r
- " ite eq \n"\r
- " mrseq r0, msp \n"\r
- " mrsne r0, psp \n"\r
- " ldr r1, handler_address_const \n"\r
- " bx r1 \n"\r
- " \n"\r
- " handler_address_const: .word vHandleMemoryFault \n"\r
- );\r
+ __asm volatile\r
+ (\r
+ " tst lr, #4 \n"\r
+ " ite eq \n"\r
+ " mrseq r0, msp \n"\r
+ " mrsne r0, psp \n"\r
+ " ldr r1, handler_address_const \n"\r
+ " bx r1 \n"\r
+ " \n"\r
+ " handler_address_const: .word vHandleMemoryFault \n"\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
#include "secure_port_macros.h"\r
\r
/* Start address of non-secure application. */\r
-#define mainNONSECURE_APP_START_ADDRESS ( 0x200000U )\r
+#define mainNONSECURE_APP_START_ADDRESS ( 0x200000U )\r
\r
/* typedef for non-secure Reset Handler. */\r
-typedef void ( *NonSecureResetHandler_t ) ( void ) __attribute__( ( cmse_nonsecure_call ) );\r
+typedef void ( *NonSecureResetHandler_t ) ( void ) __attribute__( ( cmse_nonsecure_call ) );\r
/*-----------------------------------------------------------*/\r
\r
/* Boot into the non-secure code. */\r
\r
void BootNonSecure( uint32_t ulNonSecureStartAddress )\r
{\r
- NonSecureResetHandler_t pxNonSecureResetHandler;\r
+ NonSecureResetHandler_t pxNonSecureResetHandler;\r
\r
- /* Main Stack Pointer value for the non-secure side is the first entry in\r
- * the non-secure vector table. Read the first entry and assign the same to\r
- * the non-secure main stack pointer(MSP_NS). */\r
- secureportSET_MSP_NS( *( ( uint32_t * )( ulNonSecureStartAddress ) ) );\r
+ /* Main Stack Pointer value for the non-secure side is the first entry in\r
+ * the non-secure vector table. Read the first entry and assign the same to\r
+ * the non-secure main stack pointer(MSP_NS). */\r
+ secureportSET_MSP_NS( *( ( uint32_t * )( ulNonSecureStartAddress ) ) );\r
\r
- /* Non secure Reset Handler is the second entry in the non-secure vector\r
- * table. Read the non-secure reset handler.\r
- */\r
- pxNonSecureResetHandler = ( NonSecureResetHandler_t )( * ( ( uint32_t * ) ( ( ulNonSecureStartAddress ) + 4U ) ) );\r
+ /* Non secure Reset Handler is the second entry in the non-secure vector\r
+ * table. Read the non-secure reset handler.\r
+ */\r
+ pxNonSecureResetHandler = ( NonSecureResetHandler_t )( * ( ( uint32_t * ) ( ( ulNonSecureStartAddress ) + 4U ) ) );\r
\r
- /* Start non-secure software application by jumping to the non-secure Reset\r
- * Handler. */\r
- pxNonSecureResetHandler();\r
+ /* Start non-secure software application by jumping to the non-secure Reset\r
+ * Handler. */\r
+ pxNonSecureResetHandler();\r
}\r
/*-----------------------------------------------------------*/\r
\r
/* Secure main() */\r
int main( void )\r
{\r
- /* Boot the non-secure code. */\r
- BootNonSecure( mainNONSECURE_APP_START_ADDRESS );\r
+ /* Boot the non-secure code. */\r
+ BootNonSecure( mainNONSECURE_APP_START_ADDRESS );\r
\r
- /* Non-secure software does not return, this code is not executed. */\r
- for( ; ; )\r
- {\r
- /* Should not reach here. */\r
- }\r
+ /* Non-secure software does not return, this code is not executed. */\r
+ for( ; ; )\r
+ {\r
+ /* Should not reach here. */\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
{\r
uint8_t ucVal;\r
\r
- /* Unused parameters. */\r
- ( void ) pvParameters;\r
-\r
- for( ; ; )\r
- {\r
- /* This task has RO access to ucSharedMemory and therefore it can read\r
- * it but cannot modify it. */\r
- ucVal = ucSharedMemory[ 0 ];\r
-\r
- /* Silent compiler warnings about unused variables. */\r
- ( void ) ucVal;\r
-\r
- /* Since this task has Read Only access to the ucSharedMemory region,\r
- * writing to it results in Memory Fault. Set ucROTaskFaultTracker[ 0 ]\r
- * to 1 to tell the Memory Fault Handler that this is an expected fault.\r
- * The handler will recover from this fault gracefully by jumping to the\r
- * next instruction. */\r
- ucROTaskFaultTracker[ 0 ] = 1;\r
-\r
- /* Illegal access to generate Memory Fault. */\r
- ucSharedMemory[ 0 ] = 0;\r
-\r
- /* Wait for a second. */\r
- vTaskDelay( pdMS_TO_TICKS( 1000 ) );\r
- }\r
+ /* Unused parameters. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ; ; )\r
+ {\r
+ /* This task has RO access to ucSharedMemory and therefore it can read\r
+ * it but cannot modify it. */\r
+ ucVal = ucSharedMemory[ 0 ];\r
+\r
+ /* Silent compiler warnings about unused variables. */\r
+ ( void ) ucVal;\r
+\r
+ /* Since this task has Read Only access to the ucSharedMemory region,\r
+ * writing to it results in Memory Fault. Set ucROTaskFaultTracker[ 0 ]\r
+ * to 1 to tell the Memory Fault Handler that this is an expected fault.\r
+ * The handler will recover from this fault gracefully by jumping to the\r
+ * next instruction. */\r
+ ucROTaskFaultTracker[ 0 ] = 1;\r
+\r
+ /* Illegal access to generate Memory Fault. */\r
+ ucSharedMemory[ 0 ] = 0;\r
+\r
+ /* Wait for a second. */\r
+ vTaskDelay( pdMS_TO_TICKS( 1000 ) );\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
\r
static void prvRWAccessTask( void * pvParameters )\r
{\r
- /* Unused parameters. */\r
- ( void ) pvParameters;\r
-\r
- for( ; ; )\r
- {\r
- /* This task has RW access to ucSharedMemory and therefore can write to\r
- * it. */\r
- ucSharedMemory[ 0 ] = 0;\r
-\r
- /* Wait for a second. */\r
- vTaskDelay( pdMS_TO_TICKS( 1000 ) );\r
- }\r
+ /* Unused parameters. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ; ; )\r
+ {\r
+ /* This task has RW access to ucSharedMemory and therefore can write to\r
+ * it. */\r
+ ucSharedMemory[ 0 ] = 0;\r
+\r
+ /* Wait for a second. */\r
+ vTaskDelay( pdMS_TO_TICKS( 1000 ) );\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
\r
static StackType_t xRWAccessTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( 32 ) ) );\r
TaskParameters_t xROAccessTaskParameters =\r
{\r
- .pvTaskCode = prvROAccessTask,\r
- .pcName = "ROAccess",\r
- .usStackDepth = configMINIMAL_STACK_SIZE,\r
- .pvParameters = NULL,\r
- .uxPriority = tskIDLE_PRIORITY,\r
- .puxStackBuffer = xROAccessTaskStack,\r
- .xRegions = {\r
- { ucSharedMemory, 32, tskMPU_REGION_READ_ONLY | tskMPU_REGION_EXECUTE_NEVER },\r
- { ucROTaskFaultTracker, 32, tskMPU_REGION_READ_WRITE | tskMPU_REGION_EXECUTE_NEVER },\r
- { 0, 0, 0 },\r
- }\r
+ .pvTaskCode = prvROAccessTask,\r
+ .pcName = "ROAccess",\r
+ .usStackDepth = configMINIMAL_STACK_SIZE,\r
+ .pvParameters = NULL,\r
+ .uxPriority = tskIDLE_PRIORITY,\r
+ .puxStackBuffer = xROAccessTaskStack,\r
+ .xRegions = {\r
+ { ucSharedMemory, 32, tskMPU_REGION_READ_ONLY | tskMPU_REGION_EXECUTE_NEVER },\r
+ { ucROTaskFaultTracker, 32, tskMPU_REGION_READ_WRITE | tskMPU_REGION_EXECUTE_NEVER },\r
+ { 0, 0, 0 },\r
+ }\r
};\r
TaskParameters_t xRWAccessTaskParameters =\r
{\r
- .pvTaskCode = prvRWAccessTask,\r
- .pcName = "RWAccess",\r
- .usStackDepth = configMINIMAL_STACK_SIZE,\r
- .pvParameters = NULL,\r
- .uxPriority = tskIDLE_PRIORITY,\r
- .puxStackBuffer = xRWAccessTaskStack,\r
- .xRegions = {\r
- { ucSharedMemory, 32, tskMPU_REGION_READ_WRITE | tskMPU_REGION_EXECUTE_NEVER },\r
- { 0, 0, 0 },\r
- { 0, 0, 0 },\r
- }\r
+ .pvTaskCode = prvRWAccessTask,\r
+ .pcName = "RWAccess",\r
+ .usStackDepth = configMINIMAL_STACK_SIZE,\r
+ .pvParameters = NULL,\r
+ .uxPriority = tskIDLE_PRIORITY,\r
+ .puxStackBuffer = xRWAccessTaskStack,\r
+ .xRegions = {\r
+ { ucSharedMemory, 32, tskMPU_REGION_READ_WRITE | tskMPU_REGION_EXECUTE_NEVER },\r
+ { 0, 0, 0 },\r
+ { 0, 0, 0 },\r
+ }\r
};\r
\r
- /* Create an unprivileged task with RO access to ucSharedMemory. */\r
- xTaskCreateRestricted( &( xROAccessTaskParameters ), NULL );\r
+ /* Create an unprivileged task with RO access to ucSharedMemory. */\r
+ xTaskCreateRestricted( &( xROAccessTaskParameters ), NULL );\r
\r
- /* Create an unprivileged task with RW access to ucSharedMemory. */\r
- xTaskCreateRestricted( &( xRWAccessTaskParameters ), NULL );\r
+ /* Create an unprivileged task with RW access to ucSharedMemory. */\r
+ xTaskCreateRestricted( &( xRWAccessTaskParameters ), NULL );\r
}\r
/*-----------------------------------------------------------*/\r
\r
{\r
uint32_t ulPC;\r
\r
- /* Is this an expected fault? */\r
- if( ucROTaskFaultTracker[ 0 ] == 1 )\r
- {\r
- /* Read program counter. */\r
- ulPC = pulFaultStackAddress[ 6 ];\r
-\r
- /* Increment the program counter by 2 to move to the next instruction. */\r
- ulPC += 2;\r
-\r
- /* Save the new program counter on the stack. */\r
- pulFaultStackAddress[ 6 ] = ulPC;\r
-\r
- /* Mark the fault as handled. */\r
- ucROTaskFaultTracker[ 0 ] = 0;\r
- }\r
- else\r
- {\r
- /* This is an unexpected fault - loop forever. */\r
- for( ; ; )\r
- {\r
- }\r
- }\r
+ /* Is this an expected fault? */\r
+ if( ucROTaskFaultTracker[ 0 ] == 1 )\r
+ {\r
+ /* Read program counter. */\r
+ ulPC = pulFaultStackAddress[ 6 ];\r
+\r
+ /* Increment the program counter by 2 to move to the next instruction. */\r
+ ulPC += 2;\r
+\r
+ /* Save the new program counter on the stack. */\r
+ pulFaultStackAddress[ 6 ] = ulPC;\r
+\r
+ /* Mark the fault as handled. */\r
+ ucROTaskFaultTracker[ 0 ] = 0;\r
+ }\r
+ else\r
+ {\r
+ /* This is an unexpected fault - loop forever. */\r
+ for( ; ; )\r
+ {\r
+ }\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
{\r
NonSecureCallback_t pxNonSecureCallback;\r
\r
- /* Return function pointer with cleared LSB. */\r
- pxNonSecureCallback = ( NonSecureCallback_t ) cmse_nsfptr_create( pxCallback );\r
+ /* Return function pointer with cleared LSB. */\r
+ pxNonSecureCallback = ( NonSecureCallback_t ) cmse_nsfptr_create( pxCallback );\r
\r
- /* Invoke the supplied callback. */\r
- pxNonSecureCallback();\r
+ /* Invoke the supplied callback. */\r
+ pxNonSecureCallback();\r
\r
- /* Increment the secure side counter. */\r
- ulSecureCounter += 1;\r
+ /* Increment the secure side counter. */\r
+ ulSecureCounter += 1;\r
\r
- /* Return the secure side counter. */\r
- return ulSecureCounter;\r
+ /* Return the secure side counter. */\r
+ return ulSecureCounter;\r
}\r
/*-----------------------------------------------------------*/\r
static StackType_t xSecureCallingTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( 32 ) ) );\r
TaskParameters_t xSecureCallingTaskParameters =\r
{\r
- .pvTaskCode = prvSecureCallingTask,\r
- .pcName = "SecCalling",\r
- .usStackDepth = configMINIMAL_STACK_SIZE,\r
- .pvParameters = NULL,\r
- .uxPriority = tskIDLE_PRIORITY,\r
- .puxStackBuffer = xSecureCallingTaskStack,\r
- .xRegions = {\r
- { ulNonSecureCounter, 32, tskMPU_REGION_READ_WRITE | tskMPU_REGION_EXECUTE_NEVER },\r
- { 0, 0, 0 },\r
- { 0, 0, 0 },\r
- }\r
+ .pvTaskCode = prvSecureCallingTask,\r
+ .pcName = "SecCalling",\r
+ .usStackDepth = configMINIMAL_STACK_SIZE,\r
+ .pvParameters = NULL,\r
+ .uxPriority = tskIDLE_PRIORITY,\r
+ .puxStackBuffer = xSecureCallingTaskStack,\r
+ .xRegions = {\r
+ { ulNonSecureCounter, 32, tskMPU_REGION_READ_WRITE | tskMPU_REGION_EXECUTE_NEVER },\r
+ { 0, 0, 0 },\r
+ { 0, 0, 0 },\r
+ }\r
};\r
\r
- /* Create an unprivileged task which calls secure functions. */\r
- xTaskCreateRestricted( &( xSecureCallingTaskParameters ), NULL );\r
+ /* Create an unprivileged task which calls secure functions. */\r
+ xTaskCreateRestricted( &( xSecureCallingTaskParameters ), NULL );\r
}\r
/*-----------------------------------------------------------*/\r
\r
static void prvCallback( void )\r
{\r
- /* This function is called from the secure side. Just increment the counter\r
- * here. The check that this counter keeps incrementing is performed in the\r
- * prvSecureCallingTask. */\r
- ulNonSecureCounter[ 0 ] += 1;\r
+ /* This function is called from the secure side. Just increment the counter\r
+ * here. The check that this counter keeps incrementing is performed in the\r
+ * prvSecureCallingTask. */\r
+ ulNonSecureCounter[ 0 ] += 1;\r
}\r
/*-----------------------------------------------------------*/\r
\r
uint32_t ulLastSecureCounter = 0, ulLastNonSecureCounter = 0;\r
uint32_t ulCurrentSecureCounter = 0;\r
\r
- /* This task calls secure side functions. So allocate a secure context for\r
- * it. */\r
- portALLOCATE_SECURE_CONTEXT( configMINIMAL_SECURE_STACK_SIZE );\r
+ /* This task calls secure side functions. So allocate a secure context for\r
+ * it. */\r
+ portALLOCATE_SECURE_CONTEXT( configMINIMAL_SECURE_STACK_SIZE );\r
\r
- for( ; ; )\r
- {\r
- /* Call the secure side function. It does two things:\r
- * - It calls the supplied function (prvCallback) which in turn\r
- * increments the non-secure counter.\r
- * - It increments the secure counter and returns the incremented value.\r
- * Therefore at the end of this function call both the secure and\r
- * non-secure counters must have been incremented.\r
- */\r
- ulCurrentSecureCounter = NSCFunction( prvCallback );\r
+ for( ; ; )\r
+ {\r
+ /* Call the secure side function. It does two things:\r
+ * - It calls the supplied function (prvCallback) which in turn\r
+ * increments the non-secure counter.\r
+ * - It increments the secure counter and returns the incremented value.\r
+ * Therefore at the end of this function call both the secure and\r
+ * non-secure counters must have been incremented.\r
+ */\r
+ ulCurrentSecureCounter = NSCFunction( prvCallback );\r
\r
- /* Make sure that both the counters are incremented. */\r
- configASSERT( ulCurrentSecureCounter == ulLastSecureCounter + 1 );\r
- configASSERT( ulNonSecureCounter[ 0 ] == ulLastNonSecureCounter + 1 );\r
+ /* Make sure that both the counters are incremented. */\r
+ configASSERT( ulCurrentSecureCounter == ulLastSecureCounter + 1 );\r
+ configASSERT( ulNonSecureCounter[ 0 ] == ulLastNonSecureCounter + 1 );\r
\r
- /* Update the last values for both the counters. */\r
- ulLastSecureCounter = ulCurrentSecureCounter;\r
- ulLastNonSecureCounter = ulNonSecureCounter[ 0 ];\r
+ /* Update the last values for both the counters. */\r
+ ulLastSecureCounter = ulCurrentSecureCounter;\r
+ ulLastNonSecureCounter = ulNonSecureCounter[ 0 ];\r
\r
- /* Wait for a second. */\r
- vTaskDelay( pdMS_TO_TICKS( 1000 ) );\r
- }\r
+ /* Wait for a second. */\r
+ vTaskDelay( pdMS_TO_TICKS( 1000 ) );\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
#include "portasm.h"\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
- /* Secure components includes. */\r
- #include "secure_context.h"\r
- #include "secure_init.h"\r
+ /* Secure components includes. */\r
+ #include "secure_context.h"\r
+ #include "secure_init.h"\r
#endif /* configENABLE_TRUSTZONE */\r
\r
#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
+/**\r
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only\r
+ * i.e. the processor boots as secure and never jumps to the non-secure side.\r
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS\r
+ * on the secure side. The following are the valid configuration seetings:\r
+ *\r
+ * 1. Run FreeRTOS on the Secure Side:\r
+ * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0\r
+ *\r
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:\r
+ * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1\r
+ *\r
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:\r
+ * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0\r
+ */\r
+#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )\r
+ #error Trust Zone needs to be disabled in order to run FreeRTOS on the Secure Side.\r
+#endif\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Constants required to manipulate the NVIC.\r
*/\r
-#define portNVIC_SYSTICK_CTRL ( ( volatile uint32_t * ) 0xe000e010 )\r
-#define portNVIC_SYSTICK_LOAD ( ( volatile uint32_t * ) 0xe000e014 )\r
-#define portNVIC_SYSTICK_CURRENT_VALUE ( ( volatile uint32_t * ) 0xe000e018 )\r
-#define portNVIC_INT_CTRL ( ( volatile uint32_t * ) 0xe000ed04 )\r
-#define portNVIC_SYSPRI2 ( ( volatile uint32_t * ) 0xe000ed20 )\r
-#define portNVIC_SYSTICK_CLK ( 0x00000004 )\r
-#define portNVIC_SYSTICK_INT ( 0x00000002 )\r
-#define portNVIC_SYSTICK_ENABLE ( 0x00000001 )\r
-#define portNVIC_PENDSVSET ( 0x10000000 )\r
-#define portMIN_INTERRUPT_PRIORITY ( 255UL )\r
-#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )\r
-#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )\r
+#define portNVIC_SYSTICK_CTRL ( ( volatile uint32_t * ) 0xe000e010 )\r
+#define portNVIC_SYSTICK_LOAD ( ( volatile uint32_t * ) 0xe000e014 )\r
+#define portNVIC_SYSTICK_CURRENT_VALUE ( ( volatile uint32_t * ) 0xe000e018 )\r
+#define portNVIC_INT_CTRL ( ( volatile uint32_t * ) 0xe000ed04 )\r
+#define portNVIC_SYSPRI2 ( ( volatile uint32_t * ) 0xe000ed20 )\r
+#define portNVIC_SYSTICK_CLK ( 0x00000004 )\r
+#define portNVIC_SYSTICK_INT ( 0x00000002 )\r
+#define portNVIC_SYSTICK_ENABLE ( 0x00000001 )\r
+#define portNVIC_PENDSVSET ( 0x10000000 )\r
+#define portMIN_INTERRUPT_PRIORITY ( 255UL )\r
+#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )\r
+#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Constants required to manipulate the SCB.\r
*/\r
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( * ( volatile uint32_t * ) 0xe000ed24 )\r
-#define portSCB_MEM_FAULT_ENABLE ( 1UL << 16UL )\r
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( * ( volatile uint32_t * ) 0xe000ed24 )\r
+#define portSCB_MEM_FAULT_ENABLE ( 1UL << 16UL )\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Constants required to manipulate the FPU.\r
*/\r
-#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */\r
-#define portCPACR_CP10_VALUE ( 3UL )\r
-#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE\r
-#define portCPACR_CP10_POS ( 20UL )\r
-#define portCPACR_CP11_POS ( 22UL )\r
-\r
-#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */\r
-#define portFPCCR_ASPEN_POS ( 31UL )\r
-#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS )\r
-#define portFPCCR_LSPEN_POS ( 30UL )\r
-#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS )\r
+#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */\r
+#define portCPACR_CP10_VALUE ( 3UL )\r
+#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE\r
+#define portCPACR_CP10_POS ( 20UL )\r
+#define portCPACR_CP11_POS ( 22UL )\r
+\r
+#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */\r
+#define portFPCCR_ASPEN_POS ( 31UL )\r
+#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS )\r
+#define portFPCCR_LSPEN_POS ( 30UL )\r
+#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS )\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Constants required to manipulate the MPU.\r
*/\r
-#define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )\r
-#define portMPU_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )\r
-#define portMPU_RNR_REG ( * ( ( volatile uint32_t * ) 0xe000ed98 ) )\r
+#define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )\r
+#define portMPU_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )\r
+#define portMPU_RNR_REG ( * ( ( volatile uint32_t * ) 0xe000ed98 ) )\r
\r
-#define portMPU_RBAR_REG ( * ( ( volatile uint32_t * ) 0xe000ed9c ) )\r
-#define portMPU_RLAR_REG ( * ( ( volatile uint32_t * ) 0xe000eda0 ) )\r
+#define portMPU_RBAR_REG ( * ( ( volatile uint32_t * ) 0xe000ed9c ) )\r
+#define portMPU_RLAR_REG ( * ( ( volatile uint32_t * ) 0xe000eda0 ) )\r
\r
-#define portMPU_RBAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda4 ) )\r
-#define portMPU_RLAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda8 ) )\r
+#define portMPU_RBAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda4 ) )\r
+#define portMPU_RLAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda8 ) )\r
\r
-#define portMPU_RBAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edac ) )\r
-#define portMPU_RLAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edb0 ) )\r
+#define portMPU_RBAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edac ) )\r
+#define portMPU_RLAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edb0 ) )\r
\r
-#define portMPU_RBAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb4 ) )\r
-#define portMPU_RLAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb8 ) )\r
+#define portMPU_RBAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb4 ) )\r
+#define portMPU_RLAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb8 ) )\r
\r
-#define portMPU_MAIR0_REG ( * ( ( volatile uint32_t * ) 0xe000edc0 ) )\r
-#define portMPU_MAIR1_REG ( * ( ( volatile uint32_t * ) 0xe000edc4 ) )\r
+#define portMPU_MAIR0_REG ( * ( ( volatile uint32_t * ) 0xe000edc0 ) )\r
+#define portMPU_MAIR1_REG ( * ( ( volatile uint32_t * ) 0xe000edc4 ) )\r
\r
-#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
-#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
+#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
+#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
\r
-#define portMPU_MAIR_ATTR0_POS ( 0UL )\r
-#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )\r
+#define portMPU_MAIR_ATTR0_POS ( 0UL )\r
+#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )\r
\r
-#define portMPU_MAIR_ATTR1_POS ( 8UL )\r
-#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )\r
+#define portMPU_MAIR_ATTR1_POS ( 8UL )\r
+#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )\r
\r
-#define portMPU_MAIR_ATTR2_POS ( 16UL )\r
-#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )\r
+#define portMPU_MAIR_ATTR2_POS ( 16UL )\r
+#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )\r
\r
-#define portMPU_MAIR_ATTR3_POS ( 24UL )\r
-#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )\r
+#define portMPU_MAIR_ATTR3_POS ( 24UL )\r
+#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )\r
\r
-#define portMPU_MAIR_ATTR4_POS ( 0UL )\r
-#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )\r
+#define portMPU_MAIR_ATTR4_POS ( 0UL )\r
+#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )\r
\r
-#define portMPU_MAIR_ATTR5_POS ( 8UL )\r
-#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )\r
+#define portMPU_MAIR_ATTR5_POS ( 8UL )\r
+#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )\r
\r
-#define portMPU_MAIR_ATTR6_POS ( 16UL )\r
-#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )\r
+#define portMPU_MAIR_ATTR6_POS ( 16UL )\r
+#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )\r
\r
-#define portMPU_MAIR_ATTR7_POS ( 24UL )\r
-#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )\r
+#define portMPU_MAIR_ATTR7_POS ( 24UL )\r
+#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )\r
\r
-#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )\r
-#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )\r
-#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )\r
-#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )\r
-#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )\r
-#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )\r
-#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )\r
-#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )\r
\r
-#define portMPU_RLAR_REGION_ENABLE ( 1UL )\r
+#define portMPU_RLAR_REGION_ENABLE ( 1UL )\r
\r
/* Enable privileged access to unmapped region. */\r
-#define portMPU_PRIV_BACKGROUND_ENABLE ( 1UL << 2UL )\r
+#define portMPU_PRIV_BACKGROUND_ENABLE ( 1UL << 2UL )\r
\r
/* Enable MPU. */\r
-#define portMPU_ENABLE ( 1UL << 0UL )\r
+#define portMPU_ENABLE ( 1UL << 0UL )\r
\r
/* Expected value of the portMPU_TYPE register. */\r
-#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */\r
+#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Constants required to set up the initial stack.\r
*/\r
-#define portINITIAL_XPSR ( 0x01000000 )\r
-\r
-/**\r
- * @brief Initial EXC_RETURN value.\r
- *\r
- * FF FF FF BC\r
- * 1111 1111 1111 1111 1111 1111 1011 1100\r
- *\r
- * Bit[6] - 0 --> The exception was taken from the Non-Secure state.\r
- * Bit[5] - 1 --> Do not skip stacking of additional state context.\r
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\r
- * Bit[3] - 1 --> Return to the Thread mode.\r
- * Bit[2] - 1 --> Restore registers from the process stack.\r
- * Bit[1] - 0 --> Reserved, 0.\r
- * Bit[0] - 0 --> The exception was taken to the Non-Secure state.\r
- */\r
-#define portINITIAL_EXC_RETURN ( 0xffffffbc )\r
+#define portINITIAL_XPSR ( 0x01000000 )\r
+\r
+#if( configRUN_FREERTOS_SECURE_ONLY == 1 )\r
+ /**\r
+ * @brief Initial EXC_RETURN value.\r
+ *\r
+ * FF FF FF FD\r
+ * 1111 1111 1111 1111 1111 1111 1111 1101\r
+ *\r
+ * Bit[6] - 1 --> The exception was taken from the Secure state.\r
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.\r
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\r
+ * Bit[3] - 1 --> Return to the Thread mode.\r
+ * Bit[2] - 1 --> Restore registers from the process stack.\r
+ * Bit[1] - 0 --> Reserved, 0.\r
+ * Bit[0] - 1 --> The exception was taken to the Secure state.\r
+ */\r
+ #define portINITIAL_EXC_RETURN ( 0xfffffffd )\r
+#else\r
+ /**\r
+ * @brief Initial EXC_RETURN value.\r
+ *\r
+ * FF FF FF BC\r
+ * 1111 1111 1111 1111 1111 1111 1011 1100\r
+ *\r
+ * Bit[6] - 0 --> The exception was taken from the Non-Secure state.\r
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.\r
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\r
+ * Bit[3] - 1 --> Return to the Thread mode.\r
+ * Bit[2] - 1 --> Restore registers from the process stack.\r
+ * Bit[1] - 0 --> Reserved, 0.\r
+ * Bit[0] - 0 --> The exception was taken to the Non-Secure state.\r
+ */\r
+ #define portINITIAL_EXC_RETURN ( 0xffffffbc )\r
+#endif /* configRUN_FREERTOS_SECURE_ONLY */\r
\r
/**\r
* @brief CONTROL register privileged bit mask.\r
* Bit[0] = 0 ==> The task is privileged.\r
* Bit[0] = 1 ==> The task is not privileged.\r
*/\r
-#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL )\r
+#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL )\r
\r
/**\r
* @brief Initial CONTROL register values.\r
*/\r
-#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 )\r
-#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 )\r
+#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 )\r
+#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 )\r
\r
/**\r
* @brief Let the user override the pre-loading of the initial LR with the\r
* in the debugger.\r
*/\r
#ifdef configTASK_RETURN_ADDRESS\r
- #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS\r
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS\r
#else\r
- #define portTASK_RETURN_ADDRESS prvTaskExitError\r
+ #define portTASK_RETURN_ADDRESS prvTaskExitError\r
#endif\r
\r
/**\r
* @brief If portPRELOAD_REGISTERS then registers will be given an initial value\r
* when a task is created. This helps in debugging at the cost of code size.\r
*/\r
-#define portPRELOAD_REGISTERS 1\r
+#define portPRELOAD_REGISTERS 1\r
\r
/**\r
* @brief A task is created without a secure context, and must call\r
* portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes\r
* any secure calls.\r
*/\r
-#define portNO_SECURE_CONTEXT 0\r
+#define portNO_SECURE_CONTEXT 0\r
/*-----------------------------------------------------------*/\r
\r
/**\r
static void prvTaskExitError( void );\r
\r
#if( configENABLE_MPU == 1 )\r
- /**\r
- * @brief Setup the Memory Protection Unit (MPU).\r
- */\r
- static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\r
+ /**\r
+ * @brief Setup the Memory Protection Unit (MPU).\r
+ */\r
+ static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\r
#endif /* configENABLE_MPU */\r
\r
#if( configENABLE_FPU == 1 )\r
- /**\r
- * @brief Setup the Floating Point Unit (FPU).\r
- */\r
- static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\r
+ /**\r
+ * @brief Setup the Floating Point Unit (FPU).\r
+ */\r
+ static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\r
#endif /* configENABLE_FPU */\r
\r
/**\r
static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
- /**\r
- * @brief Saved as part of the task context to indicate which context the\r
- * task is using on the secure side.\r
- */\r
- volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\r
+ /**\r
+ * @brief Saved as part of the task context to indicate which context the\r
+ * task is using on the secure side.\r
+ */\r
+ volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\r
#endif /* configENABLE_TRUSTZONE */\r
/*-----------------------------------------------------------*/\r
\r
static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\r
{\r
- /* Stop and reset the SysTick. */\r
- *( portNVIC_SYSTICK_CTRL ) = 0UL;\r
- *( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;\r
+ /* Stop and reset the SysTick. */\r
+ *( portNVIC_SYSTICK_CTRL ) = 0UL;\r
+ *( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;\r
\r
- /* Configure SysTick to interrupt at the requested rate. */\r
- *( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
- *( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
+ /* Configure SysTick to interrupt at the requested rate. */\r
+ *( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
+ *( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
}\r
/*-----------------------------------------------------------*/\r
\r
{\r
volatile uint32_t ulDummy = 0UL;\r
\r
- /* A function that implements a task must not exit or attempt to return to\r
- * its caller as there is nothing to return to. If a task wants to exit it\r
- * should instead call vTaskDelete( NULL ). Artificially force an assert()\r
- * to be triggered if configASSERT() is defined, then stop here so\r
- * application writers can catch the error. */\r
- configASSERT( ulCriticalNesting == ~0UL );\r
- portDISABLE_INTERRUPTS();\r
-\r
- while( ulDummy == 0 )\r
- {\r
- /* This file calls prvTaskExitError() after the scheduler has been\r
- * started to remove a compiler warning about the function being\r
- * defined but never called. ulDummy is used purely to quieten other\r
- * warnings about code appearing after this function is called - making\r
- * ulDummy volatile makes the compiler think the function could return\r
- * and therefore not output an 'unreachable code' warning for code that\r
- * appears after it. */\r
- }\r
+ /* A function that implements a task must not exit or attempt to return to\r
+ * its caller as there is nothing to return to. If a task wants to exit it\r
+ * should instead call vTaskDelete( NULL ). Artificially force an assert()\r
+ * to be triggered if configASSERT() is defined, then stop here so\r
+ * application writers can catch the error. */\r
+ configASSERT( ulCriticalNesting == ~0UL );\r
+ portDISABLE_INTERRUPTS();\r
+\r
+ while( ulDummy == 0 )\r
+ {\r
+ /* This file calls prvTaskExitError() after the scheduler has been\r
+ * started to remove a compiler warning about the function being\r
+ * defined but never called. ulDummy is used purely to quieten other\r
+ * warnings about code appearing after this function is called - making\r
+ * ulDummy volatile makes the compiler think the function could return\r
+ * and therefore not output an 'unreachable code' warning for code that\r
+ * appears after it. */\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
\r
#if( configENABLE_MPU == 1 )\r
- static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */\r
- {\r
- #if defined( __ARMCC_VERSION )\r
- /* Declaration when these variable are defined in code instead of being\r
- * exported from linker scripts. */\r
- extern uint32_t * __privileged_functions_start__;\r
- extern uint32_t * __privileged_functions_end__;\r
- extern uint32_t * __syscalls_flash_start__;\r
- extern uint32_t * __unprivileged_flash_end__;\r
- extern uint32_t * __privileged_sram_start__;\r
- extern uint32_t * __privileged_sram_end__;\r
- #else\r
- /* Declaration when these variable are exported from linker scripts. */\r
- extern uint32_t __privileged_functions_start__[];\r
- extern uint32_t __privileged_functions_end__[];\r
- extern uint32_t __syscalls_flash_start__[];\r
- extern uint32_t __unprivileged_flash_end__[];\r
- extern uint32_t __privileged_sram_start__[];\r
- extern uint32_t __privileged_sram_end__[];\r
- #endif /* defined( __ARMCC_VERSION ) */\r
-\r
- /* Check that the MPU is present. */\r
- if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\r
- {\r
- /* MAIR0 - Index 0. */\r
- portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
- /* MAIR0 - Index 1. */\r
- portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
-\r
- /* Setup privileged flash as Read Only so that privileged tasks can\r
- * read it but not modify. */\r
- portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;\r
- portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
- ( portMPU_REGION_NON_SHAREABLE ) |\r
- ( portMPU_REGION_PRIVILEGED_READ_ONLY );\r
- portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
- ( portMPU_RLAR_ATTR_INDEX0 ) |\r
- ( portMPU_RLAR_REGION_ENABLE );\r
-\r
- /* Setup unprivileged flash and system calls flash as Read Only by\r
- * both privileged and unprivileged tasks. All tasks can read it but\r
- * no-one can modify. */\r
- portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;\r
- portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
- ( portMPU_REGION_NON_SHAREABLE ) |\r
- ( portMPU_REGION_READ_ONLY );\r
- portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
- ( portMPU_RLAR_ATTR_INDEX0 ) |\r
- ( portMPU_RLAR_REGION_ENABLE );\r
-\r
- /* Setup RAM containing kernel data for privileged access only. */\r
- portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;\r
- portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
- ( portMPU_REGION_NON_SHAREABLE ) |\r
- ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
- ( portMPU_REGION_EXECUTE_NEVER );\r
- portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
- ( portMPU_RLAR_ATTR_INDEX0 ) |\r
- ( portMPU_RLAR_REGION_ENABLE );\r
-\r
- /* By default allow everything to access the general peripherals.\r
- * The system peripherals and registers are protected. */\r
- portMPU_RNR_REG = portUNPRIVILEGED_DEVICE_REGION;\r
- portMPU_RBAR_REG = ( ( ( uint32_t ) portDEVICE_REGION_START_ADDRESS ) & portMPU_RBAR_ADDRESS_MASK ) |\r
- ( portMPU_REGION_NON_SHAREABLE ) |\r
- ( portMPU_REGION_READ_WRITE ) |\r
- ( portMPU_REGION_EXECUTE_NEVER );\r
- portMPU_RLAR_REG = ( ( ( uint32_t ) portDEVICE_REGION_END_ADDRESS ) & portMPU_RLAR_ADDRESS_MASK ) |\r
- ( portMPU_RLAR_ATTR_INDEX1 ) |\r
- ( portMPU_RLAR_REGION_ENABLE );\r
-\r
- /* Enable mem fault. */\r
- portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;\r
-\r
- /* Enable MPU with privileged background access i.e. unmapped\r
- * regions have privileged access. */\r
- portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );\r
- }\r
- }\r
+ static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */\r
+ {\r
+ #if defined( __ARMCC_VERSION )\r
+ /* Declaration when these variable are defined in code instead of being\r
+ * exported from linker scripts. */\r
+ extern uint32_t * __privileged_functions_start__;\r
+ extern uint32_t * __privileged_functions_end__;\r
+ extern uint32_t * __syscalls_flash_start__;\r
+ extern uint32_t * __unprivileged_flash_end__;\r
+ extern uint32_t * __privileged_sram_start__;\r
+ extern uint32_t * __privileged_sram_end__;\r
+ #else\r
+ /* Declaration when these variable are exported from linker scripts. */\r
+ extern uint32_t __privileged_functions_start__[];\r
+ extern uint32_t __privileged_functions_end__[];\r
+ extern uint32_t __syscalls_flash_start__[];\r
+ extern uint32_t __unprivileged_flash_end__[];\r
+ extern uint32_t __privileged_sram_start__[];\r
+ extern uint32_t __privileged_sram_end__[];\r
+ #endif /* defined( __ARMCC_VERSION ) */\r
+\r
+ /* Check that the MPU is present. */\r
+ if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\r
+ {\r
+ /* MAIR0 - Index 0. */\r
+ portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
+ /* MAIR0 - Index 1. */\r
+ portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
+\r
+ /* Setup privileged flash as Read Only so that privileged tasks can\r
+ * read it but not modify. */\r
+ portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_PRIVILEGED_READ_ONLY );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Setup unprivileged flash and system calls flash as Read Only by\r
+ * both privileged and unprivileged tasks. All tasks can read it but\r
+ * no-one can modify. */\r
+ portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_ONLY );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Setup RAM containing kernel data for privileged access only. */\r
+ portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
+ ( portMPU_REGION_EXECUTE_NEVER );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* By default allow everything to access the general peripherals.\r
+ * The system peripherals and registers are protected. */\r
+ portMPU_RNR_REG = portUNPRIVILEGED_DEVICE_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) portDEVICE_REGION_START_ADDRESS ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_WRITE ) |\r
+ ( portMPU_REGION_EXECUTE_NEVER );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) portDEVICE_REGION_END_ADDRESS ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX1 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Enable mem fault. */\r
+ portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;\r
+\r
+ /* Enable MPU with privileged background access i.e. unmapped\r
+ * regions have privileged access. */\r
+ portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );\r
+ }\r
+ }\r
#endif /* configENABLE_MPU */\r
/*-----------------------------------------------------------*/\r
\r
#if( configENABLE_FPU == 1 )\r
- static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */\r
- {\r
- #if( configENABLE_TRUSTZONE == 1 )\r
- {\r
- /* Enable non-secure access to the FPU. */\r
- SecureInit_EnableNSFPUAccess();\r
- }\r
- #endif /* configENABLE_TRUSTZONE */\r
-\r
- /* CP10 = 11 ==> Full access to FPU i.e. both privileged and\r
- * unprivileged code should be able to access FPU. CP11 should be\r
- * programmed to the same value as CP10. */\r
- *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |\r
- ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )\r
- );\r
-\r
- /* ASPEN = 1 ==> Hardware should automatically preserve floating point\r
- * context on exception entry and restore on exception return.\r
- * LSPEN = 1 ==> Enable lazy context save of FP state. */\r
- *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );\r
- }\r
+ static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */\r
+ {\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ /* Enable non-secure access to the FPU. */\r
+ SecureInit_EnableNSFPUAccess();\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+\r
+ /* CP10 = 11 ==> Full access to FPU i.e. both privileged and\r
+ * unprivileged code should be able to access FPU. CP11 should be\r
+ * programmed to the same value as CP10. */\r
+ *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |\r
+ ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )\r
+ );\r
+\r
+ /* ASPEN = 1 ==> Hardware should automatically preserve floating point\r
+ * context on exception entry and restore on exception return.\r
+ * LSPEN = 1 ==> Enable lazy context save of FP state. */\r
+ *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );\r
+ }\r
#endif /* configENABLE_FPU */\r
/*-----------------------------------------------------------*/\r
\r
void vPortYield( void ) /* PRIVILEGED_FUNCTION */\r
{\r
- /* Set a PendSV to request a context switch. */\r
- *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
+ /* Set a PendSV to request a context switch. */\r
+ *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
\r
- /* Barriers are normally not required but do ensure the code is\r
- * completely within the specified behaviour for the architecture. */\r
- __asm volatile( "dsb" ::: "memory" );\r
- __asm volatile( "isb" );\r
+ /* Barriers are normally not required but do ensure the code is\r
+ * completely within the specified behaviour for the architecture. */\r
+ __asm volatile( "dsb" ::: "memory" );\r
+ __asm volatile( "isb" );\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */\r
{\r
- portDISABLE_INTERRUPTS();\r
- ulCriticalNesting++;\r
+ portDISABLE_INTERRUPTS();\r
+ ulCriticalNesting++;\r
\r
- /* Barriers are normally not required but do ensure the code is\r
- * completely within the specified behaviour for the architecture. */\r
- __asm volatile( "dsb" ::: "memory" );\r
- __asm volatile( "isb" );\r
+ /* Barriers are normally not required but do ensure the code is\r
+ * completely within the specified behaviour for the architecture. */\r
+ __asm volatile( "dsb" ::: "memory" );\r
+ __asm volatile( "isb" );\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */\r
{\r
- configASSERT( ulCriticalNesting );\r
- ulCriticalNesting--;\r
+ configASSERT( ulCriticalNesting );\r
+ ulCriticalNesting--;\r
\r
- if( ulCriticalNesting == 0 )\r
- {\r
- portENABLE_INTERRUPTS();\r
- }\r
+ if( ulCriticalNesting == 0 )\r
+ {\r
+ portENABLE_INTERRUPTS();\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
\r
{\r
uint32_t ulPreviousMask;\r
\r
- ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();\r
- {\r
- /* Increment the RTOS tick. */\r
- if( xTaskIncrementTick() != pdFALSE )\r
- {\r
- /* Pend a context switch. */\r
- *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
- }\r
- }\r
- portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );\r
+ ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();\r
+ {\r
+ /* Increment the RTOS tick. */\r
+ if( xTaskIncrementTick() != pdFALSE )\r
+ {\r
+ /* Pend a context switch. */\r
+ *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
+ }\r
+ }\r
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION */\r
{\r
#if( configENABLE_MPU == 1 )\r
- #if defined( __ARMCC_VERSION )\r
- /* Declaration when these variable are defined in code instead of being\r
- * exported from linker scripts. */\r
- extern uint32_t * __syscalls_flash_start__;\r
- extern uint32_t * __syscalls_flash_end__;\r
- #else\r
- /* Declaration when these variable are exported from linker scripts. */\r
- extern uint32_t __syscalls_flash_start__[];\r
- extern uint32_t __syscalls_flash_end__[];\r
- #endif /* defined( __ARMCC_VERSION ) */\r
+ #if defined( __ARMCC_VERSION )\r
+ /* Declaration when these variable are defined in code instead of being\r
+ * exported from linker scripts. */\r
+ extern uint32_t * __syscalls_flash_start__;\r
+ extern uint32_t * __syscalls_flash_end__;\r
+ #else\r
+ /* Declaration when these variable are exported from linker scripts. */\r
+ extern uint32_t __syscalls_flash_start__[];\r
+ extern uint32_t __syscalls_flash_end__[];\r
+ #endif /* defined( __ARMCC_VERSION ) */\r
#endif /* configENABLE_MPU */\r
\r
uint32_t ulPC;\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
- uint32_t ulR0;\r
- #if( configENABLE_MPU == 1 )\r
- uint32_t ulControl, ulIsTaskPrivileged;\r
- #endif /* configENABLE_MPU */\r
+ uint32_t ulR0;\r
+ #if( configENABLE_MPU == 1 )\r
+ uint32_t ulControl, ulIsTaskPrivileged;\r
+ #endif /* configENABLE_MPU */\r
#endif /* configENABLE_TRUSTZONE */\r
uint8_t ucSVCNumber;\r
\r
- /* Register are stored on the stack in the following order - R0, R1, R2, R3,\r
- * R12, LR, PC, xPSR. */\r
- ulPC = pulCallerStackAddress[ 6 ];\r
- ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];\r
-\r
- switch( ucSVCNumber )\r
- {\r
- #if( configENABLE_TRUSTZONE == 1 )\r
- case portSVC_ALLOCATE_SECURE_CONTEXT:\r
- {\r
- /* R0 contains the stack size passed as parameter to the\r
- * vPortAllocateSecureContext function. */\r
- ulR0 = pulCallerStackAddress[ 0 ];\r
-\r
- #if( configENABLE_MPU == 1 )\r
- {\r
- /* Read the CONTROL register value. */\r
- __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );\r
-\r
- /* The task that raised the SVC is privileged if Bit[0]\r
- * in the CONTROL register is 0. */\r
- ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );\r
-\r
- /* Allocate and load a context for the secure task. */\r
- xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );\r
- }\r
- #else\r
- {\r
- /* Allocate and load a context for the secure task. */\r
- xSecureContext = SecureContext_AllocateContext( ulR0 );\r
- }\r
- #endif /* configENABLE_MPU */\r
-\r
- configASSERT( xSecureContext != NULL );\r
- SecureContext_LoadContext( xSecureContext );\r
- }\r
- break;\r
-\r
- case portSVC_FREE_SECURE_CONTEXT:\r
- {\r
- /* R0 contains the secure context handle to be freed. */\r
- ulR0 = pulCallerStackAddress[ 0 ];\r
-\r
- /* Free the secure context. */\r
- SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );\r
- }\r
- break;\r
- #endif /* configENABLE_TRUSTZONE */\r
-\r
- case portSVC_START_SCHEDULER:\r
- {\r
- #if( configENABLE_TRUSTZONE == 1 )\r
- {\r
- /* De-prioritize the non-secure exceptions so that the\r
- * non-secure pendSV runs at the lowest priority. */\r
- SecureInit_DePrioritizeNSExceptions();\r
-\r
- /* Initialize the secure context management system. */\r
- SecureContext_Init();\r
- }\r
- #endif /* configENABLE_TRUSTZONE */\r
-\r
- #if( configENABLE_FPU == 1 )\r
- {\r
- /* Setup the Floating Point Unit (FPU). */\r
- prvSetupFPU();\r
- }\r
- #endif /* configENABLE_FPU */\r
-\r
- /* Setup the context of the first task so that the first task starts\r
- * executing. */\r
- vRestoreContextOfFirstTask();\r
- }\r
- break;\r
-\r
- #if( configENABLE_MPU == 1 )\r
- case portSVC_RAISE_PRIVILEGE:\r
- {\r
- /* Only raise the privilege, if the svc was raised from any of\r
- * the system calls. */\r
- if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&\r
- ulPC <= ( uint32_t ) __syscalls_flash_end__ )\r
- {\r
- vRaisePrivilege();\r
- }\r
- }\r
- break;\r
- #endif /* configENABLE_MPU */\r
-\r
- default:\r
- {\r
- /* Incorrect SVC call. */\r
- configASSERT( pdFALSE );\r
- }\r
- }\r
+ /* Register are stored on the stack in the following order - R0, R1, R2, R3,\r
+ * R12, LR, PC, xPSR. */\r
+ ulPC = pulCallerStackAddress[ 6 ];\r
+ ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];\r
+\r
+ switch( ucSVCNumber )\r
+ {\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ case portSVC_ALLOCATE_SECURE_CONTEXT:\r
+ {\r
+ /* R0 contains the stack size passed as parameter to the\r
+ * vPortAllocateSecureContext function. */\r
+ ulR0 = pulCallerStackAddress[ 0 ];\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ /* Read the CONTROL register value. */\r
+ __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );\r
+\r
+ /* The task that raised the SVC is privileged if Bit[0]\r
+ * in the CONTROL register is 0. */\r
+ ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );\r
+\r
+ /* Allocate and load a context for the secure task. */\r
+ xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );\r
+ }\r
+ #else\r
+ {\r
+ /* Allocate and load a context for the secure task. */\r
+ xSecureContext = SecureContext_AllocateContext( ulR0 );\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ configASSERT( xSecureContext != NULL );\r
+ SecureContext_LoadContext( xSecureContext );\r
+ }\r
+ break;\r
+\r
+ case portSVC_FREE_SECURE_CONTEXT:\r
+ {\r
+ /* R0 contains the secure context handle to be freed. */\r
+ ulR0 = pulCallerStackAddress[ 0 ];\r
+\r
+ /* Free the secure context. */\r
+ SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );\r
+ }\r
+ break;\r
+ #endif /* configENABLE_TRUSTZONE */\r
+\r
+ case portSVC_START_SCHEDULER:\r
+ {\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ /* De-prioritize the non-secure exceptions so that the\r
+ * non-secure pendSV runs at the lowest priority. */\r
+ SecureInit_DePrioritizeNSExceptions();\r
+\r
+ /* Initialize the secure context management system. */\r
+ SecureContext_Init();\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+\r
+ #if( configENABLE_FPU == 1 )\r
+ {\r
+ /* Setup the Floating Point Unit (FPU). */\r
+ prvSetupFPU();\r
+ }\r
+ #endif /* configENABLE_FPU */\r
+\r
+ /* Setup the context of the first task so that the first task starts\r
+ * executing. */\r
+ vRestoreContextOfFirstTask();\r
+ }\r
+ break;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ case portSVC_RAISE_PRIVILEGE:\r
+ {\r
+ /* Only raise the privilege, if the svc was raised from any of\r
+ * the system calls. */\r
+ if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&\r
+ ulPC <= ( uint32_t ) __syscalls_flash_end__ )\r
+ {\r
+ vRaisePrivilege();\r
+ }\r
+ }\r
+ break;\r
+ #endif /* configENABLE_MPU */\r
+\r
+ default:\r
+ {\r
+ /* Incorrect SVC call. */\r
+ configASSERT( pdFALSE );\r
+ }\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
\r
#if( configENABLE_MPU == 1 )\r
- StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */\r
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */\r
#else\r
- StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */\r
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */\r
#endif /* configENABLE_MPU */\r
{\r
- /* Simulate the stack frame as it would be created by a context switch\r
- * interrupt. */\r
- #if( portPRELOAD_REGISTERS == 0 )\r
- {\r
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
- *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\r
- pxTopOfStack -= 5; /* R12, R3, R2 and R1. */\r
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
- pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */\r
- *pxTopOfStack = portINITIAL_EXC_RETURN;\r
-\r
- #if( configENABLE_MPU == 1 )\r
- {\r
- pxTopOfStack--;\r
- if( xRunPrivileged == pdTRUE )\r
- {\r
- *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
- }\r
- else\r
- {\r
- *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
- }\r
- }\r
- #endif /* configENABLE_MPU */\r
-\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\r
-\r
- #if( configENABLE_TRUSTZONE == 1 )\r
- {\r
- pxTopOfStack--;\r
- *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\r
- }\r
- #endif /* configENABLE_TRUSTZONE */\r
- }\r
- #else /* portPRELOAD_REGISTERS */\r
- {\r
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
- *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */\r
-\r
- #if( configENABLE_MPU == 1 )\r
- {\r
- pxTopOfStack--;\r
- if( xRunPrivileged == pdTRUE )\r
- {\r
- *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
- }\r
- else\r
- {\r
- *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
- }\r
- }\r
- #endif /* configENABLE_MPU */\r
-\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\r
-\r
- #if( configENABLE_TRUSTZONE == 1 )\r
- {\r
- pxTopOfStack--;\r
- *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\r
- }\r
- #endif /* configENABLE_TRUSTZONE */\r
- }\r
- #endif /* portPRELOAD_REGISTERS */\r
-\r
- return pxTopOfStack;\r
+ /* Simulate the stack frame as it would be created by a context switch\r
+ * interrupt. */\r
+ #if( portPRELOAD_REGISTERS == 0 )\r
+ {\r
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\r
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */\r
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
+ pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */\r
+ *pxTopOfStack = portINITIAL_EXC_RETURN;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ if( xRunPrivileged == pdTRUE )\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ else\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\r
+\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+ }\r
+ #else /* portPRELOAD_REGISTERS */\r
+ {\r
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ if( xRunPrivileged == pdTRUE )\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ else\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\r
+\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+ }\r
+ #endif /* portPRELOAD_REGISTERS */\r
+\r
+ return pxTopOfStack;\r
}\r
/*-----------------------------------------------------------*/\r
\r
BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */\r
{\r
- /* Make PendSV, CallSV and SysTick the same priority as the kernel. */\r
- *( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;\r
- *( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;\r
-\r
- #if( configENABLE_MPU == 1 )\r
- {\r
- /* Setup the Memory Protection Unit (MPU). */\r
- prvSetupMPU();\r
- }\r
- #endif /* configENABLE_MPU */\r
-\r
- /* Start the timer that generates the tick ISR. Interrupts are disabled\r
- * here already. */\r
- prvSetupTimerInterrupt();\r
-\r
- /* Initialize the critical nesting count ready for the first task. */\r
- ulCriticalNesting = 0;\r
-\r
- /* Start the first task. */\r
- vStartFirstTask();\r
-\r
- /* Should never get here as the tasks will now be executing. Call the task\r
- * exit error function to prevent compiler warnings about a static function\r
- * not being called in the case that the application writer overrides this\r
- * functionality by defining configTASK_RETURN_ADDRESS. Call\r
- * vTaskSwitchContext() so link time optimization does not remove the\r
- * symbol. */\r
- vTaskSwitchContext();\r
- prvTaskExitError();\r
-\r
- /* Should not get here. */\r
- return 0;\r
+ /* Make PendSV, CallSV and SysTick the same priority as the kernel. */\r
+ *( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;\r
+ *( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ /* Setup the Memory Protection Unit (MPU). */\r
+ prvSetupMPU();\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ /* Start the timer that generates the tick ISR. Interrupts are disabled\r
+ * here already. */\r
+ prvSetupTimerInterrupt();\r
+\r
+ /* Initialize the critical nesting count ready for the first task. */\r
+ ulCriticalNesting = 0;\r
+\r
+ /* Start the first task. */\r
+ vStartFirstTask();\r
+\r
+ /* Should never get here as the tasks will now be executing. Call the task\r
+ * exit error function to prevent compiler warnings about a static function\r
+ * not being called in the case that the application writer overrides this\r
+ * functionality by defining configTASK_RETURN_ADDRESS. Call\r
+ * vTaskSwitchContext() so link time optimization does not remove the\r
+ * symbol. */\r
+ vTaskSwitchContext();\r
+ prvTaskExitError();\r
+\r
+ /* Should not get here. */\r
+ return 0;\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */\r
{\r
- /* Not implemented in ports where there is nothing to return to.\r
- * Artificially force an assert. */\r
- configASSERT( ulCriticalNesting == 1000UL );\r
+ /* Not implemented in ports where there is nothing to return to.\r
+ * Artificially force an assert. */\r
+ configASSERT( ulCriticalNesting == 1000UL );\r
}\r
/*-----------------------------------------------------------*/\r
\r
#if( configENABLE_MPU == 1 )\r
- void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )\r
- {\r
- uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;\r
- int32_t lIndex = 0;\r
-\r
- /* Setup MAIR0. */\r
- xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
- xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
-\r
- /* This function is called automatically when the task is created - in\r
- * which case the stack region parameters will be valid. At all other\r
- * times the stack parameters will not be valid and it is assumed that\r
- * the stack region has already been configured. */\r
- if( ulStackDepth > 0 )\r
- {\r
- /* Define the region that allows access to the stack. */\r
- ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;\r
- ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;\r
- ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\r
-\r
- xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |\r
- ( portMPU_REGION_NON_SHAREABLE ) |\r
- ( portMPU_REGION_READ_WRITE ) |\r
- ( portMPU_REGION_EXECUTE_NEVER );\r
-\r
- xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |\r
- ( portMPU_RLAR_ATTR_INDEX0 ) |\r
- ( portMPU_RLAR_REGION_ENABLE );\r
- }\r
-\r
- /* User supplied configurable regions. */\r
- for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )\r
- {\r
- /* If xRegions is NULL i.e. the task has not specified any MPU\r
- * region, the else part ensures that all the configurable MPU\r
- * regions are invalidated. */\r
- if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )\r
- {\r
- /* Translate the generic region definition contained in xRegions\r
- * into the ARMv8 specific MPU settings that are then stored in\r
- * xMPUSettings. */\r
- ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;\r
- ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;\r
- ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\r
-\r
- /* Start address. */\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |\r
- ( portMPU_REGION_NON_SHAREABLE );\r
-\r
- /* RO/RW. */\r
- if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )\r
- {\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );\r
- }\r
- else\r
- {\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );\r
- }\r
-\r
- /* XN. */\r
- if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )\r
- {\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );\r
- }\r
-\r
- /* End Address. */\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |\r
- ( portMPU_RLAR_REGION_ENABLE );\r
-\r
- /* Normal memory/ Device memory. */\r
- if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )\r
- {\r
- /* Attr1 in MAIR0 is configured as device memory. */\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;\r
- }\r
- else\r
- {\r
- /* Attr1 in MAIR0 is configured as normal memory. */\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;\r
- }\r
- }\r
- else\r
- {\r
- /* Invalidate the region. */\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;\r
- }\r
-\r
- lIndex++;\r
- }\r
- }\r
+ void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )\r
+ {\r
+ uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;\r
+ int32_t lIndex = 0;\r
+\r
+ /* Setup MAIR0. */\r
+ xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
+ xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
+\r
+ /* This function is called automatically when the task is created - in\r
+ * which case the stack region parameters will be valid. At all other\r
+ * times the stack parameters will not be valid and it is assumed that\r
+ * the stack region has already been configured. */\r
+ if( ulStackDepth > 0 )\r
+ {\r
+ /* Define the region that allows access to the stack. */\r
+ ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;\r
+ ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;\r
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\r
+\r
+ xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_WRITE ) |\r
+ ( portMPU_REGION_EXECUTE_NEVER );\r
+\r
+ xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+ }\r
+\r
+ /* User supplied configurable regions. */\r
+ for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )\r
+ {\r
+ /* If xRegions is NULL i.e. the task has not specified any MPU\r
+ * region, the else part ensures that all the configurable MPU\r
+ * regions are invalidated. */\r
+ if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )\r
+ {\r
+ /* Translate the generic region definition contained in xRegions\r
+ * into the ARMv8 specific MPU settings that are then stored in\r
+ * xMPUSettings. */\r
+ ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;\r
+ ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;\r
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\r
+\r
+ /* Start address. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |\r
+ ( portMPU_REGION_NON_SHAREABLE );\r
+\r
+ /* RO/RW. */\r
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )\r
+ {\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );\r
+ }\r
+ else\r
+ {\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );\r
+ }\r
+\r
+ /* XN. */\r
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )\r
+ {\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );\r
+ }\r
+\r
+ /* End Address. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Normal memory/ Device memory. */\r
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )\r
+ {\r
+ /* Attr1 in MAIR0 is configured as device memory. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;\r
+ }\r
+ else\r
+ {\r
+ /* Attr1 in MAIR0 is configured as normal memory. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Invalidate the region. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;\r
+ }\r
+\r
+ lIndex++;\r
+ }\r
+ }\r
#endif /* configENABLE_MPU */\r
/*-----------------------------------------------------------*/\r
\r
void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
{\r
- __asm volatile\r
- (\r
- " .syntax unified \n"\r
- " \n"\r
- " ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
- " ldr r3, [r2] \n" /* Read pxCurrentTCB. */\r
- " ldr r0, [r3] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
- " \n"\r
- #if( configENABLE_MPU == 1 )\r
- " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
- " ldr r4, [r3] \n" /* r4 = *r3 i.e. r4 = MAIR0. */\r
- " ldr r2, xMAIR0Const2 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
- " str r4, [r2] \n" /* Program MAIR0. */\r
- " ldr r2, xRNRConst2 \n" /* r2 = 0xe000ed98 [Location of RNR]. */\r
- " movs r4, #4 \n" /* r4 = 4. */\r
- " str r4, [r2] \n" /* Program RNR = 4. */\r
- " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\r
- " ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */\r
- " ldmia r3!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */\r
- " stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
- #endif /* configENABLE_MPU */\r
- " \n"\r
- #if( configENABLE_MPU == 1 )\r
- " ldm r0!, {r1-r4} \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */\r
- " ldr r5, xSecureContextConst2 \n"\r
- " str r1, [r5] \n" /* Set xSecureContext to this task's value for the same. */\r
- " msr psplim, r2 \n" /* Set this task's PSPLIM value. */\r
- " msr control, r3 \n" /* Set this task's CONTROL value. */\r
- " adds r0, #32 \n" /* Discard everything up to r0. */\r
- " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */\r
- " isb \n"\r
- " bx r4 \n" /* Finally, branch to EXC_RETURN. */\r
- #else /* configENABLE_MPU */\r
- " ldm r0!, {r1-r3} \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */\r
- " ldr r4, xSecureContextConst2 \n"\r
- " str r1, [r4] \n" /* Set xSecureContext to this task's value for the same. */\r
- " msr psplim, r2 \n" /* Set this task's PSPLIM value. */\r
- " movs r1, #2 \n" /* r1 = 2. */\r
- " msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */\r
- " adds r0, #32 \n" /* Discard everything up to r0. */\r
- " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */\r
- " isb \n"\r
- " bx r3 \n" /* Finally, branch to EXC_RETURN. */\r
- #endif /* configENABLE_MPU */\r
- " \n"\r
- " .align 4 \n"\r
- "pxCurrentTCBConst2: .word pxCurrentTCB \n"\r
- "xSecureContextConst2: .word xSecureContext \n"\r
- #if( configENABLE_MPU == 1 )\r
- "xMAIR0Const2: .word 0xe000edc0 \n"\r
- "xRNRConst2: .word 0xe000ed98 \n"\r
- "xRBARConst2: .word 0xe000ed9c \n"\r
- #endif /* configENABLE_MPU */\r
- );\r
+ __asm volatile\r
+ (\r
+ " .syntax unified \n"\r
+ " \n"\r
+ " ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ " ldr r3, [r2] \n" /* Read pxCurrentTCB. */\r
+ " ldr r0, [r3] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
+ " ldr r4, [r3] \n" /* r4 = *r3 i.e. r4 = MAIR0. */\r
+ " ldr r2, xMAIR0Const2 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ " str r4, [r2] \n" /* Program MAIR0. */\r
+ " ldr r2, xRNRConst2 \n" /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ " movs r4, #4 \n" /* r4 = 4. */\r
+ " str r4, [r2] \n" /* Program RNR = 4. */\r
+ " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\r
+ " ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */\r
+ " ldmia r3!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */\r
+ " stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " ldm r0!, {r1-r4} \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */\r
+ " ldr r5, xSecureContextConst2 \n"\r
+ " str r1, [r5] \n" /* Set xSecureContext to this task's value for the same. */\r
+ " msr psplim, r2 \n" /* Set this task's PSPLIM value. */\r
+ " msr control, r3 \n" /* Set this task's CONTROL value. */\r
+ " adds r0, #32 \n" /* Discard everything up to r0. */\r
+ " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */\r
+ " isb \n"\r
+ " bx r4 \n" /* Finally, branch to EXC_RETURN. */\r
+ #else /* configENABLE_MPU */\r
+ " ldm r0!, {r1-r3} \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */\r
+ " ldr r4, xSecureContextConst2 \n"\r
+ " str r1, [r4] \n" /* Set xSecureContext to this task's value for the same. */\r
+ " msr psplim, r2 \n" /* Set this task's PSPLIM value. */\r
+ " movs r1, #2 \n" /* r1 = 2. */\r
+ " msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */\r
+ " adds r0, #32 \n" /* Discard everything up to r0. */\r
+ " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */\r
+ " isb \n"\r
+ " bx r3 \n" /* Finally, branch to EXC_RETURN. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ " .align 4 \n"\r
+ "pxCurrentTCBConst2: .word pxCurrentTCB \n"\r
+ "xSecureContextConst2: .word xSecureContext \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ "xMAIR0Const2: .word 0xe000edc0 \n"\r
+ "xRNRConst2: .word 0xe000ed98 \n"\r
+ "xRBARConst2: .word 0xe000ed9c \n"\r
+ #endif /* configENABLE_MPU */\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
\r
BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */\r
{\r
- __asm volatile\r
- (\r
- " mrs r0, control \n" /* r0 = CONTROL. */\r
- " tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\r
- " ite ne \n"\r
- " movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
- " moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\r
- " bx lr \n" /* Return. */\r
- " \n"\r
- " .align 4 \n"\r
- ::: "r0", "memory"\r
- );\r
+ __asm volatile\r
+ (\r
+ " mrs r0, control \n" /* r0 = CONTROL. */\r
+ " tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\r
+ " ite ne \n"\r
+ " movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
+ " moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\r
+ " bx lr \n" /* Return. */\r
+ " \n"\r
+ " .align 4 \n"\r
+ ::: "r0", "memory"\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
{\r
- __asm volatile\r
- (\r
- " mrs r0, control \n" /* Read the CONTROL register. */\r
- " bic r0, #1 \n" /* Clear the bit 0. */\r
- " msr control, r0 \n" /* Write back the new CONTROL value. */\r
- " bx lr \n" /* Return to the caller. */\r
- ::: "r0", "memory"\r
- );\r
+ __asm volatile\r
+ (\r
+ " mrs r0, control \n" /* Read the CONTROL register. */\r
+ " bic r0, #1 \n" /* Clear the bit 0. */\r
+ " msr control, r0 \n" /* Write back the new CONTROL value. */\r
+ " bx lr \n" /* Return to the caller. */\r
+ ::: "r0", "memory"\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vResetPrivilege( void ) /* __attribute__ (( naked )) */\r
{\r
- __asm volatile\r
- (\r
- " mrs r0, control \n" /* r0 = CONTROL. */\r
- " orr r0, #1 \n" /* r0 = r0 | 1. */\r
- " msr control, r0 \n" /* CONTROL = r0. */\r
- " bx lr \n" /* Return to the caller. */\r
- :::"r0", "memory"\r
- );\r
+ __asm volatile\r
+ (\r
+ " mrs r0, control \n" /* r0 = CONTROL. */\r
+ " orr r0, #1 \n" /* r0 = r0 | 1. */\r
+ " msr control, r0 \n" /* CONTROL = r0. */\r
+ " bx lr \n" /* Return to the caller. */\r
+ :::"r0", "memory"\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
{\r
- __asm volatile\r
- (\r
- " ldr r0, xVTORConst \n" /* Use the NVIC offset register to locate the stack. */\r
- " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */\r
- " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */\r
- " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */\r
- " cpsie i \n" /* Globally enable interrupts. */\r
- " cpsie f \n"\r
- " dsb \n"\r
- " isb \n"\r
- " svc %0 \n" /* System call to start the first task. */\r
- " nop \n"\r
- " \n"\r
- " .align 4 \n"\r
- "xVTORConst: .word 0xe000ed08 \n"\r
- :: "i" ( portSVC_START_SCHEDULER ) : "memory"\r
- );\r
+ __asm volatile\r
+ (\r
+ " ldr r0, xVTORConst \n" /* Use the NVIC offset register to locate the stack. */\r
+ " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */\r
+ " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */\r
+ " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */\r
+ " cpsie i \n" /* Globally enable interrupts. */\r
+ " cpsie f \n"\r
+ " dsb \n"\r
+ " isb \n"\r
+ " svc %0 \n" /* System call to start the first task. */\r
+ " nop \n"\r
+ " \n"\r
+ " .align 4 \n"\r
+ "xVTORConst: .word 0xe000ed08 \n"\r
+ :: "i" ( portSVC_START_SCHEDULER ) : "memory"\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
\r
uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
{\r
- __asm volatile\r
- (\r
- " mrs r0, PRIMASK \n"\r
- " cpsid i \n"\r
- " bx lr \n"\r
- ::: "memory"\r
- );\r
+ __asm volatile\r
+ (\r
+ " mrs r0, PRIMASK \n"\r
+ " cpsid i \n"\r
+ " bx lr \n"\r
+ ::: "memory"\r
+ );\r
\r
#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- /* To avoid compiler warnings. The return statement will never be reached,\r
- * but some compilers warn if it is not included, while others won't compile\r
- * if it is. */\r
- return 0;\r
+ /* To avoid compiler warnings. The return statement will never be reached,\r
+ * but some compilers warn if it is not included, while others won't compile\r
+ * if it is. */\r
+ return 0;\r
#endif\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
{\r
- __asm volatile\r
- (\r
- " msr PRIMASK, r0 \n"\r
- " bx lr \n"\r
- ::: "memory"\r
- );\r
+ __asm volatile\r
+ (\r
+ " msr PRIMASK, r0 \n"\r
+ " bx lr \n"\r
+ ::: "memory"\r
+ );\r
\r
#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- /* Just to avoid compiler warning. ulMask is used from the asm code but\r
- * the compiler can't see that. Some compilers generate warnings without\r
- * the following line, while others generate warnings if the line is\r
- * included. */\r
- ( void ) ulMask;\r
+ /* Just to avoid compiler warning. ulMask is used from the asm code but\r
+ * the compiler can't see that. Some compilers generate warnings without\r
+ * the following line, while others generate warnings if the line is\r
+ * included. */\r
+ ( void ) ulMask;\r
#endif\r
}\r
/*-----------------------------------------------------------*/\r
\r
void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
{\r
- __asm volatile\r
- (\r
- " .syntax unified \n"\r
- " .extern SecureContext_SaveContext \n"\r
- " .extern SecureContext_LoadContext \n"\r
- " \n"\r
- " mrs r1, psp \n" /* Read PSP in r1. */\r
- " ldr r2, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
- " ldr r0, [r2] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */\r
- " \n"\r
- " cbz r0, save_ns_context \n" /* No secure context to save. */\r
- " push {r0-r2, r14} \n"\r
- " bl SecureContext_SaveContext \n"\r
- " pop {r0-r3} \n" /* LR is now in r3. */\r
- " mov lr, r3 \n" /* LR = r3. */\r
- " lsls r2, r3, #25 \n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
- " bpl save_ns_context \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
- " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
- " ldr r2, [r3] \n" /* Read pxCurrentTCB. */\r
- #if( configENABLE_MPU == 1 )\r
- " subs r1, r1, #16 \n" /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
- " str r1, [r2] \n" /* Save the new top of stack in TCB. */\r
- " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
- " mrs r3, control \n" /* r3 = CONTROL. */\r
- " mov r4, lr \n" /* r4 = LR/EXC_RETURN. */\r
- " stmia r1!, {r0, r2-r4} \n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
- #else /* configENABLE_MPU */\r
- " subs r1, r1, #12 \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */\r
- " str r1, [r2] \n" /* Save the new top of stack in TCB. */\r
- " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
- " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */\r
- " stmia r1!, {r0, r2-r3} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */\r
- #endif /* configENABLE_MPU */\r
- " b select_next_task \n"\r
- " \n"\r
- " save_ns_context: \n"\r
- " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
- " ldr r2, [r3] \n" /* Read pxCurrentTCB. */\r
- #if( configENABLE_FPU == 1 )\r
- " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
- " it eq \n"\r
- " vstmdbeq r1!, {s16-s31} \n" /* Store the FPU registers which are not saved automatically. */\r
- #endif /* configENABLE_FPU */\r
- #if( configENABLE_MPU == 1 )\r
- " subs r1, r1, #48 \n" /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */\r
- " str r1, [r2] \n" /* Save the new top of stack in TCB. */\r
- " adds r1, r1, #16 \n" /* r1 = r1 + 16. */\r
- " stm r1, {r4-r11} \n" /* Store the registers that are not saved automatically. */\r
- " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
- " mrs r3, control \n" /* r3 = CONTROL. */\r
- " mov r4, lr \n" /* r4 = LR/EXC_RETURN. */\r
- " subs r1, r1, #16 \n" /* r1 = r1 - 16. */\r
- " stm r1, {r0, r2-r4} \n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
- #else /* configENABLE_MPU */\r
- " subs r1, r1, #44 \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */\r
- " str r1, [r2] \n" /* Save the new top of stack in TCB. */\r
- " adds r1, r1, #12 \n" /* r1 = r1 + 12. */\r
- " stm r1, {r4-r11} \n" /* Store the registers that are not saved automatically. */\r
- " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
- " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */\r
- " subs r1, r1, #12 \n" /* r1 = r1 - 12. */\r
- " stmia r1!, {r0, r2-r3} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */\r
- #endif /* configENABLE_MPU */\r
- " \n"\r
- " select_next_task: \n"\r
- " cpsid i \n"\r
- " bl vTaskSwitchContext \n"\r
- " cpsie i \n"\r
- " \n"\r
- " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
- " ldr r3, [r2] \n" /* Read pxCurrentTCB. */\r
- " ldr r1, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */\r
- " \n"\r
- #if( configENABLE_MPU == 1 )\r
- " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
- " ldr r4, [r3] \n" /* r4 = *r3 i.e. r4 = MAIR0. */\r
- " ldr r2, xMAIR0Const \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
- " str r4, [r2] \n" /* Program MAIR0. */\r
- " ldr r2, xRNRConst \n" /* r2 = 0xe000ed98 [Location of RNR]. */\r
- " movs r4, #4 \n" /* r4 = 4. */\r
- " str r4, [r2] \n" /* Program RNR = 4. */\r
- " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\r
- " ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */\r
- " ldmia r3!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
- " stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
- #endif /* configENABLE_MPU */\r
- " \n"\r
- #if( configENABLE_MPU == 1 )\r
- " ldmia r1!, {r0, r2-r4} \n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */\r
- " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */\r
- " msr control, r3 \n" /* Restore the CONTROL register value for the task. */\r
- " mov lr, r4 \n" /* LR = r4. */\r
- " ldr r2, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
- " str r0, [r2] \n" /* Restore the task's xSecureContext. */\r
- " cbz r0, restore_ns_context \n" /* If there is no secure context for the task, restore the non-secure context. */\r
- " push {r1,r4} \n"\r
- " bl SecureContext_LoadContext \n" /* Restore the secure context. */\r
- " pop {r1,r4} \n"\r
- " mov lr, r4 \n" /* LR = r4. */\r
- " lsls r2, r4, #25 \n" /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
- " bpl restore_ns_context \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
- " msr psp, r1 \n" /* Remember the new top of stack for the task. */\r
- " bx lr \n"\r
- #else /* configENABLE_MPU */\r
- " ldmia r1!, {r0, r2-r3} \n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */\r
- " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */\r
- " mov lr, r3 \n" /* LR = r3. */\r
- " ldr r2, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
- " str r0, [r2] \n" /* Restore the task's xSecureContext. */\r
- " cbz r0, restore_ns_context \n" /* If there is no secure context for the task, restore the non-secure context. */\r
- " push {r1,r3} \n"\r
- " bl SecureContext_LoadContext \n" /* Restore the secure context. */\r
- " pop {r1,r3} \n"\r
- " mov lr, r3 \n" /* LR = r3. */\r
- " lsls r2, r3, #25 \n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
- " bpl restore_ns_context \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
- " msr psp, r1 \n" /* Remember the new top of stack for the task. */\r
- " bx lr \n"\r
- #endif /* configENABLE_MPU */\r
- " \n"\r
- " restore_ns_context: \n"\r
- " ldmia r1!, {r4-r11} \n" /* Restore the registers that are not automatically restored. */\r
- #if( configENABLE_FPU == 1 )\r
- " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
- " it eq \n"\r
- " vldmiaeq r1!, {s16-s31} \n" /* Restore the FPU registers which are not restored automatically. */\r
- #endif /* configENABLE_FPU */\r
- " msr psp, r1 \n" /* Remember the new top of stack for the task. */\r
- " bx lr \n"\r
- " \n"\r
- " .align 4 \n"\r
- "pxCurrentTCBConst: .word pxCurrentTCB \n"\r
- "xSecureContextConst: .word xSecureContext \n"\r
- #if( configENABLE_MPU == 1 )\r
- "xMAIR0Const: .word 0xe000edc0 \n"\r
- "xRNRConst: .word 0xe000ed98 \n"\r
- "xRBARConst: .word 0xe000ed9c \n"\r
- #endif /* configENABLE_MPU */\r
- );\r
+ __asm volatile\r
+ (\r
+ " .syntax unified \n"\r
+ " .extern SecureContext_SaveContext \n"\r
+ " .extern SecureContext_LoadContext \n"\r
+ " \n"\r
+ " mrs r1, psp \n" /* Read PSP in r1. */\r
+ " ldr r2, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
+ " ldr r0, [r2] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */\r
+ " \n"\r
+ " cbz r0, save_ns_context \n" /* No secure context to save. */\r
+ " push {r0-r2, r14} \n"\r
+ " bl SecureContext_SaveContext \n"\r
+ " pop {r0-r3} \n" /* LR is now in r3. */\r
+ " mov lr, r3 \n" /* LR = r3. */\r
+ " lsls r2, r3, #25 \n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
+ " bpl save_ns_context \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
+ " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ " ldr r2, [r3] \n" /* Read pxCurrentTCB. */\r
+ #if( configENABLE_MPU == 1 )\r
+ " subs r1, r1, #16 \n" /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
+ " str r1, [r2] \n" /* Save the new top of stack in TCB. */\r
+ " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
+ " mrs r3, control \n" /* r3 = CONTROL. */\r
+ " mov r4, lr \n" /* r4 = LR/EXC_RETURN. */\r
+ " stmia r1!, {r0, r2-r4} \n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
+ #else /* configENABLE_MPU */\r
+ " subs r1, r1, #12 \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */\r
+ " str r1, [r2] \n" /* Save the new top of stack in TCB. */\r
+ " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
+ " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */\r
+ " stmia r1!, {r0, r2-r3} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */\r
+ #endif /* configENABLE_MPU */\r
+ " b select_next_task \n"\r
+ " \n"\r
+ " save_ns_context: \n"\r
+ " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ " ldr r2, [r3] \n" /* Read pxCurrentTCB. */\r
+ #if( configENABLE_FPU == 1 )\r
+ " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
+ " it eq \n"\r
+ " vstmdbeq r1!, {s16-s31} \n" /* Store the FPU registers which are not saved automatically. */\r
+ #endif /* configENABLE_FPU */\r
+ #if( configENABLE_MPU == 1 )\r
+ " subs r1, r1, #48 \n" /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */\r
+ " str r1, [r2] \n" /* Save the new top of stack in TCB. */\r
+ " adds r1, r1, #16 \n" /* r1 = r1 + 16. */\r
+ " stm r1, {r4-r11} \n" /* Store the registers that are not saved automatically. */\r
+ " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
+ " mrs r3, control \n" /* r3 = CONTROL. */\r
+ " mov r4, lr \n" /* r4 = LR/EXC_RETURN. */\r
+ " subs r1, r1, #16 \n" /* r1 = r1 - 16. */\r
+ " stm r1, {r0, r2-r4} \n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
+ #else /* configENABLE_MPU */\r
+ " subs r1, r1, #44 \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */\r
+ " str r1, [r2] \n" /* Save the new top of stack in TCB. */\r
+ " adds r1, r1, #12 \n" /* r1 = r1 + 12. */\r
+ " stm r1, {r4-r11} \n" /* Store the registers that are not saved automatically. */\r
+ " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
+ " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */\r
+ " subs r1, r1, #12 \n" /* r1 = r1 - 12. */\r
+ " stmia r1!, {r0, r2-r3} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ " select_next_task: \n"\r
+ " cpsid i \n"\r
+ " bl vTaskSwitchContext \n"\r
+ " cpsie i \n"\r
+ " \n"\r
+ " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ " ldr r3, [r2] \n" /* Read pxCurrentTCB. */\r
+ " ldr r1, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
+ " ldr r4, [r3] \n" /* r4 = *r3 i.e. r4 = MAIR0. */\r
+ " ldr r2, xMAIR0Const \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ " str r4, [r2] \n" /* Program MAIR0. */\r
+ " ldr r2, xRNRConst \n" /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ " movs r4, #4 \n" /* r4 = 4. */\r
+ " str r4, [r2] \n" /* Program RNR = 4. */\r
+ " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\r
+ " ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */\r
+ " ldmia r3!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
+ " stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " ldmia r1!, {r0, r2-r4} \n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */\r
+ " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */\r
+ " msr control, r3 \n" /* Restore the CONTROL register value for the task. */\r
+ " mov lr, r4 \n" /* LR = r4. */\r
+ " ldr r2, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
+ " str r0, [r2] \n" /* Restore the task's xSecureContext. */\r
+ " cbz r0, restore_ns_context \n" /* If there is no secure context for the task, restore the non-secure context. */\r
+ " push {r1,r4} \n"\r
+ " bl SecureContext_LoadContext \n" /* Restore the secure context. */\r
+ " pop {r1,r4} \n"\r
+ " mov lr, r4 \n" /* LR = r4. */\r
+ " lsls r2, r4, #25 \n" /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
+ " bpl restore_ns_context \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
+ " msr psp, r1 \n" /* Remember the new top of stack for the task. */\r
+ " bx lr \n"\r
+ #else /* configENABLE_MPU */\r
+ " ldmia r1!, {r0, r2-r3} \n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */\r
+ " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */\r
+ " mov lr, r3 \n" /* LR = r3. */\r
+ " ldr r2, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
+ " str r0, [r2] \n" /* Restore the task's xSecureContext. */\r
+ " cbz r0, restore_ns_context \n" /* If there is no secure context for the task, restore the non-secure context. */\r
+ " push {r1,r3} \n"\r
+ " bl SecureContext_LoadContext \n" /* Restore the secure context. */\r
+ " pop {r1,r3} \n"\r
+ " mov lr, r3 \n" /* LR = r3. */\r
+ " lsls r2, r3, #25 \n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
+ " bpl restore_ns_context \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
+ " msr psp, r1 \n" /* Remember the new top of stack for the task. */\r
+ " bx lr \n"\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ " restore_ns_context: \n"\r
+ " ldmia r1!, {r4-r11} \n" /* Restore the registers that are not automatically restored. */\r
+ #if( configENABLE_FPU == 1 )\r
+ " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
+ " it eq \n"\r
+ " vldmiaeq r1!, {s16-s31} \n" /* Restore the FPU registers which are not restored automatically. */\r
+ #endif /* configENABLE_FPU */\r
+ " msr psp, r1 \n" /* Remember the new top of stack for the task. */\r
+ " bx lr \n"\r
+ " \n"\r
+ " .align 4 \n"\r
+ "pxCurrentTCBConst: .word pxCurrentTCB \n"\r
+ "xSecureContextConst: .word xSecureContext \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ "xMAIR0Const: .word 0xe000edc0 \n"\r
+ "xRNRConst: .word 0xe000ed98 \n"\r
+ "xRBARConst: .word 0xe000ed9c \n"\r
+ #endif /* configENABLE_MPU */\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
\r
void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
{\r
- __asm volatile\r
- (\r
- " tst lr, #4 \n"\r
- " ite eq \n"\r
- " mrseq r0, msp \n"\r
- " mrsne r0, psp \n"\r
- " ldr r1, svchandler_address_const \n"\r
- " bx r1 \n"\r
- " \n"\r
- " .align 4 \n"\r
- "svchandler_address_const: .word vPortSVCHandler_C \n"\r
- );\r
+ __asm volatile\r
+ (\r
+ " tst lr, #4 \n"\r
+ " ite eq \n"\r
+ " mrseq r0, msp \n"\r
+ " mrsne r0, psp \n"\r
+ " ldr r1, svchandler_address_const \n"\r
+ " bx r1 \n"\r
+ " \n"\r
+ " .align 4 \n"\r
+ "svchandler_address_const: .word vPortSVCHandler_C \n"\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */\r
{\r
- __asm volatile\r
- (\r
- " svc %0 \n" /* Secure context is allocated in the supervisor call. */\r
- " bx lr \n" /* Return. */\r
- :: "i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"\r
- );\r
+ __asm volatile\r
+ (\r
+ " svc %0 \n" /* Secure context is allocated in the supervisor call. */\r
+ " bx lr \n" /* Return. */\r
+ :: "i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
{\r
- __asm volatile\r
- (\r
- " ldr r1, [r0] \n" /* The first item in the TCB is the top of the stack. */\r
- " ldr r0, [r1] \n" /* The first item on the stack is the task's xSecureContext. */\r
- " cmp r0, #0 \n" /* Raise svc if task's xSecureContext is not NULL. */\r
- " it ne \n"\r
- " svcne %0 \n" /* Secure context is freed in the supervisor call. */\r
- " bx lr \n" /* Return. */\r
- :: "i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"\r
- );\r
+ __asm volatile\r
+ (\r
+ " ldr r1, [r0] \n" /* The first item in the TCB is the top of the stack. */\r
+ " ldr r0, [r1] \n" /* The first item on the stack is the task's xSecureContext. */\r
+ " cmp r0, #0 \n" /* Raise svc if task's xSecureContext is not NULL. */\r
+ " it ne \n"\r
+ " svcne %0 \n" /* Secure context is freed in the supervisor call. */\r
+ " bx lr \n" /* Return. */\r
+ :: "i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
{\r
- __asm volatile\r
- (\r
- " .syntax unified \n"\r
- " \n"\r
- " ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
- " ldr r1, [r2] \n" /* Read pxCurrentTCB. */\r
- " ldr r0, [r1] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
- " \n"\r
- #if( configENABLE_MPU == 1 )\r
- " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
- " ldr r3, [r1] \n" /* r3 = *r1 i.e. r3 = MAIR0. */\r
- " ldr r2, xMAIR0Const2 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
- " str r3, [r2] \n" /* Program MAIR0. */\r
- " ldr r2, xRNRConst2 \n" /* r2 = 0xe000ed98 [Location of RNR]. */\r
- " movs r3, #4 \n" /* r3 = 4. */\r
- " str r3, [r2] \n" /* Program RNR = 4. */\r
- " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
- " ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */\r
- " ldmia r1!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */\r
- " stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
- #endif /* configENABLE_MPU */\r
- " \n"\r
- #if( configENABLE_MPU == 1 )\r
- " ldm r0!, {r1-r3} \n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */\r
- " msr psplim, r1 \n" /* Set this task's PSPLIM value. */\r
- " msr control, r2 \n" /* Set this task's CONTROL value. */\r
- " adds r0, #32 \n" /* Discard everything up to r0. */\r
- " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */\r
- " isb \n"\r
- " bx r3 \n" /* Finally, branch to EXC_RETURN. */\r
- #else /* configENABLE_MPU */\r
- " ldm r0!, {r1-r2} \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */\r
- " msr psplim, r1 \n" /* Set this task's PSPLIM value. */\r
- " movs r1, #2 \n" /* r1 = 2. */\r
- " msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */\r
- " adds r0, #32 \n" /* Discard everything up to r0. */\r
- " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */\r
- " isb \n"\r
- " bx r2 \n" /* Finally, branch to EXC_RETURN. */\r
- #endif /* configENABLE_MPU */\r
- " \n"\r
- " .align 4 \n"\r
- "pxCurrentTCBConst2: .word pxCurrentTCB \n"\r
- #if( configENABLE_MPU == 1 )\r
- "xMAIR0Const2: .word 0xe000edc0 \n"\r
- "xRNRConst2: .word 0xe000ed98 \n"\r
- "xRBARConst2: .word 0xe000ed9c \n"\r
- #endif /* configENABLE_MPU */\r
- );\r
+ __asm volatile\r
+ (\r
+ " .syntax unified \n"\r
+ " \n"\r
+ " ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */\r
+ " ldr r0, [r1] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
+ " ldr r3, [r1] \n" /* r3 = *r1 i.e. r3 = MAIR0. */\r
+ " ldr r2, xMAIR0Const2 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ " str r3, [r2] \n" /* Program MAIR0. */\r
+ " ldr r2, xRNRConst2 \n" /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ " movs r3, #4 \n" /* r3 = 4. */\r
+ " str r3, [r2] \n" /* Program RNR = 4. */\r
+ " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
+ " ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */\r
+ " ldmia r1!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */\r
+ " stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " ldm r0!, {r1-r3} \n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */\r
+ " msr psplim, r1 \n" /* Set this task's PSPLIM value. */\r
+ " msr control, r2 \n" /* Set this task's CONTROL value. */\r
+ " adds r0, #32 \n" /* Discard everything up to r0. */\r
+ " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */\r
+ " isb \n"\r
+ " bx r3 \n" /* Finally, branch to EXC_RETURN. */\r
+ #else /* configENABLE_MPU */\r
+ " ldm r0!, {r1-r2} \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */\r
+ " msr psplim, r1 \n" /* Set this task's PSPLIM value. */\r
+ " movs r1, #2 \n" /* r1 = 2. */\r
+ " msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */\r
+ " adds r0, #32 \n" /* Discard everything up to r0. */\r
+ " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */\r
+ " isb \n"\r
+ " bx r2 \n" /* Finally, branch to EXC_RETURN. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ " .align 4 \n"\r
+ "pxCurrentTCBConst2: .word pxCurrentTCB \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ "xMAIR0Const2: .word 0xe000edc0 \n"\r
+ "xRNRConst2: .word 0xe000ed98 \n"\r
+ "xRBARConst2: .word 0xe000ed9c \n"\r
+ #endif /* configENABLE_MPU */\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
\r
BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */\r
{\r
- __asm volatile\r
- (\r
- " mrs r0, control \n" /* r0 = CONTROL. */\r
- " tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\r
- " ite ne \n"\r
- " movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
- " moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\r
- " bx lr \n" /* Return. */\r
- " \n"\r
- " .align 4 \n"\r
- ::: "r0", "memory"\r
- );\r
+ __asm volatile\r
+ (\r
+ " mrs r0, control \n" /* r0 = CONTROL. */\r
+ " tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\r
+ " ite ne \n"\r
+ " movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
+ " moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\r
+ " bx lr \n" /* Return. */\r
+ " \n"\r
+ " .align 4 \n"\r
+ ::: "r0", "memory"\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
{\r
- __asm volatile\r
- (\r
- " mrs r0, control \n" /* Read the CONTROL register. */\r
- " bic r0, #1 \n" /* Clear the bit 0. */\r
- " msr control, r0 \n" /* Write back the new CONTROL value. */\r
- " bx lr \n" /* Return to the caller. */\r
- ::: "r0", "memory"\r
- );\r
+ __asm volatile\r
+ (\r
+ " mrs r0, control \n" /* Read the CONTROL register. */\r
+ " bic r0, #1 \n" /* Clear the bit 0. */\r
+ " msr control, r0 \n" /* Write back the new CONTROL value. */\r
+ " bx lr \n" /* Return to the caller. */\r
+ ::: "r0", "memory"\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vResetPrivilege( void ) /* __attribute__ (( naked )) */\r
{\r
- __asm volatile\r
- (\r
- " mrs r0, control \n" /* r0 = CONTROL. */\r
- " orr r0, #1 \n" /* r0 = r0 | 1. */\r
- " msr control, r0 \n" /* CONTROL = r0. */\r
- " bx lr \n" /* Return to the caller. */\r
- :::"r0", "memory"\r
- );\r
+ __asm volatile\r
+ (\r
+ " mrs r0, control \n" /* r0 = CONTROL. */\r
+ " orr r0, #1 \n" /* r0 = r0 | 1. */\r
+ " msr control, r0 \n" /* CONTROL = r0. */\r
+ " bx lr \n" /* Return to the caller. */\r
+ :::"r0", "memory"\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
{\r
- __asm volatile\r
- (\r
- " ldr r0, xVTORConst \n" /* Use the NVIC offset register to locate the stack. */\r
- " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */\r
- " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */\r
- " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */\r
- " cpsie i \n" /* Globally enable interrupts. */\r
- " cpsie f \n"\r
- " dsb \n"\r
- " isb \n"\r
- " svc %0 \n" /* System call to start the first task. */\r
- " nop \n"\r
- " \n"\r
- " .align 4 \n"\r
- "xVTORConst: .word 0xe000ed08 \n"\r
- :: "i" ( portSVC_START_SCHEDULER ) : "memory"\r
- );\r
+ __asm volatile\r
+ (\r
+ " ldr r0, xVTORConst \n" /* Use the NVIC offset register to locate the stack. */\r
+ " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */\r
+ " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */\r
+ " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */\r
+ " cpsie i \n" /* Globally enable interrupts. */\r
+ " cpsie f \n"\r
+ " dsb \n"\r
+ " isb \n"\r
+ " svc %0 \n" /* System call to start the first task. */\r
+ " nop \n"\r
+ " \n"\r
+ " .align 4 \n"\r
+ "xVTORConst: .word 0xe000ed08 \n"\r
+ :: "i" ( portSVC_START_SCHEDULER ) : "memory"\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
\r
uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
{\r
- __asm volatile\r
- (\r
- " mrs r0, PRIMASK \n"\r
- " cpsid i \n"\r
- " bx lr \n"\r
- ::: "memory"\r
- );\r
+ __asm volatile\r
+ (\r
+ " mrs r0, PRIMASK \n"\r
+ " cpsid i \n"\r
+ " bx lr \n"\r
+ ::: "memory"\r
+ );\r
\r
#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- /* To avoid compiler warnings. The return statement will never be reached,\r
- * but some compilers warn if it is not included, while others won't compile\r
- * if it is. */\r
- return 0;\r
+ /* To avoid compiler warnings. The return statement will never be reached,\r
+ * but some compilers warn if it is not included, while others won't compile\r
+ * if it is. */\r
+ return 0;\r
#endif\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
{\r
- __asm volatile\r
- (\r
- " msr PRIMASK, r0 \n"\r
- " bx lr \n"\r
- ::: "memory"\r
- );\r
+ __asm volatile\r
+ (\r
+ " msr PRIMASK, r0 \n"\r
+ " bx lr \n"\r
+ ::: "memory"\r
+ );\r
\r
#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- /* Just to avoid compiler warning. ulMask is used from the asm code but\r
- * the compiler can't see that. Some compilers generate warnings without\r
- * the following line, while others generate warnings if the line is\r
- * included. */\r
- ( void ) ulMask;\r
+ /* Just to avoid compiler warning. ulMask is used from the asm code but\r
+ * the compiler can't see that. Some compilers generate warnings without\r
+ * the following line, while others generate warnings if the line is\r
+ * included. */\r
+ ( void ) ulMask;\r
#endif\r
}\r
/*-----------------------------------------------------------*/\r
\r
void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
{\r
- __asm volatile\r
- (\r
- " .syntax unified \n"\r
- " \n"\r
- " mrs r0, psp \n" /* Read PSP in r0. */\r
- #if( configENABLE_FPU == 1 )\r
- " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
- " it eq \n"\r
- " vstmdbeq r0!, {s16-s31} \n" /* Store the FPU registers which are not saved automatically. */\r
- #endif /* configENABLE_FPU */\r
- #if( configENABLE_MPU == 1 )\r
- " mrs r1, psplim \n" /* r1 = PSPLIM. */\r
- " mrs r2, control \n" /* r2 = CONTROL. */\r
- " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */\r
- " stmdb r0!, {r1-r11} \n" /* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */\r
- #else /* configENABLE_MPU */\r
- " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
- " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */\r
- " stmdb r0!, {r2-r11} \n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */\r
- #endif /* configENABLE_MPU */\r
- " \n"\r
- " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
- " ldr r1, [r2] \n" /* Read pxCurrentTCB. */\r
- " str r0, [r1] \n" /* Save the new top of stack in TCB. */\r
- " \n"\r
- " cpsid i \n"\r
- " bl vTaskSwitchContext \n"\r
- " cpsie i \n"\r
- " \n"\r
- " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
- " ldr r1, [r2] \n" /* Read pxCurrentTCB. */\r
- " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */\r
- " \n"\r
- #if( configENABLE_MPU == 1 )\r
- " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
- " ldr r3, [r1] \n" /* r3 = *r1 i.e. r3 = MAIR0. */\r
- " ldr r2, xMAIR0Const \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
- " str r3, [r2] \n" /* Program MAIR0. */\r
- " ldr r2, xRNRConst \n" /* r2 = 0xe000ed98 [Location of RNR]. */\r
- " movs r3, #4 \n" /* r3 = 4. */\r
- " str r3, [r2] \n" /* Program RNR = 4. */\r
- " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
- " ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */\r
- " ldmia r1!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
- " stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
- #endif /* configENABLE_MPU */\r
- " \n"\r
- #if( configENABLE_MPU == 1 )\r
- " ldmia r0!, {r1-r11} \n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */\r
- #else /* configENABLE_MPU */\r
- " ldmia r0!, {r2-r11} \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */\r
- #endif /* configENABLE_MPU */\r
- " \n"\r
- #if( configENABLE_FPU == 1 )\r
- " tst r3, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
- " it eq \n"\r
- " vldmiaeq r0!, {s16-s31} \n" /* Restore the FPU registers which are not restored automatically. */\r
- #endif /* configENABLE_FPU */\r
- " \n"\r
- #if( configENABLE_MPU == 1 )\r
- " msr psplim, r1 \n" /* Restore the PSPLIM register value for the task. */\r
- " msr control, r2 \n" /* Restore the CONTROL register value for the task. */\r
- #else /* configENABLE_MPU */\r
- " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */\r
- #endif /* configENABLE_MPU */\r
- " msr psp, r0 \n" /* Remember the new top of stack for the task. */\r
- " bx r3 \n"\r
- " \n"\r
- " .align 4 \n"\r
- "pxCurrentTCBConst: .word pxCurrentTCB \n"\r
- "xMAIR0Const: .word 0xe000edc0 \n"\r
- "xRNRConst: .word 0xe000ed98 \n"\r
- "xRBARConst: .word 0xe000ed9c \n"\r
- );\r
+ __asm volatile\r
+ (\r
+ " .syntax unified \n"\r
+ " \n"\r
+ " mrs r0, psp \n" /* Read PSP in r0. */\r
+ #if( configENABLE_FPU == 1 )\r
+ " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
+ " it eq \n"\r
+ " vstmdbeq r0!, {s16-s31} \n" /* Store the FPU registers which are not saved automatically. */\r
+ #endif /* configENABLE_FPU */\r
+ #if( configENABLE_MPU == 1 )\r
+ " mrs r1, psplim \n" /* r1 = PSPLIM. */\r
+ " mrs r2, control \n" /* r2 = CONTROL. */\r
+ " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */\r
+ " stmdb r0!, {r1-r11} \n" /* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */\r
+ #else /* configENABLE_MPU */\r
+ " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
+ " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */\r
+ " stmdb r0!, {r2-r11} \n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */\r
+ " str r0, [r1] \n" /* Save the new top of stack in TCB. */\r
+ " \n"\r
+ " cpsid i \n"\r
+ " bl vTaskSwitchContext \n"\r
+ " cpsie i \n"\r
+ " \n"\r
+ " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */\r
+ " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
+ " ldr r3, [r1] \n" /* r3 = *r1 i.e. r3 = MAIR0. */\r
+ " ldr r2, xMAIR0Const \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ " str r3, [r2] \n" /* Program MAIR0. */\r
+ " ldr r2, xRNRConst \n" /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ " movs r3, #4 \n" /* r3 = 4. */\r
+ " str r3, [r2] \n" /* Program RNR = 4. */\r
+ " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
+ " ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */\r
+ " ldmia r1!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
+ " stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " ldmia r0!, {r1-r11} \n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */\r
+ #else /* configENABLE_MPU */\r
+ " ldmia r0!, {r2-r11} \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ #if( configENABLE_FPU == 1 )\r
+ " tst r3, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
+ " it eq \n"\r
+ " vldmiaeq r0!, {s16-s31} \n" /* Restore the FPU registers which are not restored automatically. */\r
+ #endif /* configENABLE_FPU */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " msr psplim, r1 \n" /* Restore the PSPLIM register value for the task. */\r
+ " msr control, r2 \n" /* Restore the CONTROL register value for the task. */\r
+ #else /* configENABLE_MPU */\r
+ " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */\r
+ #endif /* configENABLE_MPU */\r
+ " msr psp, r0 \n" /* Remember the new top of stack for the task. */\r
+ " bx r3 \n"\r
+ " \n"\r
+ " .align 4 \n"\r
+ "pxCurrentTCBConst: .word pxCurrentTCB \n"\r
+ "xMAIR0Const: .word 0xe000edc0 \n"\r
+ "xRNRConst: .word 0xe000ed98 \n"\r
+ "xRBARConst: .word 0xe000ed9c \n"\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
\r
void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
{\r
- __asm volatile\r
- (\r
- " tst lr, #4 \n"\r
- " ite eq \n"\r
- " mrseq r0, msp \n"\r
- " mrsne r0, psp \n"\r
- " ldr r1, svchandler_address_const \n"\r
- " bx r1 \n"\r
- " \n"\r
- " .align 4 \n"\r
- "svchandler_address_const: .word vPortSVCHandler_C \n"\r
- );\r
+ __asm volatile\r
+ (\r
+ " tst lr, #4 \n"\r
+ " ite eq \n"\r
+ " mrseq r0, msp \n"\r
+ " mrsne r0, psp \n"\r
+ " ldr r1, svchandler_address_const \n"\r
+ " bx r1 \n"\r
+ " \n"\r
+ " .align 4 \n"\r
+ "svchandler_address_const: .word vPortSVCHandler_C \n"\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
* 1 tab == 4 spaces!\r
*/\r
\r
- EXTERN pxCurrentTCB\r
- EXTERN xSecureContext\r
- EXTERN vTaskSwitchContext\r
- EXTERN vPortSVCHandler_C\r
- EXTERN SecureContext_SaveContext\r
- EXTERN SecureContext_LoadContext\r
+ EXTERN pxCurrentTCB\r
+ EXTERN xSecureContext\r
+ EXTERN vTaskSwitchContext\r
+ EXTERN vPortSVCHandler_C\r
+ EXTERN SecureContext_SaveContext\r
+ EXTERN SecureContext_LoadContext\r
\r
- PUBLIC xIsPrivileged\r
- PUBLIC vResetPrivilege\r
- PUBLIC vPortAllocateSecureContext\r
- PUBLIC vRestoreContextOfFirstTask\r
- PUBLIC vRaisePrivilege\r
- PUBLIC vStartFirstTask\r
- PUBLIC ulSetInterruptMaskFromISR\r
- PUBLIC vClearInterruptMaskFromISR\r
- PUBLIC PendSV_Handler\r
- PUBLIC SVC_Handler\r
- PUBLIC vPortFreeSecureContext\r
+ PUBLIC xIsPrivileged\r
+ PUBLIC vResetPrivilege\r
+ PUBLIC vPortAllocateSecureContext\r
+ PUBLIC vRestoreContextOfFirstTask\r
+ PUBLIC vRaisePrivilege\r
+ PUBLIC vStartFirstTask\r
+ PUBLIC ulSetInterruptMaskFromISR\r
+ PUBLIC vClearInterruptMaskFromISR\r
+ PUBLIC PendSV_Handler\r
+ PUBLIC SVC_Handler\r
+ PUBLIC vPortFreeSecureContext\r
/*-----------------------------------------------------------*/\r
\r
/*---------------- Unprivileged Functions -------------------*/\r
\r
/*-----------------------------------------------------------*/\r
\r
- SECTION .text:CODE:NOROOT(2)\r
- THUMB\r
+ SECTION .text:CODE:NOROOT(2)\r
+ THUMB\r
/*-----------------------------------------------------------*/\r
\r
xIsPrivileged:\r
- mrs r0, control /* r0 = CONTROL. */\r
- tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\r
- ite ne\r
- movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
- moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */\r
- bx lr /* Return. */\r
+ mrs r0, control /* r0 = CONTROL. */\r
+ tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\r
+ ite ne\r
+ movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
+ moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */\r
+ bx lr /* Return. */\r
/*-----------------------------------------------------------*/\r
\r
vResetPrivilege:\r
- mrs r0, control /* r0 = CONTROL. */\r
- orr r0, r0, #1 /* r0 = r0 | 1. */\r
- msr control, r0 /* CONTROL = r0. */\r
- bx lr /* Return to the caller. */\r
+ mrs r0, control /* r0 = CONTROL. */\r
+ orr r0, r0, #1 /* r0 = r0 | 1. */\r
+ msr control, r0 /* CONTROL = r0. */\r
+ bx lr /* Return to the caller. */\r
/*-----------------------------------------------------------*/\r
\r
vPortAllocateSecureContext:\r
- svc 0 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */\r
- bx lr /* Return. */\r
+ svc 0 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */\r
+ bx lr /* Return. */\r
/*-----------------------------------------------------------*/\r
\r
/*----------------- Privileged Functions --------------------*/\r
\r
/*-----------------------------------------------------------*/\r
\r
- SECTION privileged_functions:CODE:NOROOT(2)\r
- THUMB\r
+ SECTION privileged_functions:CODE:NOROOT(2)\r
+ THUMB\r
/*-----------------------------------------------------------*/\r
\r
vRestoreContextOfFirstTask:\r
- ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
- ldr r3, [r2] /* Read pxCurrentTCB. */\r
- ldr r0, [r3] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ ldr r3, [r2] /* Read pxCurrentTCB. */\r
+ ldr r0, [r3] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
\r
#if ( configENABLE_MPU == 1 )\r
- adds r3, #4 /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
- ldr r4, [r3] /* r4 = *r3 i.e. r4 = MAIR0. */\r
- ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
- str r4, [r2] /* Program MAIR0. */\r
- ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */\r
- movs r4, #4 /* r4 = 4. */\r
- str r4, [r2] /* Program RNR = 4. */\r
- adds r3, #4 /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\r
- ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */\r
- ldmia r3!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */\r
- stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+ adds r3, #4 /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
+ ldr r4, [r3] /* r4 = *r3 i.e. r4 = MAIR0. */\r
+ ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ str r4, [r2] /* Program MAIR0. */\r
+ ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ movs r4, #4 /* r4 = 4. */\r
+ str r4, [r2] /* Program RNR = 4. */\r
+ adds r3, #4 /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\r
+ ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */\r
+ ldmia r3!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */\r
+ stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
#endif /* configENABLE_MPU */\r
\r
#if ( configENABLE_MPU == 1 )\r
- ldm r0!, {r1-r4} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */\r
- ldr r5, =xSecureContext\r
- str r1, [r5] /* Set xSecureContext to this task's value for the same. */\r
- msr psplim, r2 /* Set this task's PSPLIM value. */\r
- msr control, r3 /* Set this task's CONTROL value. */\r
- adds r0, #32 /* Discard everything up to r0. */\r
- msr psp, r0 /* This is now the new top of stack to use in the task. */\r
- isb\r
- bx r4 /* Finally, branch to EXC_RETURN. */\r
+ ldm r0!, {r1-r4} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */\r
+ ldr r5, =xSecureContext\r
+ str r1, [r5] /* Set xSecureContext to this task's value for the same. */\r
+ msr psplim, r2 /* Set this task's PSPLIM value. */\r
+ msr control, r3 /* Set this task's CONTROL value. */\r
+ adds r0, #32 /* Discard everything up to r0. */\r
+ msr psp, r0 /* This is now the new top of stack to use in the task. */\r
+ isb\r
+ bx r4 /* Finally, branch to EXC_RETURN. */\r
#else /* configENABLE_MPU */\r
- ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */\r
- ldr r4, =xSecureContext\r
- str r1, [r4] /* Set xSecureContext to this task's value for the same. */\r
- msr psplim, r2 /* Set this task's PSPLIM value. */\r
- movs r1, #2 /* r1 = 2. */\r
- msr CONTROL, r1 /* Switch to use PSP in the thread mode. */\r
- adds r0, #32 /* Discard everything up to r0. */\r
- msr psp, r0 /* This is now the new top of stack to use in the task. */\r
- isb\r
- bx r3 /* Finally, branch to EXC_RETURN. */\r
+ ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */\r
+ ldr r4, =xSecureContext\r
+ str r1, [r4] /* Set xSecureContext to this task's value for the same. */\r
+ msr psplim, r2 /* Set this task's PSPLIM value. */\r
+ movs r1, #2 /* r1 = 2. */\r
+ msr CONTROL, r1 /* Switch to use PSP in the thread mode. */\r
+ adds r0, #32 /* Discard everything up to r0. */\r
+ msr psp, r0 /* This is now the new top of stack to use in the task. */\r
+ isb\r
+ bx r3 /* Finally, branch to EXC_RETURN. */\r
#endif /* configENABLE_MPU */\r
/*-----------------------------------------------------------*/\r
\r
vRaisePrivilege:\r
- mrs r0, control /* Read the CONTROL register. */\r
- bic r0, r0, #1 /* Clear the bit 0. */\r
- msr control, r0 /* Write back the new CONTROL value. */\r
- bx lr /* Return to the caller. */\r
+ mrs r0, control /* Read the CONTROL register. */\r
+ bic r0, r0, #1 /* Clear the bit 0. */\r
+ msr control, r0 /* Write back the new CONTROL value. */\r
+ bx lr /* Return to the caller. */\r
/*-----------------------------------------------------------*/\r
\r
vStartFirstTask:\r
- ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */\r
- ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */\r
- ldr r0, [r0] /* The first entry in vector table is stack pointer. */\r
- msr msp, r0 /* Set the MSP back to the start of the stack. */\r
- cpsie i /* Globally enable interrupts. */\r
- cpsie f\r
- dsb\r
- isb\r
- svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */\r
+ ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */\r
+ ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */\r
+ ldr r0, [r0] /* The first entry in vector table is stack pointer. */\r
+ msr msp, r0 /* Set the MSP back to the start of the stack. */\r
+ cpsie i /* Globally enable interrupts. */\r
+ cpsie f\r
+ dsb\r
+ isb\r
+ svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */\r
/*-----------------------------------------------------------*/\r
\r
ulSetInterruptMaskFromISR:\r
- mrs r0, PRIMASK\r
- cpsid i\r
- bx lr\r
+ mrs r0, PRIMASK\r
+ cpsid i\r
+ bx lr\r
/*-----------------------------------------------------------*/\r
\r
vClearInterruptMaskFromISR:\r
- msr PRIMASK, r0\r
- bx lr\r
+ msr PRIMASK, r0\r
+ bx lr\r
/*-----------------------------------------------------------*/\r
\r
PendSV_Handler:\r
- mrs r1, psp /* Read PSP in r1. */\r
- ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
- ldr r0, [r2] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */\r
+ mrs r1, psp /* Read PSP in r1. */\r
+ ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
+ ldr r0, [r2] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */\r
\r
- cbz r0, save_ns_context /* No secure context to save. */\r
- push {r0-r2, r14}\r
- bl SecureContext_SaveContext\r
- pop {r0-r3} /* LR is now in r3. */\r
- mov lr, r3 /* LR = r3. */\r
- lsls r2, r3, #25 /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
- bpl save_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
- ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
- ldr r2, [r3] /* Read pxCurrentTCB. */\r
+ cbz r0, save_ns_context /* No secure context to save. */\r
+ push {r0-r2, r14}\r
+ bl SecureContext_SaveContext\r
+ pop {r0-r3} /* LR is now in r3. */\r
+ mov lr, r3 /* LR = r3. */\r
+ lsls r2, r3, #25 /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
+ bpl save_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
+ ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ ldr r2, [r3] /* Read pxCurrentTCB. */\r
#if ( configENABLE_MPU == 1 )\r
- subs r1, r1, #16 /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
- str r1, [r2] /* Save the new top of stack in TCB. */\r
- mrs r2, psplim /* r2 = PSPLIM. */\r
- mrs r3, control /* r3 = CONTROL. */\r
- mov r4, lr /* r4 = LR/EXC_RETURN. */\r
- stmia r1!, {r0, r2-r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
+ subs r1, r1, #16 /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
+ str r1, [r2] /* Save the new top of stack in TCB. */\r
+ mrs r2, psplim /* r2 = PSPLIM. */\r
+ mrs r3, control /* r3 = CONTROL. */\r
+ mov r4, lr /* r4 = LR/EXC_RETURN. */\r
+ stmia r1!, {r0, r2-r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
#else /* configENABLE_MPU */\r
- subs r1, r1, #12 /* Make space for xSecureContext, PSPLIM and LR on the stack. */\r
- str r1, [r2] /* Save the new top of stack in TCB. */\r
- mrs r2, psplim /* r2 = PSPLIM. */\r
- mov r3, lr /* r3 = LR/EXC_RETURN. */\r
- stmia r1!, {r0, r2-r3} /* Store xSecureContext, PSPLIM and LR on the stack. */\r
+ subs r1, r1, #12 /* Make space for xSecureContext, PSPLIM and LR on the stack. */\r
+ str r1, [r2] /* Save the new top of stack in TCB. */\r
+ mrs r2, psplim /* r2 = PSPLIM. */\r
+ mov r3, lr /* r3 = LR/EXC_RETURN. */\r
+ stmia r1!, {r0, r2-r3} /* Store xSecureContext, PSPLIM and LR on the stack. */\r
#endif /* configENABLE_MPU */\r
- b select_next_task\r
+ b select_next_task\r
\r
- save_ns_context:\r
- ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
- ldr r2, [r3] /* Read pxCurrentTCB. */\r
- #if ( configENABLE_FPU == 1 )\r
- tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
- it eq\r
- vstmdbeq r1!, {s16-s31} /* Store the FPU registers which are not saved automatically. */\r
- #endif /* configENABLE_FPU */\r
- #if ( configENABLE_MPU == 1 )\r
- subs r1, r1, #48 /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */\r
- str r1, [r2] /* Save the new top of stack in TCB. */\r
- adds r1, r1, #16 /* r1 = r1 + 16. */\r
- stm r1, {r4-r11} /* Store the registers that are not saved automatically. */\r
- mrs r2, psplim /* r2 = PSPLIM. */\r
- mrs r3, control /* r3 = CONTROL. */\r
- mov r4, lr /* r4 = LR/EXC_RETURN. */\r
- subs r1, r1, #16 /* r1 = r1 - 16. */\r
- stm r1, {r0, r2-r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
- #else /* configENABLE_MPU */\r
- subs r1, r1, #44 /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */\r
- str r1, [r2] /* Save the new top of stack in TCB. */\r
- adds r1, r1, #12 /* r1 = r1 + 12. */\r
- stm r1, {r4-r11} /* Store the registers that are not saved automatically. */\r
- mrs r2, psplim /* r2 = PSPLIM. */\r
- mov r3, lr /* r3 = LR/EXC_RETURN. */\r
- subs r1, r1, #12 /* r1 = r1 - 12. */\r
- stmia r1!, {r0, r2-r3} /* Store xSecureContext, PSPLIM and LR on the stack. */\r
- #endif /* configENABLE_MPU */\r
+ save_ns_context:\r
+ ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ ldr r2, [r3] /* Read pxCurrentTCB. */\r
+ #if ( configENABLE_FPU == 1 )\r
+ tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
+ it eq\r
+ vstmdbeq r1!, {s16-s31} /* Store the FPU registers which are not saved automatically. */\r
+ #endif /* configENABLE_FPU */\r
+ #if ( configENABLE_MPU == 1 )\r
+ subs r1, r1, #48 /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */\r
+ str r1, [r2] /* Save the new top of stack in TCB. */\r
+ adds r1, r1, #16 /* r1 = r1 + 16. */\r
+ stm r1, {r4-r11} /* Store the registers that are not saved automatically. */\r
+ mrs r2, psplim /* r2 = PSPLIM. */\r
+ mrs r3, control /* r3 = CONTROL. */\r
+ mov r4, lr /* r4 = LR/EXC_RETURN. */\r
+ subs r1, r1, #16 /* r1 = r1 - 16. */\r
+ stm r1, {r0, r2-r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
+ #else /* configENABLE_MPU */\r
+ subs r1, r1, #44 /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */\r
+ str r1, [r2] /* Save the new top of stack in TCB. */\r
+ adds r1, r1, #12 /* r1 = r1 + 12. */\r
+ stm r1, {r4-r11} /* Store the registers that are not saved automatically. */\r
+ mrs r2, psplim /* r2 = PSPLIM. */\r
+ mov r3, lr /* r3 = LR/EXC_RETURN. */\r
+ subs r1, r1, #12 /* r1 = r1 - 12. */\r
+ stmia r1!, {r0, r2-r3} /* Store xSecureContext, PSPLIM and LR on the stack. */\r
+ #endif /* configENABLE_MPU */\r
\r
- select_next_task:\r
- cpsid i\r
- bl vTaskSwitchContext\r
- cpsie i\r
+ select_next_task:\r
+ cpsid i\r
+ bl vTaskSwitchContext\r
+ cpsie i\r
\r
- ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
- ldr r3, [r2] /* Read pxCurrentTCB. */\r
- ldr r1, [r3] /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */\r
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ ldr r3, [r2] /* Read pxCurrentTCB. */\r
+ ldr r1, [r3] /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */\r
\r
- #if ( configENABLE_MPU == 1 )\r
- adds r3, #4 /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
- ldr r4, [r3] /* r4 = *r3 i.e. r4 = MAIR0. */\r
- ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
- str r4, [r2] /* Program MAIR0. */\r
- ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */\r
- movs r4, #4 /* r4 = 4. */\r
- str r4, [r2] /* Program RNR = 4. */\r
- adds r3, #4 /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\r
- ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */\r
- ldmia r3!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
- stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
- #endif /* configENABLE_MPU */\r
+ #if ( configENABLE_MPU == 1 )\r
+ adds r3, #4 /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
+ ldr r4, [r3] /* r4 = *r3 i.e. r4 = MAIR0. */\r
+ ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ str r4, [r2] /* Program MAIR0. */\r
+ ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ movs r4, #4 /* r4 = 4. */\r
+ str r4, [r2] /* Program RNR = 4. */\r
+ adds r3, #4 /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\r
+ ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */\r
+ ldmia r3!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
+ stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+ #endif /* configENABLE_MPU */\r
\r
- #if ( configENABLE_MPU == 1 )\r
- ldmia r1!, {r0, r2-r4} /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */\r
- msr psplim, r2 /* Restore the PSPLIM register value for the task. */\r
- msr control, r3 /* Restore the CONTROL register value for the task. */\r
- mov lr, r4 /* LR = r4. */\r
- ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
- str r0, [r2] /* Restore the task's xSecureContext. */\r
- cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */\r
- push {r1,r4}\r
- bl SecureContext_LoadContext /* Restore the secure context. */\r
- pop {r1,r4}\r
- mov lr, r4 /* LR = r4. */\r
- lsls r2, r4, #25 /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
- bpl restore_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
- msr psp, r1 /* Remember the new top of stack for the task. */\r
- bx lr\r
- #else /* configENABLE_MPU */\r
- ldmia r1!, {r0, r2-r3} /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */\r
- msr psplim, r2 /* Restore the PSPLIM register value for the task. */\r
- mov lr, r3 /* LR = r3. */\r
- ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
- str r0, [r2] /* Restore the task's xSecureContext. */\r
- cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */\r
- push {r1,r3}\r
- bl SecureContext_LoadContext /* Restore the secure context. */\r
- pop {r1,r3}\r
- mov lr, r3 /* LR = r3. */\r
- lsls r2, r3, #25 /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
- bpl restore_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
- msr psp, r1 /* Remember the new top of stack for the task. */\r
- bx lr\r
- #endif /* configENABLE_MPU */\r
+ #if ( configENABLE_MPU == 1 )\r
+ ldmia r1!, {r0, r2-r4} /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */\r
+ msr psplim, r2 /* Restore the PSPLIM register value for the task. */\r
+ msr control, r3 /* Restore the CONTROL register value for the task. */\r
+ mov lr, r4 /* LR = r4. */\r
+ ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
+ str r0, [r2] /* Restore the task's xSecureContext. */\r
+ cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */\r
+ push {r1,r4}\r
+ bl SecureContext_LoadContext /* Restore the secure context. */\r
+ pop {r1,r4}\r
+ mov lr, r4 /* LR = r4. */\r
+ lsls r2, r4, #25 /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
+ bpl restore_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
+ msr psp, r1 /* Remember the new top of stack for the task. */\r
+ bx lr\r
+ #else /* configENABLE_MPU */\r
+ ldmia r1!, {r0, r2-r3} /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */\r
+ msr psplim, r2 /* Restore the PSPLIM register value for the task. */\r
+ mov lr, r3 /* LR = r3. */\r
+ ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
+ str r0, [r2] /* Restore the task's xSecureContext. */\r
+ cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */\r
+ push {r1,r3}\r
+ bl SecureContext_LoadContext /* Restore the secure context. */\r
+ pop {r1,r3}\r
+ mov lr, r3 /* LR = r3. */\r
+ lsls r2, r3, #25 /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
+ bpl restore_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
+ msr psp, r1 /* Remember the new top of stack for the task. */\r
+ bx lr\r
+ #endif /* configENABLE_MPU */\r
\r
- restore_ns_context:\r
- ldmia r1!, {r4-r11} /* Restore the registers that are not automatically restored. */\r
- #if ( configENABLE_FPU == 1 )\r
- tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
- it eq\r
- vldmiaeq r1!, {s16-s31} /* Restore the FPU registers which are not restored automatically. */\r
- #endif /* configENABLE_FPU */\r
- msr psp, r1 /* Remember the new top of stack for the task. */\r
- bx lr\r
+ restore_ns_context:\r
+ ldmia r1!, {r4-r11} /* Restore the registers that are not automatically restored. */\r
+ #if ( configENABLE_FPU == 1 )\r
+ tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
+ it eq\r
+ vldmiaeq r1!, {s16-s31} /* Restore the FPU registers which are not restored automatically. */\r
+ #endif /* configENABLE_FPU */\r
+ msr psp, r1 /* Remember the new top of stack for the task. */\r
+ bx lr\r
/*-----------------------------------------------------------*/\r
\r
SVC_Handler:\r
- tst lr, #4\r
- ite eq\r
- mrseq r0, msp\r
- mrsne r0, psp\r
- b vPortSVCHandler_C\r
+ tst lr, #4\r
+ ite eq\r
+ mrseq r0, msp\r
+ mrsne r0, psp\r
+ b vPortSVCHandler_C\r
/*-----------------------------------------------------------*/\r
\r
vPortFreeSecureContext:\r
- /* r0 = uint32_t *pulTCB. */\r
- ldr r1, [r0] /* The first item in the TCB is the top of the stack. */\r
- ldr r0, [r1] /* The first item on the stack is the task's xSecureContext. */\r
- cmp r0, #0 /* Raise svc if task's xSecureContext is not NULL. */\r
- it ne\r
- svcne 1 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */\r
- bx lr /* Return. */\r
+ /* r0 = uint32_t *pulTCB. */\r
+ ldr r1, [r0] /* The first item in the TCB is the top of the stack. */\r
+ ldr r0, [r1] /* The first item on the stack is the task's xSecureContext. */\r
+ cmp r0, #0 /* Raise svc if task's xSecureContext is not NULL. */\r
+ it ne\r
+ svcne 1 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */\r
+ bx lr /* Return. */\r
/*-----------------------------------------------------------*/\r
\r
- END\r
+ END\r
* 1 tab == 4 spaces!\r
*/\r
\r
- EXTERN pxCurrentTCB\r
- EXTERN vTaskSwitchContext\r
- EXTERN vPortSVCHandler_C\r
-\r
- PUBLIC xIsPrivileged\r
- PUBLIC vResetPrivilege\r
- PUBLIC vRestoreContextOfFirstTask\r
- PUBLIC vRaisePrivilege\r
- PUBLIC vStartFirstTask\r
- PUBLIC ulSetInterruptMaskFromISR\r
- PUBLIC vClearInterruptMaskFromISR\r
- PUBLIC PendSV_Handler\r
- PUBLIC SVC_Handler\r
+ EXTERN pxCurrentTCB\r
+ EXTERN vTaskSwitchContext\r
+ EXTERN vPortSVCHandler_C\r
+\r
+ PUBLIC xIsPrivileged\r
+ PUBLIC vResetPrivilege\r
+ PUBLIC vRestoreContextOfFirstTask\r
+ PUBLIC vRaisePrivilege\r
+ PUBLIC vStartFirstTask\r
+ PUBLIC ulSetInterruptMaskFromISR\r
+ PUBLIC vClearInterruptMaskFromISR\r
+ PUBLIC PendSV_Handler\r
+ PUBLIC SVC_Handler\r
/*-----------------------------------------------------------*/\r
\r
/*---------------- Unprivileged Functions -------------------*/\r
\r
/*-----------------------------------------------------------*/\r
\r
- SECTION .text:CODE:NOROOT(2)\r
- THUMB\r
+ SECTION .text:CODE:NOROOT(2)\r
+ THUMB\r
/*-----------------------------------------------------------*/\r
\r
xIsPrivileged:\r
- mrs r0, control /* r0 = CONTROL. */\r
- tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\r
- ite ne\r
- movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
- moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */\r
- bx lr /* Return. */\r
+ mrs r0, control /* r0 = CONTROL. */\r
+ tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\r
+ ite ne\r
+ movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
+ moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */\r
+ bx lr /* Return. */\r
/*-----------------------------------------------------------*/\r
\r
vResetPrivilege:\r
- mrs r0, control /* r0 = CONTROL. */\r
- orr r0, r0, #1 /* r0 = r0 | 1. */\r
- msr control, r0 /* CONTROL = r0. */\r
- bx lr /* Return to the caller. */\r
+ mrs r0, control /* r0 = CONTROL. */\r
+ orr r0, r0, #1 /* r0 = r0 | 1. */\r
+ msr control, r0 /* CONTROL = r0. */\r
+ bx lr /* Return to the caller. */\r
/*-----------------------------------------------------------*/\r
\r
/*----------------- Privileged Functions --------------------*/\r
\r
/*-----------------------------------------------------------*/\r
\r
- SECTION privileged_functions:CODE:NOROOT(2)\r
- THUMB\r
+ SECTION privileged_functions:CODE:NOROOT(2)\r
+ THUMB\r
/*-----------------------------------------------------------*/\r
\r
vRestoreContextOfFirstTask:\r
- ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
- ldr r1, [r2] /* Read pxCurrentTCB. */\r
- ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ ldr r1, [r2] /* Read pxCurrentTCB. */\r
+ ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
\r
#if ( configENABLE_MPU == 1 )\r
- adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
- ldr r3, [r1] /* r3 = *r1 i.e. r3 = MAIR0. */\r
- ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
- str r3, [r2] /* Program MAIR0. */\r
- ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */\r
- movs r3, #4 /* r3 = 4. */\r
- str r3, [r2] /* Program RNR = 4. */\r
- adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
- ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */\r
- ldmia r1!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
- stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+ adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
+ ldr r3, [r1] /* r3 = *r1 i.e. r3 = MAIR0. */\r
+ ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ str r3, [r2] /* Program MAIR0. */\r
+ ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ movs r3, #4 /* r3 = 4. */\r
+ str r3, [r2] /* Program RNR = 4. */\r
+ adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
+ ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */\r
+ ldmia r1!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
+ stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
#endif /* configENABLE_MPU */\r
\r
#if ( configENABLE_MPU == 1 )\r
- ldm r0!, {r1-r3} /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */\r
- msr psplim, r1 /* Set this task's PSPLIM value. */\r
- msr control, r2 /* Set this task's CONTROL value. */\r
- adds r0, #32 /* Discard everything up to r0. */\r
- msr psp, r0 /* This is now the new top of stack to use in the task. */\r
- isb\r
- bx r3 /* Finally, branch to EXC_RETURN. */\r
+ ldm r0!, {r1-r3} /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */\r
+ msr psplim, r1 /* Set this task's PSPLIM value. */\r
+ msr control, r2 /* Set this task's CONTROL value. */\r
+ adds r0, #32 /* Discard everything up to r0. */\r
+ msr psp, r0 /* This is now the new top of stack to use in the task. */\r
+ isb\r
+ bx r3 /* Finally, branch to EXC_RETURN. */\r
#else /* configENABLE_MPU */\r
- ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */\r
- msr psplim, r1 /* Set this task's PSPLIM value. */\r
- movs r1, #2 /* r1 = 2. */\r
- msr CONTROL, r1 /* Switch to use PSP in the thread mode. */\r
- adds r0, #32 /* Discard everything up to r0. */\r
- msr psp, r0 /* This is now the new top of stack to use in the task. */\r
- isb\r
- bx r2 /* Finally, branch to EXC_RETURN. */\r
+ ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */\r
+ msr psplim, r1 /* Set this task's PSPLIM value. */\r
+ movs r1, #2 /* r1 = 2. */\r
+ msr CONTROL, r1 /* Switch to use PSP in the thread mode. */\r
+ adds r0, #32 /* Discard everything up to r0. */\r
+ msr psp, r0 /* This is now the new top of stack to use in the task. */\r
+ isb\r
+ bx r2 /* Finally, branch to EXC_RETURN. */\r
#endif /* configENABLE_MPU */\r
/*-----------------------------------------------------------*/\r
\r
vRaisePrivilege:\r
- mrs r0, control /* Read the CONTROL register. */\r
- bic r0, r0, #1 /* Clear the bit 0. */\r
- msr control, r0 /* Write back the new CONTROL value. */\r
- bx lr /* Return to the caller. */\r
+ mrs r0, control /* Read the CONTROL register. */\r
+ bic r0, r0, #1 /* Clear the bit 0. */\r
+ msr control, r0 /* Write back the new CONTROL value. */\r
+ bx lr /* Return to the caller. */\r
/*-----------------------------------------------------------*/\r
\r
vStartFirstTask:\r
- ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */\r
- ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */\r
- ldr r0, [r0] /* The first entry in vector table is stack pointer. */\r
- msr msp, r0 /* Set the MSP back to the start of the stack. */\r
- cpsie i /* Globally enable interrupts. */\r
- cpsie f\r
- dsb\r
- isb\r
- svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */\r
+ ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */\r
+ ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */\r
+ ldr r0, [r0] /* The first entry in vector table is stack pointer. */\r
+ msr msp, r0 /* Set the MSP back to the start of the stack. */\r
+ cpsie i /* Globally enable interrupts. */\r
+ cpsie f\r
+ dsb\r
+ isb\r
+ svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */\r
/*-----------------------------------------------------------*/\r
\r
ulSetInterruptMaskFromISR:\r
- mrs r0, PRIMASK\r
- cpsid i\r
- bx lr\r
+ mrs r0, PRIMASK\r
+ cpsid i\r
+ bx lr\r
/*-----------------------------------------------------------*/\r
\r
vClearInterruptMaskFromISR:\r
- msr PRIMASK, r0\r
- bx lr\r
+ msr PRIMASK, r0\r
+ bx lr\r
/*-----------------------------------------------------------*/\r
\r
PendSV_Handler:\r
- mrs r0, psp /* Read PSP in r0. */\r
+ mrs r0, psp /* Read PSP in r0. */\r
#if ( configENABLE_FPU == 1 )\r
- tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
- it eq\r
- vstmdbeq r0!, {s16-s31} /* Store the FPU registers which are not saved automatically. */\r
+ tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
+ it eq\r
+ vstmdbeq r0!, {s16-s31} /* Store the FPU registers which are not saved automatically. */\r
#endif /* configENABLE_FPU */\r
#if ( configENABLE_MPU == 1 )\r
- mrs r1, psplim /* r1 = PSPLIM. */\r
- mrs r2, control /* r2 = CONTROL. */\r
- mov r3, lr /* r3 = LR/EXC_RETURN. */\r
- stmdb r0!, {r1-r11} /* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */\r
+ mrs r1, psplim /* r1 = PSPLIM. */\r
+ mrs r2, control /* r2 = CONTROL. */\r
+ mov r3, lr /* r3 = LR/EXC_RETURN. */\r
+ stmdb r0!, {r1-r11} /* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */\r
#else /* configENABLE_MPU */\r
- mrs r2, psplim /* r2 = PSPLIM. */\r
- mov r3, lr /* r3 = LR/EXC_RETURN. */\r
- stmdb r0!, {r2-r11} /* Store on the stack - PSPLIM, LR and registers that are not automatically. */\r
+ mrs r2, psplim /* r2 = PSPLIM. */\r
+ mov r3, lr /* r3 = LR/EXC_RETURN. */\r
+ stmdb r0!, {r2-r11} /* Store on the stack - PSPLIM, LR and registers that are not automatically. */\r
#endif /* configENABLE_MPU */\r
\r
- ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
- ldr r1, [r2] /* Read pxCurrentTCB. */\r
- str r0, [r1] /* Save the new top of stack in TCB. */\r
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ ldr r1, [r2] /* Read pxCurrentTCB. */\r
+ str r0, [r1] /* Save the new top of stack in TCB. */\r
\r
- cpsid i\r
- bl vTaskSwitchContext\r
- cpsie i\r
+ cpsid i\r
+ bl vTaskSwitchContext\r
+ cpsie i\r
\r
- ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
- ldr r1, [r2] /* Read pxCurrentTCB. */\r
- ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */\r
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ ldr r1, [r2] /* Read pxCurrentTCB. */\r
+ ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */\r
\r
#if ( configENABLE_MPU == 1 )\r
- adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
- ldr r3, [r1] /* r3 = *r1 i.e. r3 = MAIR0. */\r
- ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
- str r3, [r2] /* Program MAIR0. */\r
- ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */\r
- movs r3, #4 /* r3 = 4. */\r
- str r3, [r2] /* Program RNR = 4. */\r
- adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
- ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */\r
- ldmia r1!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
- stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+ adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
+ ldr r3, [r1] /* r3 = *r1 i.e. r3 = MAIR0. */\r
+ ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ str r3, [r2] /* Program MAIR0. */\r
+ ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ movs r3, #4 /* r3 = 4. */\r
+ str r3, [r2] /* Program RNR = 4. */\r
+ adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
+ ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */\r
+ ldmia r1!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
+ stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
#endif /* configENABLE_MPU */\r
\r
#if ( configENABLE_MPU == 1 )\r
- ldmia r0!, {r1-r11} /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */\r
+ ldmia r0!, {r1-r11} /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */\r
#else /* configENABLE_MPU */\r
- ldmia r0!, {r2-r11} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */\r
+ ldmia r0!, {r2-r11} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */\r
#endif /* configENABLE_MPU */\r
\r
#if ( configENABLE_FPU == 1 )\r
- tst r3, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
- it eq\r
- vldmiaeq r0!, {s16-s31} /* Restore the FPU registers which are not restored automatically. */\r
+ tst r3, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
+ it eq\r
+ vldmiaeq r0!, {s16-s31} /* Restore the FPU registers which are not restored automatically. */\r
#endif /* configENABLE_FPU */\r
\r
#if ( configENABLE_MPU == 1 )\r
- msr psplim, r1 /* Restore the PSPLIM register value for the task. */\r
- msr control, r2 /* Restore the CONTROL register value for the task. */\r
+ msr psplim, r1 /* Restore the PSPLIM register value for the task. */\r
+ msr control, r2 /* Restore the CONTROL register value for the task. */\r
#else /* configENABLE_MPU */\r
- msr psplim, r2 /* Restore the PSPLIM register value for the task. */\r
+ msr psplim, r2 /* Restore the PSPLIM register value for the task. */\r
#endif /* configENABLE_MPU */\r
- msr psp, r0 /* Remember the new top of stack for the task. */\r
- bx r3\r
+ msr psp, r0 /* Remember the new top of stack for the task. */\r
+ bx r3\r
/*-----------------------------------------------------------*/\r
\r
SVC_Handler:\r
- tst lr, #4\r
- ite eq\r
- mrseq r0, msp\r
- mrsne r0, psp\r
- b vPortSVCHandler_C\r
+ tst lr, #4\r
+ ite eq\r
+ mrseq r0, msp\r
+ mrsne r0, psp\r
+ b vPortSVCHandler_C\r
/*-----------------------------------------------------------*/\r
\r
- END\r
+ END\r
*------------------------------------------------------------------------------\r
*/\r
\r
+#ifndef configENABLE_FPU\r
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h.\r
+#endif /* configENABLE_FPU */\r
+\r
+#ifndef configENABLE_MPU\r
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h.\r
+#endif /* configENABLE_MPU */\r
+\r
+#ifndef configENABLE_TRUSTZONE\r
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.\r
+#endif /* configENABLE_TRUSTZONE */\r
+/*-----------------------------------------------------------*/\r
+\r
/**\r
* @brief Type definitions.\r
*/\r
-#define portCHAR char\r
-#define portFLOAT float\r
-#define portDOUBLE double\r
-#define portLONG long\r
-#define portSHORT short\r
-#define portSTACK_TYPE uint32_t\r
-#define portBASE_TYPE long\r
-\r
-typedef portSTACK_TYPE StackType_t;\r
-typedef long BaseType_t;\r
-typedef unsigned long UBaseType_t;\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT short\r
+#define portSTACK_TYPE uint32_t\r
+#define portBASE_TYPE long\r
+\r
+typedef portSTACK_TYPE StackType_t;\r
+typedef long BaseType_t;\r
+typedef unsigned long UBaseType_t;\r
\r
#if( configUSE_16_BIT_TICKS == 1 )\r
- typedef uint16_t TickType_t;\r
- #define portMAX_DELAY ( TickType_t ) 0xffff\r
+ typedef uint16_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffff\r
#else\r
- typedef uint32_t TickType_t;\r
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL\r
+ typedef uint32_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL\r
\r
- /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\r
- * not need to be guarded with a critical section. */\r
- #define portTICK_TYPE_IS_ATOMIC 1\r
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\r
+ * not need to be guarded with a critical section. */\r
+ #define portTICK_TYPE_IS_ATOMIC 1\r
#endif\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* Architecture specifics.\r
*/\r
-#define portSTACK_GROWTH ( -1 )\r
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
-#define portBYTE_ALIGNMENT 8\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
+#define portBYTE_ALIGNMENT 8\r
#define portNOP()\r
-#define portINLINE __inline\r
+#define portINLINE __inline\r
#ifndef portFORCE_INLINE\r
- #define portFORCE_INLINE inline __attribute__(( always_inline ))\r
+ #define portFORCE_INLINE inline __attribute__(( always_inline ))\r
#endif\r
-#define portHAS_STACK_OVERFLOW_CHECKING 1\r
+#define portHAS_STACK_OVERFLOW_CHECKING 1\r
/*-----------------------------------------------------------*/\r
\r
/**\r
extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );\r
- extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* PRIVILEGED_FUNCTION */;\r
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );\r
+ extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* PRIVILEGED_FUNCTION */;\r
#endif /* configENABLE_TRUSTZONE */\r
\r
#if( configENABLE_MPU == 1 )\r
- extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;\r
- extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;\r
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;\r
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;\r
#endif /* configENABLE_MPU */\r
/*-----------------------------------------------------------*/\r
\r
* @brief MPU specific constants.\r
*/\r
#if( configENABLE_MPU == 1 )\r
- #define portUSING_MPU_WRAPPERS 1\r
- #define portPRIVILEGE_BIT ( 0x80000000UL )\r
+ #define portUSING_MPU_WRAPPERS 1\r
+ #define portPRIVILEGE_BIT ( 0x80000000UL )\r
#else\r
- #define portPRIVILEGE_BIT ( 0x0UL )\r
+ #define portPRIVILEGE_BIT ( 0x0UL )\r
#endif /* configENABLE_MPU */\r
\r
\r
/* MPU regions. */\r
-#define portPRIVILEGED_FLASH_REGION ( 0UL )\r
-#define portUNPRIVILEGED_FLASH_REGION ( 1UL )\r
-#define portPRIVILEGED_RAM_REGION ( 2UL )\r
-#define portUNPRIVILEGED_DEVICE_REGION ( 3UL )\r
-#define portSTACK_REGION ( 4UL )\r
-#define portFIRST_CONFIGURABLE_REGION ( 5UL )\r
-#define portLAST_CONFIGURABLE_REGION ( 7UL )\r
-#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\r
-#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */\r
+#define portPRIVILEGED_FLASH_REGION ( 0UL )\r
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )\r
+#define portPRIVILEGED_RAM_REGION ( 2UL )\r
+#define portUNPRIVILEGED_DEVICE_REGION ( 3UL )\r
+#define portSTACK_REGION ( 4UL )\r
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )\r
+#define portLAST_CONFIGURABLE_REGION ( 7UL )\r
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\r
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */\r
\r
/* Devices Region. */\r
-#define portDEVICE_REGION_START_ADDRESS ( 0x50000000 )\r
-#define portDEVICE_REGION_END_ADDRESS ( 0x5FFFFFFF )\r
+#define portDEVICE_REGION_START_ADDRESS ( 0x50000000 )\r
+#define portDEVICE_REGION_END_ADDRESS ( 0x5FFFFFFF )\r
\r
/* Device memory attributes used in MPU_MAIR registers.\r
*\r
* 8-bit values encoded as follows:\r
* Bit[7:4] - 0000 - Device Memory\r
* Bit[3:2] - 00 --> Device-nGnRnE\r
- * 01 --> Device-nGnRE\r
- * 10 --> Device-nGRE\r
- * 11 --> Device-GRE\r
+ * 01 --> Device-nGnRE\r
+ * 10 --> Device-nGRE\r
+ * 11 --> Device-GRE\r
* Bit[1:0] - 00, Reserved.\r
*/\r
-#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */\r
-#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */\r
-#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */\r
-#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */\r
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */\r
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */\r
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */\r
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */\r
\r
/* Normal memory attributes used in MPU_MAIR registers. */\r
-#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */\r
-#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */\r
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */\r
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */\r
\r
/* Attributes used in MPU_RBAR registers. */\r
-#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )\r
-#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )\r
-#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )\r
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )\r
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )\r
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )\r
\r
-#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )\r
-#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )\r
-#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )\r
-#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )\r
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )\r
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )\r
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )\r
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )\r
\r
-#define portMPU_REGION_EXECUTE_NEVER ( 1UL )\r
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )\r
/*-----------------------------------------------------------*/\r
\r
/**\r
*/\r
typedef struct MPURegionSettings\r
{\r
- uint32_t ulRBAR; /**< RBAR for the region. */\r
- uint32_t ulRLAR; /**< RLAR for the region. */\r
+ uint32_t ulRBAR; /**< RBAR for the region. */\r
+ uint32_t ulRLAR; /**< RLAR for the region. */\r
} MPURegionSettings_t;\r
\r
/**\r
*/\r
typedef struct MPU_SETTINGS\r
{\r
- uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */\r
- MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */\r
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */\r
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */\r
} xMPU_SETTINGS;\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief SVC numbers.\r
*/\r
-#define portSVC_ALLOCATE_SECURE_CONTEXT 0\r
-#define portSVC_FREE_SECURE_CONTEXT 1\r
-#define portSVC_START_SCHEDULER 2\r
-#define portSVC_RAISE_PRIVILEGE 3\r
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0\r
+#define portSVC_FREE_SECURE_CONTEXT 1\r
+#define portSVC_START_SCHEDULER 2\r
+#define portSVC_RAISE_PRIVILEGE 3\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Scheduler utilities.\r
*/\r
-#define portYIELD() vPortYield()\r
-#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )\r
-#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )\r
-#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT\r
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
+#define portYIELD() vPortYield()\r
+#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )\r
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )\r
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT\r
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Critical section management.\r
*/\r
-#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()\r
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )\r
-#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )\r
-#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )\r
-#define portENTER_CRITICAL() vPortEnterCritical()\r
-#define portEXIT_CRITICAL() vPortExitCritical()\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )\r
+#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )\r
+#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )\r
+#define portENTER_CRITICAL() vPortEnterCritical()\r
+#define portEXIT_CRITICAL() vPortExitCritical()\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Task function macros as described on the FreeRTOS.org WEB site.\r
*/\r
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
/*-----------------------------------------------------------*/\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
- /**\r
- * @brief Allocate a secure context for the task.\r
- *\r
- * Tasks are not created with a secure context. Any task that is going to call\r
- * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a\r
- * secure context before it calls any secure function.\r
- *\r
- * @param[in] ulSecureStackSize The size of the secure stack to be allocated.\r
- */\r
- #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )\r
-\r
- /**\r
- * @brief Called when a task is deleted to delete the task's secure context,\r
- * if it has one.\r
- *\r
- * @param[in] pxTCB The TCB of the task being deleted.\r
- */\r
- #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )\r
+ /**\r
+ * @brief Allocate a secure context for the task.\r
+ *\r
+ * Tasks are not created with a secure context. Any task that is going to call\r
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a\r
+ * secure context before it calls any secure function.\r
+ *\r
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.\r
+ */\r
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )\r
+\r
+ /**\r
+ * @brief Called when a task is deleted to delete the task's secure context,\r
+ * if it has one.\r
+ *\r
+ * @param[in] pxTCB The TCB of the task being deleted.\r
+ */\r
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )\r
#else\r
- #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )\r
- #define portCLEAN_UP_TCB( pxTCB )\r
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )\r
+ #define portCLEAN_UP_TCB( pxTCB )\r
#endif /* configENABLE_TRUSTZONE */\r
/*-----------------------------------------------------------*/\r
\r
#if( configENABLE_MPU == 1 )\r
- /**\r
- * @brief Checks whether or not the processor is privileged.\r
- *\r
- * @return 1 if the processor is already privileged, 0 otherwise.\r
- */\r
- #define portIS_PRIVILEGED() xIsPrivileged()\r
-\r
- /**\r
- * @brief Raise an SVC request to raise privilege.\r
- *\r
- * The SVC handler checks that the SVC was raised from a system call and only\r
- * then it raises the privilege. If this is called from any other place,\r
- * the privilege is not raised.\r
- */\r
- #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );\r
-\r
- /**\r
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\r
- * register.\r
- */\r
- #define portRESET_PRIVILEGE() vResetPrivilege()\r
+ /**\r
+ * @brief Checks whether or not the processor is privileged.\r
+ *\r
+ * @return 1 if the processor is already privileged, 0 otherwise.\r
+ */\r
+ #define portIS_PRIVILEGED() xIsPrivileged()\r
+\r
+ /**\r
+ * @brief Raise an SVC request to raise privilege.\r
+ *\r
+ * The SVC handler checks that the SVC was raised from a system call and only\r
+ * then it raises the privilege. If this is called from any other place,\r
+ * the privilege is not raised.\r
+ */\r
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );\r
+\r
+ /**\r
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\r
+ * register.\r
+ */\r
+ #define portRESET_PRIVILEGE() vResetPrivilege()\r
#else\r
- #define portIS_PRIVILEGED()\r
- #define portRAISE_PRIVILEGE()\r
- #define portRESET_PRIVILEGE()\r
+ #define portIS_PRIVILEGED()\r
+ #define portRAISE_PRIVILEGE()\r
+ #define portRESET_PRIVILEGE()\r
#endif /* configENABLE_MPU */\r
/*-----------------------------------------------------------*/\r
\r
\r
secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )\r
{\r
- /* xSecureContextHandle value is in r0. */\r
- __asm volatile\r
- (\r
- " .syntax unified \n"\r
- " \n"\r
- " mrs r1, ipsr \n" /* r1 = IPSR. */\r
- " cbz r1, load_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */\r
- " ldmia r0!, {r1, r2} \n" /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */\r
- #if( configENABLE_MPU == 1 )\r
- " ldmia r1!, {r3} \n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */\r
- " msr control, r3 \n" /* CONTROL = r3. */\r
- #endif /* configENABLE_MPU */\r
- " msr psplim, r2 \n" /* PSPLIM = r2. */\r
- " msr psp, r1 \n" /* PSP = r1. */\r
- " \n"\r
- " load_ctx_therad_mode: \n"\r
- " nop \n"\r
- " \n"\r
- :::"r0", "r1", "r2"\r
- );\r
+ /* xSecureContextHandle value is in r0. */\r
+ __asm volatile\r
+ (\r
+ " .syntax unified \n"\r
+ " \n"\r
+ " mrs r1, ipsr \n" /* r1 = IPSR. */\r
+ " cbz r1, load_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */\r
+ " ldmia r0!, {r1, r2} \n" /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */\r
+ #if( configENABLE_MPU == 1 )\r
+ " ldmia r1!, {r3} \n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */\r
+ " msr control, r3 \n" /* CONTROL = r3. */\r
+ #endif /* configENABLE_MPU */\r
+ " msr psplim, r2 \n" /* PSPLIM = r2. */\r
+ " msr psp, r1 \n" /* PSP = r1. */\r
+ " \n"\r
+ " load_ctx_therad_mode: \n"\r
+ " nop \n"\r
+ " \n"\r
+ :::"r0", "r1", "r2"\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
\r
secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )\r
{\r
- /* xSecureContextHandle value is in r0. */\r
- __asm volatile\r
- (\r
- " .syntax unified \n"\r
- " \n"\r
- " mrs r1, ipsr \n" /* r1 = IPSR. */\r
- " cbz r1, save_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */\r
- " mrs r1, psp \n" /* r1 = PSP. */\r
- #if( configENABLE_FPU == 1 )\r
- " vstmdb r1!, {s0} \n" /* Trigger the defferred stacking of FPU registers. */\r
- " vldmia r1!, {s0} \n" /* Nullify the effect of the pervious statement. */\r
- #endif /* configENABLE_FPU */\r
- #if( configENABLE_MPU == 1 )\r
- " mrs r2, control \n" /* r2 = CONTROL. */\r
- " stmdb r1!, {r2} \n" /* Store CONTROL value on the stack. */\r
- #endif /* configENABLE_MPU */\r
- " str r1, [r0] \n" /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */\r
- " movs r1, %0 \n" /* r1 = securecontextNO_STACK. */\r
- " msr psplim, r1 \n" /* PSPLIM = securecontextNO_STACK. */\r
- " msr psp, r1 \n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */\r
- " \n"\r
- " save_ctx_therad_mode: \n"\r
- " nop \n"\r
- " \n"\r
- :: "i" ( securecontextNO_STACK ) : "r1", "memory"\r
- );\r
+ /* xSecureContextHandle value is in r0. */\r
+ __asm volatile\r
+ (\r
+ " .syntax unified \n"\r
+ " \n"\r
+ " mrs r1, ipsr \n" /* r1 = IPSR. */\r
+ " cbz r1, save_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */\r
+ " mrs r1, psp \n" /* r1 = PSP. */\r
+ #if( configENABLE_FPU == 1 )\r
+ " vstmdb r1!, {s0} \n" /* Trigger the defferred stacking of FPU registers. */\r
+ " vldmia r1!, {s0} \n" /* Nullify the effect of the pervious statement. */\r
+ #endif /* configENABLE_FPU */\r
+ #if( configENABLE_MPU == 1 )\r
+ " mrs r2, control \n" /* r2 = CONTROL. */\r
+ " stmdb r1!, {r2} \n" /* Store CONTROL value on the stack. */\r
+ #endif /* configENABLE_MPU */\r
+ " str r1, [r0] \n" /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */\r
+ " movs r1, %0 \n" /* r1 = securecontextNO_STACK. */\r
+ " msr psplim, r1 \n" /* PSPLIM = securecontextNO_STACK. */\r
+ " msr psp, r1 \n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */\r
+ " \n"\r
+ " save_ctx_therad_mode: \n"\r
+ " nop \n"\r
+ " \n"\r
+ :: "i" ( securecontextNO_STACK ) : "r1", "memory"\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
\r
secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )\r
{\r
- SecureContext_LoadContextAsm( xSecureContextHandle );\r
+ SecureContext_LoadContextAsm( xSecureContextHandle );\r
}\r
/*-----------------------------------------------------------*/\r
\r
secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )\r
{\r
- SecureContext_SaveContextAsm( xSecureContextHandle );\r
+ SecureContext_SaveContextAsm( xSecureContextHandle );\r
}\r
/*-----------------------------------------------------------*/\r
* 1 tab == 4 spaces!\r
*/\r
\r
- SECTION .text:CODE:NOROOT(2)\r
- THUMB\r
+ SECTION .text:CODE:NOROOT(2)\r
+ THUMB\r
\r
- PUBLIC SecureContext_LoadContextAsm\r
- PUBLIC SecureContext_SaveContextAsm\r
+ PUBLIC SecureContext_LoadContextAsm\r
+ PUBLIC SecureContext_SaveContextAsm\r
/*-----------------------------------------------------------*/\r
\r
SecureContext_LoadContextAsm:\r
- /* xSecureContextHandle value is in r0. */\r
- mrs r1, ipsr /* r1 = IPSR. */\r
- cbz r1, load_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */\r
- ldmia r0!, {r1, r2} /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */\r
+ /* xSecureContextHandle value is in r0. */\r
+ mrs r1, ipsr /* r1 = IPSR. */\r
+ cbz r1, load_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */\r
+ ldmia r0!, {r1, r2} /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */\r
#if ( configENABLE_MPU == 1 )\r
- ldmia r1!, {r3} /* Read CONTROL register value from task's stack. r3 = CONTROL. */\r
- msr control, r3 /* CONTROL = r3. */\r
+ ldmia r1!, {r3} /* Read CONTROL register value from task's stack. r3 = CONTROL. */\r
+ msr control, r3 /* CONTROL = r3. */\r
#endif /* configENABLE_MPU */\r
- msr psplim, r2 /* PSPLIM = r2. */\r
- msr psp, r1 /* PSP = r1. */\r
+ msr psplim, r2 /* PSPLIM = r2. */\r
+ msr psp, r1 /* PSP = r1. */\r
\r
- load_ctx_therad_mode:\r
- bx lr\r
+ load_ctx_therad_mode:\r
+ bx lr\r
/*-----------------------------------------------------------*/\r
\r
SecureContext_SaveContextAsm:\r
- /* xSecureContextHandle value is in r0. */\r
- mrs r1, ipsr /* r1 = IPSR. */\r
- cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */\r
- mrs r1, psp /* r1 = PSP. */\r
+ /* xSecureContextHandle value is in r0. */\r
+ mrs r1, ipsr /* r1 = IPSR. */\r
+ cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */\r
+ mrs r1, psp /* r1 = PSP. */\r
#if ( configENABLE_FPU == 1 )\r
- vstmdb r1!, {s0} /* Trigger the defferred stacking of FPU registers. */\r
- vldmia r1!, {s0} /* Nullify the effect of the pervious statement. */\r
+ vstmdb r1!, {s0} /* Trigger the defferred stacking of FPU registers. */\r
+ vldmia r1!, {s0} /* Nullify the effect of the pervious statement. */\r
#endif /* configENABLE_FPU */\r
#if ( configENABLE_MPU == 1 )\r
- mrs r2, control /* r2 = CONTROL. */\r
- stmdb r1!, {r2} /* Store CONTROL value on the stack. */\r
+ mrs r2, control /* r2 = CONTROL. */\r
+ stmdb r1!, {r2} /* Store CONTROL value on the stack. */\r
#endif /* configENABLE_MPU */\r
- str r1, [r0] /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */\r
- movs r1, #0 /* r1 = securecontextNO_STACK. */\r
- msr psplim, r1 /* PSPLIM = securecontextNO_STACK. */\r
- msr psp, r1 /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */\r
+ str r1, [r0] /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */\r
+ movs r1, #0 /* r1 = securecontextNO_STACK. */\r
+ msr psplim, r1 /* PSPLIM = securecontextNO_STACK. */\r
+ msr psp, r1 /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */\r
\r
- save_ctx_therad_mode:\r
- bx lr\r
+ save_ctx_therad_mode:\r
+ bx lr\r
/*-----------------------------------------------------------*/\r
\r
- END\r
+ END\r
* Bit[0] - 0 --> Thread mode is privileged.\r
* Bit[1] - 1 --> Thread mode uses PSP.\r
*/\r
-#define securecontextCONTROL_VALUE_PRIVILEGED 0x02\r
+#define securecontextCONTROL_VALUE_PRIVILEGED 0x02\r
\r
/**\r
* @brief CONTROL value for un-privileged tasks.\r
* Bit[0] - 1 --> Thread mode is un-privileged.\r
* Bit[1] - 1 --> Thread mode uses PSP.\r
*/\r
-#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03\r
+#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03\r
/*-----------------------------------------------------------*/\r
\r
/**\r
*/\r
typedef struct SecureContext\r
{\r
- uint8_t *pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */\r
- uint8_t *pucStackLimit; /**< Last location of the stack memory (PSPLIM). */\r
- uint8_t *pucStackStart; /**< First location of the stack memory. */\r
+ uint8_t *pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */\r
+ uint8_t *pucStackLimit; /**< Last location of the stack memory (PSPLIM). */\r
+ uint8_t *pucStackStart; /**< First location of the stack memory. */\r
} SecureContext_t;\r
/*-----------------------------------------------------------*/\r
\r
secureportNON_SECURE_CALLABLE void SecureContext_Init( void )\r
{\r
- uint32_t ulIPSR;\r
-\r
- /* Read the Interrupt Program Status Register (IPSR) value. */\r
- secureportREAD_IPSR( ulIPSR );\r
-\r
- /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
- * when the processor is running in the Thread Mode. */\r
- if( ulIPSR != 0 )\r
- {\r
- /* No stack for thread mode until a task's context is loaded. */\r
- secureportSET_PSPLIM( securecontextNO_STACK );\r
- secureportSET_PSP( securecontextNO_STACK );\r
-\r
- #if( configENABLE_MPU == 1 )\r
- {\r
- /* Configure thread mode to use PSP and to be unprivileged. */\r
- secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );\r
- }\r
- #else /* configENABLE_MPU */\r
- {\r
- /* Configure thread mode to use PSP and to be privileged.. */\r
- secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );\r
- }\r
- #endif /* configENABLE_MPU */\r
- }\r
+ uint32_t ulIPSR;\r
+\r
+ /* Read the Interrupt Program Status Register (IPSR) value. */\r
+ secureportREAD_IPSR( ulIPSR );\r
+\r
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
+ * when the processor is running in the Thread Mode. */\r
+ if( ulIPSR != 0 )\r
+ {\r
+ /* No stack for thread mode until a task's context is loaded. */\r
+ secureportSET_PSPLIM( securecontextNO_STACK );\r
+ secureportSET_PSP( securecontextNO_STACK );\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ /* Configure thread mode to use PSP and to be unprivileged. */\r
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );\r
+ }\r
+ #else /* configENABLE_MPU */\r
+ {\r
+ /* Configure thread mode to use PSP and to be privileged.. */\r
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
\r
#if( configENABLE_MPU == 1 )\r
- secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged )\r
+ secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged )\r
#else /* configENABLE_MPU */\r
- secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize )\r
+ secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize )\r
#endif /* configENABLE_MPU */\r
{\r
- uint8_t *pucStackMemory = NULL;\r
- uint32_t ulIPSR;\r
- SecureContextHandle_t xSecureContextHandle = NULL;\r
- #if( configENABLE_MPU == 1 )\r
- uint32_t *pulCurrentStackPointer = NULL;\r
- #endif /* configENABLE_MPU */\r
-\r
- /* Read the Interrupt Program Status Register (IPSR) value. */\r
- secureportREAD_IPSR( ulIPSR );\r
-\r
- /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
- * when the processor is running in the Thread Mode. */\r
- if( ulIPSR != 0 )\r
- {\r
- /* Allocate the context structure. */\r
- xSecureContextHandle = ( SecureContextHandle_t ) pvPortMalloc( sizeof( SecureContext_t ) );\r
-\r
- if( xSecureContextHandle != NULL )\r
- {\r
- /* Allocate the stack space. */\r
- pucStackMemory = pvPortMalloc( ulSecureStackSize );\r
-\r
- if( pucStackMemory != NULL )\r
- {\r
- /* Since stack grows down, the starting point will be the last\r
- * location. Note that this location is next to the last\r
- * allocated byte because the hardware decrements the stack\r
- * pointer before writing i.e. if stack pointer is 0x2, a push\r
- * operation will decrement the stack pointer to 0x1 and then\r
- * write at 0x1. */\r
- xSecureContextHandle->pucStackStart = pucStackMemory + ulSecureStackSize;\r
-\r
- /* The stack cannot go beyond this location. This value is\r
- * programmed in the PSPLIM register on context switch.*/\r
- xSecureContextHandle->pucStackLimit = pucStackMemory;\r
-\r
- #if( configENABLE_MPU == 1 )\r
- {\r
- /* Store the correct CONTROL value for the task on the stack.\r
- * This value is programmed in the CONTROL register on\r
- * context switch. */\r
- pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;\r
- pulCurrentStackPointer--;\r
- if( ulIsTaskPrivileged )\r
- {\r
- *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;\r
- }\r
- else\r
- {\r
- *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;\r
- }\r
-\r
- /* Store the current stack pointer. This value is programmed in\r
- * the PSP register on context switch. */\r
- xSecureContextHandle->pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;\r
- }\r
- #else /* configENABLE_MPU */\r
- {\r
- /* Current SP is set to the starting of the stack. This\r
- * value programmed in the PSP register on context switch. */\r
- xSecureContextHandle->pucCurrentStackPointer = xSecureContextHandle->pucStackStart;\r
-\r
- }\r
- #endif /* configENABLE_MPU */\r
- }\r
- else\r
- {\r
- /* Free the context to avoid memory leak and make sure to return\r
- * NULL to indicate failure. */\r
- vPortFree( xSecureContextHandle );\r
- xSecureContextHandle = NULL;\r
- }\r
- }\r
- }\r
-\r
- return xSecureContextHandle;\r
+ uint8_t *pucStackMemory = NULL;\r
+ uint32_t ulIPSR;\r
+ SecureContextHandle_t xSecureContextHandle = NULL;\r
+ #if( configENABLE_MPU == 1 )\r
+ uint32_t *pulCurrentStackPointer = NULL;\r
+ #endif /* configENABLE_MPU */\r
+\r
+ /* Read the Interrupt Program Status Register (IPSR) value. */\r
+ secureportREAD_IPSR( ulIPSR );\r
+\r
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
+ * when the processor is running in the Thread Mode. */\r
+ if( ulIPSR != 0 )\r
+ {\r
+ /* Allocate the context structure. */\r
+ xSecureContextHandle = ( SecureContextHandle_t ) pvPortMalloc( sizeof( SecureContext_t ) );\r
+\r
+ if( xSecureContextHandle != NULL )\r
+ {\r
+ /* Allocate the stack space. */\r
+ pucStackMemory = pvPortMalloc( ulSecureStackSize );\r
+\r
+ if( pucStackMemory != NULL )\r
+ {\r
+ /* Since stack grows down, the starting point will be the last\r
+ * location. Note that this location is next to the last\r
+ * allocated byte because the hardware decrements the stack\r
+ * pointer before writing i.e. if stack pointer is 0x2, a push\r
+ * operation will decrement the stack pointer to 0x1 and then\r
+ * write at 0x1. */\r
+ xSecureContextHandle->pucStackStart = pucStackMemory + ulSecureStackSize;\r
+\r
+ /* The stack cannot go beyond this location. This value is\r
+ * programmed in the PSPLIM register on context switch.*/\r
+ xSecureContextHandle->pucStackLimit = pucStackMemory;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ /* Store the correct CONTROL value for the task on the stack.\r
+ * This value is programmed in the CONTROL register on\r
+ * context switch. */\r
+ pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;\r
+ pulCurrentStackPointer--;\r
+ if( ulIsTaskPrivileged )\r
+ {\r
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;\r
+ }\r
+ else\r
+ {\r
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;\r
+ }\r
+\r
+ /* Store the current stack pointer. This value is programmed in\r
+ * the PSP register on context switch. */\r
+ xSecureContextHandle->pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;\r
+ }\r
+ #else /* configENABLE_MPU */\r
+ {\r
+ /* Current SP is set to the starting of the stack. This\r
+ * value programmed in the PSP register on context switch. */\r
+ xSecureContextHandle->pucCurrentStackPointer = xSecureContextHandle->pucStackStart;\r
+\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+ }\r
+ else\r
+ {\r
+ /* Free the context to avoid memory leak and make sure to return\r
+ * NULL to indicate failure. */\r
+ vPortFree( xSecureContextHandle );\r
+ xSecureContextHandle = NULL;\r
+ }\r
+ }\r
+ }\r
+\r
+ return xSecureContextHandle;\r
}\r
/*-----------------------------------------------------------*/\r
\r
secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle )\r
{\r
- uint32_t ulIPSR;\r
+ uint32_t ulIPSR;\r
\r
- /* Read the Interrupt Program Status Register (IPSR) value. */\r
- secureportREAD_IPSR( ulIPSR );\r
+ /* Read the Interrupt Program Status Register (IPSR) value. */\r
+ secureportREAD_IPSR( ulIPSR );\r
\r
- /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
- * when the processor is running in the Thread Mode. */\r
- if( ulIPSR != 0 )\r
- {\r
- /* Ensure that valid parameters are passed. */\r
- secureportASSERT( xSecureContextHandle != NULL );\r
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
+ * when the processor is running in the Thread Mode. */\r
+ if( ulIPSR != 0 )\r
+ {\r
+ /* Ensure that valid parameters are passed. */\r
+ secureportASSERT( xSecureContextHandle != NULL );\r
\r
- /* Free the stack space. */\r
- vPortFree( xSecureContextHandle->pucStackLimit );\r
+ /* Free the stack space. */\r
+ vPortFree( xSecureContextHandle->pucStackLimit );\r
\r
- /* Free the context itself. */\r
- vPortFree( xSecureContextHandle );\r
- }\r
+ /* Free the context itself. */\r
+ vPortFree( xSecureContextHandle );\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
/**\r
* @brief PSP value when no task's context is loaded.\r
*/\r
-#define securecontextNO_STACK 0x0\r
+#define securecontextNO_STACK 0x0\r
\r
/**\r
* @brief Opaque handle.\r
*/\r
struct SecureContext;\r
-typedef struct SecureContext* SecureContextHandle_t;\r
+typedef struct SecureContext* SecureContextHandle_t;\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* otherwise.\r
*/\r
#if( configENABLE_MPU == 1 )\r
- SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged );\r
+ SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged );\r
#else /* configENABLE_MPU */\r
- SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize );\r
+ SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize );\r
#endif /* configENABLE_MPU */\r
\r
/**\r
/**\r
* @brief Total heap size.\r
*/\r
-#define secureconfigTOTAL_HEAP_SIZE ( ( ( size_t ) ( 10 * 1024 ) ) )\r
+#define secureconfigTOTAL_HEAP_SIZE ( ( ( size_t ) ( 10 * 1024 ) ) )\r
\r
/* No test marker by default. */\r
#ifndef mtCOVERAGE_TEST_MARKER\r
- #define mtCOVERAGE_TEST_MARKER()\r
+ #define mtCOVERAGE_TEST_MARKER()\r
#endif\r
\r
/* No tracing by default. */\r
#ifndef traceMALLOC\r
- #define traceMALLOC( pvReturn, xWantedSize )\r
+ #define traceMALLOC( pvReturn, xWantedSize )\r
#endif\r
\r
/* No tracing by default. */\r
#ifndef traceFREE\r
- #define traceFREE( pv, xBlockSize )\r
+ #define traceFREE( pv, xBlockSize )\r
#endif\r
\r
/* Block sizes must not get too small. */\r
-#define secureheapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) )\r
+#define secureheapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) )\r
\r
/* Assumes 8bit bytes! */\r
-#define secureheapBITS_PER_BYTE ( ( size_t ) 8 )\r
+#define secureheapBITS_PER_BYTE ( ( size_t ) 8 )\r
/*-----------------------------------------------------------*/\r
\r
/* Allocate the memory for the heap. */\r
#if( configAPPLICATION_ALLOCATED_HEAP == 1 )\r
- /* The application writer has already defined the array used for the RTOS\r
- * heap - probably so it can be placed in a special segment or address. */\r
- extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];\r
+ /* The application writer has already defined the array used for the RTOS\r
+ * heap - probably so it can be placed in a special segment or address. */\r
+ extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];\r
#else /* configAPPLICATION_ALLOCATED_HEAP */\r
- static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];\r
+ static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];\r
#endif /* configAPPLICATION_ALLOCATED_HEAP */\r
\r
/**\r
*/\r
typedef struct A_BLOCK_LINK\r
{\r
- struct A_BLOCK_LINK *pxNextFreeBlock; /**< The next free block in the list. */\r
- size_t xBlockSize; /**< The size of the free block. */\r
+ struct A_BLOCK_LINK *pxNextFreeBlock; /**< The next free block in the list. */\r
+ size_t xBlockSize; /**< The size of the free block. */\r
} BlockLink_t;\r
/*-----------------------------------------------------------*/\r
\r
size_t uxAddress;\r
size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;\r
\r
- /* Ensure the heap starts on a correctly aligned boundary. */\r
- uxAddress = ( size_t ) ucHeap;\r
-\r
- if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )\r
- {\r
- uxAddress += ( secureportBYTE_ALIGNMENT - 1 );\r
- uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\r
- xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;\r
- }\r
-\r
- pucAlignedHeap = ( uint8_t * ) uxAddress;\r
-\r
- /* xStart is used to hold a pointer to the first item in the list of free\r
- * blocks. The void cast is used to prevent compiler warnings. */\r
- xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;\r
- xStart.xBlockSize = ( size_t ) 0;\r
-\r
- /* pxEnd is used to mark the end of the list of free blocks and is inserted\r
- * at the end of the heap space. */\r
- uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;\r
- uxAddress -= xHeapStructSize;\r
- uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\r
- pxEnd = ( void * ) uxAddress;\r
- pxEnd->xBlockSize = 0;\r
- pxEnd->pxNextFreeBlock = NULL;\r
-\r
- /* To start with there is a single free block that is sized to take up the\r
- * entire heap space, minus the space taken by pxEnd. */\r
- pxFirstFreeBlock = ( void * ) pucAlignedHeap;\r
- pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;\r
- pxFirstFreeBlock->pxNextFreeBlock = pxEnd;\r
-\r
- /* Only one block exists - and it covers the entire usable heap space. */\r
- xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;\r
- xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;\r
-\r
- /* Work out the position of the top bit in a size_t variable. */\r
- xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );\r
+ /* Ensure the heap starts on a correctly aligned boundary. */\r
+ uxAddress = ( size_t ) ucHeap;\r
+\r
+ if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )\r
+ {\r
+ uxAddress += ( secureportBYTE_ALIGNMENT - 1 );\r
+ uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\r
+ xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;\r
+ }\r
+\r
+ pucAlignedHeap = ( uint8_t * ) uxAddress;\r
+\r
+ /* xStart is used to hold a pointer to the first item in the list of free\r
+ * blocks. The void cast is used to prevent compiler warnings. */\r
+ xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;\r
+ xStart.xBlockSize = ( size_t ) 0;\r
+\r
+ /* pxEnd is used to mark the end of the list of free blocks and is inserted\r
+ * at the end of the heap space. */\r
+ uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;\r
+ uxAddress -= xHeapStructSize;\r
+ uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\r
+ pxEnd = ( void * ) uxAddress;\r
+ pxEnd->xBlockSize = 0;\r
+ pxEnd->pxNextFreeBlock = NULL;\r
+\r
+ /* To start with there is a single free block that is sized to take up the\r
+ * entire heap space, minus the space taken by pxEnd. */\r
+ pxFirstFreeBlock = ( void * ) pucAlignedHeap;\r
+ pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;\r
+ pxFirstFreeBlock->pxNextFreeBlock = pxEnd;\r
+\r
+ /* Only one block exists - and it covers the entire usable heap space. */\r
+ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;\r
+ xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;\r
+\r
+ /* Work out the position of the top bit in a size_t variable. */\r
+ xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );\r
}\r
/*-----------------------------------------------------------*/\r
\r
BlockLink_t *pxIterator;\r
uint8_t *puc;\r
\r
- /* Iterate through the list until a block is found that has a higher address\r
- * than the block being inserted. */\r
- for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )\r
- {\r
- /* Nothing to do here, just iterate to the right position. */\r
- }\r
-\r
- /* Do the block being inserted, and the block it is being inserted after\r
- * make a contiguous block of memory? */\r
- puc = ( uint8_t * ) pxIterator;\r
- if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )\r
- {\r
- pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;\r
- pxBlockToInsert = pxIterator;\r
- }\r
- else\r
- {\r
- mtCOVERAGE_TEST_MARKER();\r
- }\r
-\r
- /* Do the block being inserted, and the block it is being inserted before\r
- * make a contiguous block of memory? */\r
- puc = ( uint8_t * ) pxBlockToInsert;\r
- if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )\r
- {\r
- if( pxIterator->pxNextFreeBlock != pxEnd )\r
- {\r
- /* Form one big block from the two blocks. */\r
- pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;\r
- pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;\r
- }\r
- else\r
- {\r
- pxBlockToInsert->pxNextFreeBlock = pxEnd;\r
- }\r
- }\r
- else\r
- {\r
- pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;\r
- }\r
-\r
- /* If the block being inserted plugged a gab, so was merged with the block\r
- * before and the block after, then it's pxNextFreeBlock pointer will have\r
- * already been set, and should not be set here as that would make it point\r
- * to itself. */\r
- if( pxIterator != pxBlockToInsert )\r
- {\r
- pxIterator->pxNextFreeBlock = pxBlockToInsert;\r
- }\r
- else\r
- {\r
- mtCOVERAGE_TEST_MARKER();\r
- }\r
+ /* Iterate through the list until a block is found that has a higher address\r
+ * than the block being inserted. */\r
+ for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )\r
+ {\r
+ /* Nothing to do here, just iterate to the right position. */\r
+ }\r
+\r
+ /* Do the block being inserted, and the block it is being inserted after\r
+ * make a contiguous block of memory? */\r
+ puc = ( uint8_t * ) pxIterator;\r
+ if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )\r
+ {\r
+ pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;\r
+ pxBlockToInsert = pxIterator;\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+\r
+ /* Do the block being inserted, and the block it is being inserted before\r
+ * make a contiguous block of memory? */\r
+ puc = ( uint8_t * ) pxBlockToInsert;\r
+ if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )\r
+ {\r
+ if( pxIterator->pxNextFreeBlock != pxEnd )\r
+ {\r
+ /* Form one big block from the two blocks. */\r
+ pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;\r
+ pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;\r
+ }\r
+ else\r
+ {\r
+ pxBlockToInsert->pxNextFreeBlock = pxEnd;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;\r
+ }\r
+\r
+ /* If the block being inserted plugged a gab, so was merged with the block\r
+ * before and the block after, then it's pxNextFreeBlock pointer will have\r
+ * already been set, and should not be set here as that would make it point\r
+ * to itself. */\r
+ if( pxIterator != pxBlockToInsert )\r
+ {\r
+ pxIterator->pxNextFreeBlock = pxBlockToInsert;\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
\r
BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;\r
void *pvReturn = NULL;\r
\r
- /* If this is the first call to malloc then the heap will require\r
- * initialisation to setup the list of free blocks. */\r
- if( pxEnd == NULL )\r
- {\r
- prvHeapInit();\r
- }\r
- else\r
- {\r
- mtCOVERAGE_TEST_MARKER();\r
- }\r
-\r
- /* Check the requested block size is not so large that the top bit is set.\r
- * The top bit of the block size member of the BlockLink_t structure is used\r
- * to determine who owns the block - the application or the kernel, so it\r
- * must be free. */\r
- if( ( xWantedSize & xBlockAllocatedBit ) == 0 )\r
- {\r
- /* The wanted size is increased so it can contain a BlockLink_t\r
- * structure in addition to the requested amount of bytes. */\r
- if( xWantedSize > 0 )\r
- {\r
- xWantedSize += xHeapStructSize;\r
-\r
- /* Ensure that blocks are always aligned to the required number of\r
- * bytes. */\r
- if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )\r
- {\r
- /* Byte alignment required. */\r
- xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );\r
- secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );\r
- }\r
- else\r
- {\r
- mtCOVERAGE_TEST_MARKER();\r
- }\r
- }\r
- else\r
- {\r
- mtCOVERAGE_TEST_MARKER();\r
- }\r
-\r
- if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )\r
- {\r
- /* Traverse the list from the start (lowest address) block until\r
- * one of adequate size is found. */\r
- pxPreviousBlock = &xStart;\r
- pxBlock = xStart.pxNextFreeBlock;\r
- while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )\r
- {\r
- pxPreviousBlock = pxBlock;\r
- pxBlock = pxBlock->pxNextFreeBlock;\r
- }\r
-\r
- /* If the end marker was reached then a block of adequate size was\r
- * not found. */\r
- if( pxBlock != pxEnd )\r
- {\r
- /* Return the memory space pointed to - jumping over the\r
- * BlockLink_t structure at its start. */\r
- pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );\r
-\r
- /* This block is being returned for use so must be taken out\r
- * of the list of free blocks. */\r
- pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;\r
-\r
- /* If the block is larger than required it can be split into\r
- * two. */\r
- if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )\r
- {\r
- /* This block is to be split into two. Create a new\r
- * block following the number of bytes requested. The void\r
- * cast is used to prevent byte alignment warnings from the\r
- * compiler. */\r
- pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );\r
- secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );\r
-\r
- /* Calculate the sizes of two blocks split from the single\r
- * block. */\r
- pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;\r
- pxBlock->xBlockSize = xWantedSize;\r
-\r
- /* Insert the new block into the list of free blocks. */\r
- prvInsertBlockIntoFreeList( pxNewBlockLink );\r
- }\r
- else\r
- {\r
- mtCOVERAGE_TEST_MARKER();\r
- }\r
-\r
- xFreeBytesRemaining -= pxBlock->xBlockSize;\r
-\r
- if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )\r
- {\r
- xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;\r
- }\r
- else\r
- {\r
- mtCOVERAGE_TEST_MARKER();\r
- }\r
-\r
- /* The block is being returned - it is allocated and owned by\r
- * the application and has no "next" block. */\r
- pxBlock->xBlockSize |= xBlockAllocatedBit;\r
- pxBlock->pxNextFreeBlock = NULL;\r
- }\r
- else\r
- {\r
- mtCOVERAGE_TEST_MARKER();\r
- }\r
- }\r
- else\r
- {\r
- mtCOVERAGE_TEST_MARKER();\r
- }\r
- }\r
- else\r
- {\r
- mtCOVERAGE_TEST_MARKER();\r
- }\r
-\r
- traceMALLOC( pvReturn, xWantedSize );\r
-\r
- #if( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )\r
- {\r
- if( pvReturn == NULL )\r
- {\r
- extern void vApplicationMallocFailedHook( void );\r
- vApplicationMallocFailedHook();\r
- }\r
- else\r
- {\r
- mtCOVERAGE_TEST_MARKER();\r
- }\r
- }\r
- #endif\r
-\r
- secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );\r
- return pvReturn;\r
+ /* If this is the first call to malloc then the heap will require\r
+ * initialisation to setup the list of free blocks. */\r
+ if( pxEnd == NULL )\r
+ {\r
+ prvHeapInit();\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+\r
+ /* Check the requested block size is not so large that the top bit is set.\r
+ * The top bit of the block size member of the BlockLink_t structure is used\r
+ * to determine who owns the block - the application or the kernel, so it\r
+ * must be free. */\r
+ if( ( xWantedSize & xBlockAllocatedBit ) == 0 )\r
+ {\r
+ /* The wanted size is increased so it can contain a BlockLink_t\r
+ * structure in addition to the requested amount of bytes. */\r
+ if( xWantedSize > 0 )\r
+ {\r
+ xWantedSize += xHeapStructSize;\r
+\r
+ /* Ensure that blocks are always aligned to the required number of\r
+ * bytes. */\r
+ if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )\r
+ {\r
+ /* Byte alignment required. */\r
+ xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );\r
+ secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+\r
+ if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )\r
+ {\r
+ /* Traverse the list from the start (lowest address) block until\r
+ * one of adequate size is found. */\r
+ pxPreviousBlock = &xStart;\r
+ pxBlock = xStart.pxNextFreeBlock;\r
+ while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )\r
+ {\r
+ pxPreviousBlock = pxBlock;\r
+ pxBlock = pxBlock->pxNextFreeBlock;\r
+ }\r
+\r
+ /* If the end marker was reached then a block of adequate size was\r
+ * not found. */\r
+ if( pxBlock != pxEnd )\r
+ {\r
+ /* Return the memory space pointed to - jumping over the\r
+ * BlockLink_t structure at its start. */\r
+ pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );\r
+\r
+ /* This block is being returned for use so must be taken out\r
+ * of the list of free blocks. */\r
+ pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;\r
+\r
+ /* If the block is larger than required it can be split into\r
+ * two. */\r
+ if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )\r
+ {\r
+ /* This block is to be split into two. Create a new\r
+ * block following the number of bytes requested. The void\r
+ * cast is used to prevent byte alignment warnings from the\r
+ * compiler. */\r
+ pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );\r
+ secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );\r
+\r
+ /* Calculate the sizes of two blocks split from the single\r
+ * block. */\r
+ pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;\r
+ pxBlock->xBlockSize = xWantedSize;\r
+\r
+ /* Insert the new block into the list of free blocks. */\r
+ prvInsertBlockIntoFreeList( pxNewBlockLink );\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+\r
+ xFreeBytesRemaining -= pxBlock->xBlockSize;\r
+\r
+ if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )\r
+ {\r
+ xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+\r
+ /* The block is being returned - it is allocated and owned by\r
+ * the application and has no "next" block. */\r
+ pxBlock->xBlockSize |= xBlockAllocatedBit;\r
+ pxBlock->pxNextFreeBlock = NULL;\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+\r
+ traceMALLOC( pvReturn, xWantedSize );\r
+\r
+ #if( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )\r
+ {\r
+ if( pvReturn == NULL )\r
+ {\r
+ extern void vApplicationMallocFailedHook( void );\r
+ vApplicationMallocFailedHook();\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+ }\r
+ #endif\r
+\r
+ secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );\r
+ return pvReturn;\r
}\r
/*-----------------------------------------------------------*/\r
\r
uint8_t *puc = ( uint8_t * ) pv;\r
BlockLink_t *pxLink;\r
\r
- if( pv != NULL )\r
- {\r
- /* The memory being freed will have an BlockLink_t structure immediately\r
- * before it. */\r
- puc -= xHeapStructSize;\r
-\r
- /* This casting is to keep the compiler from issuing warnings. */\r
- pxLink = ( void * ) puc;\r
-\r
- /* Check the block is actually allocated. */\r
- secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );\r
- secureportASSERT( pxLink->pxNextFreeBlock == NULL );\r
-\r
- if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )\r
- {\r
- if( pxLink->pxNextFreeBlock == NULL )\r
- {\r
- /* The block is being returned to the heap - it is no longer\r
- * allocated. */\r
- pxLink->xBlockSize &= ~xBlockAllocatedBit;\r
-\r
- secureportDISABLE_NON_SECURE_INTERRUPTS();\r
- {\r
- /* Add this block to the list of free blocks. */\r
- xFreeBytesRemaining += pxLink->xBlockSize;\r
- traceFREE( pv, pxLink->xBlockSize );\r
- prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );\r
- }\r
- secureportENABLE_NON_SECURE_INTERRUPTS();\r
- }\r
- else\r
- {\r
- mtCOVERAGE_TEST_MARKER();\r
- }\r
- }\r
- else\r
- {\r
- mtCOVERAGE_TEST_MARKER();\r
- }\r
- }\r
+ if( pv != NULL )\r
+ {\r
+ /* The memory being freed will have an BlockLink_t structure immediately\r
+ * before it. */\r
+ puc -= xHeapStructSize;\r
+\r
+ /* This casting is to keep the compiler from issuing warnings. */\r
+ pxLink = ( void * ) puc;\r
+\r
+ /* Check the block is actually allocated. */\r
+ secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );\r
+ secureportASSERT( pxLink->pxNextFreeBlock == NULL );\r
+\r
+ if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )\r
+ {\r
+ if( pxLink->pxNextFreeBlock == NULL )\r
+ {\r
+ /* The block is being returned to the heap - it is no longer\r
+ * allocated. */\r
+ pxLink->xBlockSize &= ~xBlockAllocatedBit;\r
+\r
+ secureportDISABLE_NON_SECURE_INTERRUPTS();\r
+ {\r
+ /* Add this block to the list of free blocks. */\r
+ xFreeBytesRemaining += pxLink->xBlockSize;\r
+ traceFREE( pv, pxLink->xBlockSize );\r
+ prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );\r
+ }\r
+ secureportENABLE_NON_SECURE_INTERRUPTS();\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
\r
size_t xPortGetFreeHeapSize( void )\r
{\r
- return xFreeBytesRemaining;\r
+ return xFreeBytesRemaining;\r
}\r
/*-----------------------------------------------------------*/\r
\r
size_t xPortGetMinimumEverFreeHeapSize( void )\r
{\r
- return xMinimumEverFreeBytesRemaining;\r
+ return xMinimumEverFreeBytesRemaining;\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vPortInitialiseBlocks( void )\r
{\r
- /* This just exists to keep the linker quiet. */\r
+ /* This just exists to keep the linker quiet. */\r
}\r
/*-----------------------------------------------------------*/\r
/**\r
* @brief Constants required to manipulate the SCB.\r
*/\r
-#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */\r
-#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL )\r
-#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )\r
-#define secureinitSCB_AIRCR_PRIS_POS ( 14UL )\r
-#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS )\r
+#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */\r
+#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL )\r
+#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )\r
+#define secureinitSCB_AIRCR_PRIS_POS ( 14UL )\r
+#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS )\r
\r
/**\r
* @brief Constants required to manipulate the FPU.\r
*/\r
-#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */\r
-#define secureinitFPCCR_LSPENS_POS ( 29UL )\r
-#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS )\r
-#define secureinitFPCCR_TS_POS ( 26UL )\r
-#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS )\r
+#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */\r
+#define secureinitFPCCR_LSPENS_POS ( 29UL )\r
+#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS )\r
+#define secureinitFPCCR_TS_POS ( 26UL )\r
+#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS )\r
\r
-#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */\r
-#define secureinitNSACR_CP10_POS ( 10UL )\r
-#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS )\r
-#define secureinitNSACR_CP11_POS ( 11UL )\r
-#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS )\r
+#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */\r
+#define secureinitNSACR_CP10_POS ( 10UL )\r
+#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS )\r
+#define secureinitNSACR_CP11_POS ( 11UL )\r
+#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS )\r
/*-----------------------------------------------------------*/\r
\r
secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )\r
{\r
- uint32_t ulIPSR;\r
+ uint32_t ulIPSR;\r
\r
- /* Read the Interrupt Program Status Register (IPSR) value. */\r
- secureportREAD_IPSR( ulIPSR );\r
+ /* Read the Interrupt Program Status Register (IPSR) value. */\r
+ secureportREAD_IPSR( ulIPSR );\r
\r
- /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
- * when the processor is running in the Thread Mode. */\r
- if( ulIPSR != 0 )\r
- {\r
- *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |\r
- ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |\r
- ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK );\r
- }\r
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
+ * when the processor is running in the Thread Mode. */\r
+ if( ulIPSR != 0 )\r
+ {\r
+ *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |\r
+ ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |\r
+ ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK );\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
\r
secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )\r
{\r
- uint32_t ulIPSR;\r
+ uint32_t ulIPSR;\r
\r
- /* Read the Interrupt Program Status Register (IPSR) value. */\r
- secureportREAD_IPSR( ulIPSR );\r
+ /* Read the Interrupt Program Status Register (IPSR) value. */\r
+ secureportREAD_IPSR( ulIPSR );\r
\r
- /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
- * when the processor is running in the Thread Mode. */\r
- if( ulIPSR != 0 )\r
- {\r
- /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is\r
- * permitted. CP11 should be programmed to the same value as CP10. */\r
- *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );\r
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
+ * when the processor is running in the Thread Mode. */\r
+ if( ulIPSR != 0 )\r
+ {\r
+ /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is\r
+ * permitted. CP11 should be programmed to the same value as CP10. */\r
+ *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );\r
\r
- /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures\r
- * that we can enable/disable lazy stacking in port.c file. */\r
- *( secureinitFPCCR ) &= ~ ( secureinitFPCCR_LSPENS_MASK );\r
+ /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures\r
+ * that we can enable/disable lazy stacking in port.c file. */\r
+ *( secureinitFPCCR ) &= ~ ( secureinitFPCCR_LSPENS_MASK );\r
\r
- /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP\r
- * registers (S16-S31) are also pushed to stack on exception entry and\r
- * restored on exception return. */\r
- *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );\r
- }\r
+ /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP\r
+ * registers (S16-S31) are also pushed to stack on exception entry and\r
+ * restored on exception return. */\r
+ *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
/**\r
* @brief Byte alignment requirements.\r
*/\r
-#define secureportBYTE_ALIGNMENT 8\r
-#define secureportBYTE_ALIGNMENT_MASK ( 0x0007 )\r
+#define secureportBYTE_ALIGNMENT 8\r
+#define secureportBYTE_ALIGNMENT_MASK ( 0x0007 )\r
\r
/**\r
* @brief Macro to declare a function as non-secure callable.\r
*/\r
#if defined( __IAR_SYSTEMS_ICC__ )\r
- #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry\r
+ #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry\r
#else\r
- #define secureportNON_SECURE_CALLABLE __attribute__((cmse_nonsecure_entry))\r
+ #define secureportNON_SECURE_CALLABLE __attribute__((cmse_nonsecure_entry))\r
#endif\r
\r
/**\r
* @brief Set the secure PRIMASK value.\r
*/\r
#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \\r
- __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )\r
+ __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )\r
\r
/**\r
* @brief Set the non-secure PRIMASK value.\r
*/\r
#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \\r
- __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )\r
+ __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )\r
\r
/**\r
* @brief Read the PSP value in the given variable.\r
*/\r
#define secureportREAD_PSP( pucOutCurrentStackPointer ) \\r
- __asm volatile ( "mrs %0, psp" : "=r" ( pucOutCurrentStackPointer ) )\r
+ __asm volatile ( "mrs %0, psp" : "=r" ( pucOutCurrentStackPointer ) )\r
\r
/**\r
* @brief Set the PSP to the given value.\r
*/\r
#define secureportSET_PSP( pucCurrentStackPointer ) \\r
- __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )\r
+ __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )\r
\r
/**\r
* @brief Set the PSPLIM to the given value.\r
*/\r
#define secureportSET_PSPLIM( pucStackLimit ) \\r
- __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )\r
+ __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )\r
\r
/**\r
* @brief Set the NonSecure MSP to the given value.\r
*/\r
#define secureportSET_MSP_NS( pucMainStackPointer ) \\r
- __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )\r
+ __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )\r
\r
/**\r
* @brief Set the CONTROL register to the given value.\r
*/\r
#define secureportSET_CONTROL( ulControl ) \\r
- __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )\r
+ __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )\r
\r
/**\r
* @brief Read the Interrupt Program Status Register (IPSR) value in the given\r
* variable.\r
*/\r
#define secureportREAD_IPSR( ulIPSR ) \\r
- __asm volatile ( "mrs %0, ipsr" : "=r" ( ulIPSR ) )\r
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulIPSR ) )\r
\r
/**\r
* @brief PRIMASK value to enable interrupts.\r
*/\r
-#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL 0\r
+#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL 0\r
\r
/**\r
* @brief PRIMASK value to disable interrupts.\r
*/\r
-#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL 1\r
+#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL 1\r
\r
/**\r
* @brief Disable secure interrupts.\r
*/\r
-#define secureportDISABLE_SECURE_INTERRUPTS() secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )\r
+#define secureportDISABLE_SECURE_INTERRUPTS() secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )\r
\r
/**\r
* @brief Disable non-secure interrupts.\r
*\r
* This effectively disables context switches.\r
*/\r
-#define secureportDISABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )\r
+#define secureportDISABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )\r
\r
/**\r
* @brief Enable non-secure interrupts.\r
*/\r
-#define secureportENABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )\r
+#define secureportENABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )\r
\r
/**\r
* @brief Assert definition.\r
*/\r
-#define secureportASSERT( x ) \\r
- if( ( x ) == 0 ) \\r
- { \\r
- secureportDISABLE_SECURE_INTERRUPTS(); \\r
- secureportDISABLE_NON_SECURE_INTERRUPTS(); \\r
- for( ;; ); \\r
- }\r
+#define secureportASSERT( x ) \\r
+ if( ( x ) == 0 ) \\r
+ { \\r
+ secureportDISABLE_SECURE_INTERRUPTS(); \\r
+ secureportDISABLE_NON_SECURE_INTERRUPTS(); \\r
+ for( ;; ); \\r
+ }\r
\r
#endif /* __SECURE_PORT_MACROS_H__ */\r
#include "portasm.h"\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
- /* Secure components includes. */\r
- #include "secure_context.h"\r
- #include "secure_init.h"\r
+ /* Secure components includes. */\r
+ #include "secure_context.h"\r
+ #include "secure_init.h"\r
#endif /* configENABLE_TRUSTZONE */\r
\r
#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
+/**\r
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only\r
+ * i.e. the processor boots as secure and never jumps to the non-secure side.\r
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS\r
+ * on the secure side. The following are the valid configuration seetings:\r
+ *\r
+ * 1. Run FreeRTOS on the Secure Side:\r
+ * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0\r
+ *\r
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:\r
+ * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1\r
+ *\r
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:\r
+ * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0\r
+ */\r
+#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )\r
+ #error Trust Zone needs to be disabled in order to run FreeRTOS on the Secure Side.\r
+#endif\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Constants required to manipulate the NVIC.\r
*/\r
-#define portNVIC_SYSTICK_CTRL ( ( volatile uint32_t * ) 0xe000e010 )\r
-#define portNVIC_SYSTICK_LOAD ( ( volatile uint32_t * ) 0xe000e014 )\r
-#define portNVIC_SYSTICK_CURRENT_VALUE ( ( volatile uint32_t * ) 0xe000e018 )\r
-#define portNVIC_INT_CTRL ( ( volatile uint32_t * ) 0xe000ed04 )\r
-#define portNVIC_SYSPRI2 ( ( volatile uint32_t * ) 0xe000ed20 )\r
-#define portNVIC_SYSTICK_CLK ( 0x00000004 )\r
-#define portNVIC_SYSTICK_INT ( 0x00000002 )\r
-#define portNVIC_SYSTICK_ENABLE ( 0x00000001 )\r
-#define portNVIC_PENDSVSET ( 0x10000000 )\r
-#define portMIN_INTERRUPT_PRIORITY ( 255UL )\r
-#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )\r
-#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )\r
+#define portNVIC_SYSTICK_CTRL ( ( volatile uint32_t * ) 0xe000e010 )\r
+#define portNVIC_SYSTICK_LOAD ( ( volatile uint32_t * ) 0xe000e014 )\r
+#define portNVIC_SYSTICK_CURRENT_VALUE ( ( volatile uint32_t * ) 0xe000e018 )\r
+#define portNVIC_INT_CTRL ( ( volatile uint32_t * ) 0xe000ed04 )\r
+#define portNVIC_SYSPRI2 ( ( volatile uint32_t * ) 0xe000ed20 )\r
+#define portNVIC_SYSTICK_CLK ( 0x00000004 )\r
+#define portNVIC_SYSTICK_INT ( 0x00000002 )\r
+#define portNVIC_SYSTICK_ENABLE ( 0x00000001 )\r
+#define portNVIC_PENDSVSET ( 0x10000000 )\r
+#define portMIN_INTERRUPT_PRIORITY ( 255UL )\r
+#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )\r
+#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Constants required to manipulate the SCB.\r
*/\r
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( * ( volatile uint32_t * ) 0xe000ed24 )\r
-#define portSCB_MEM_FAULT_ENABLE ( 1UL << 16UL )\r
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( * ( volatile uint32_t * ) 0xe000ed24 )\r
+#define portSCB_MEM_FAULT_ENABLE ( 1UL << 16UL )\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Constants required to manipulate the FPU.\r
*/\r
-#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */\r
-#define portCPACR_CP10_VALUE ( 3UL )\r
-#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE\r
-#define portCPACR_CP10_POS ( 20UL )\r
-#define portCPACR_CP11_POS ( 22UL )\r
-\r
-#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */\r
-#define portFPCCR_ASPEN_POS ( 31UL )\r
-#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS )\r
-#define portFPCCR_LSPEN_POS ( 30UL )\r
-#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS )\r
+#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */\r
+#define portCPACR_CP10_VALUE ( 3UL )\r
+#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE\r
+#define portCPACR_CP10_POS ( 20UL )\r
+#define portCPACR_CP11_POS ( 22UL )\r
+\r
+#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */\r
+#define portFPCCR_ASPEN_POS ( 31UL )\r
+#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS )\r
+#define portFPCCR_LSPEN_POS ( 30UL )\r
+#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS )\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Constants required to manipulate the MPU.\r
*/\r
-#define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )\r
-#define portMPU_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )\r
-#define portMPU_RNR_REG ( * ( ( volatile uint32_t * ) 0xe000ed98 ) )\r
+#define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )\r
+#define portMPU_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )\r
+#define portMPU_RNR_REG ( * ( ( volatile uint32_t * ) 0xe000ed98 ) )\r
\r
-#define portMPU_RBAR_REG ( * ( ( volatile uint32_t * ) 0xe000ed9c ) )\r
-#define portMPU_RLAR_REG ( * ( ( volatile uint32_t * ) 0xe000eda0 ) )\r
+#define portMPU_RBAR_REG ( * ( ( volatile uint32_t * ) 0xe000ed9c ) )\r
+#define portMPU_RLAR_REG ( * ( ( volatile uint32_t * ) 0xe000eda0 ) )\r
\r
-#define portMPU_RBAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda4 ) )\r
-#define portMPU_RLAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda8 ) )\r
+#define portMPU_RBAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda4 ) )\r
+#define portMPU_RLAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda8 ) )\r
\r
-#define portMPU_RBAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edac ) )\r
-#define portMPU_RLAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edb0 ) )\r
+#define portMPU_RBAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edac ) )\r
+#define portMPU_RLAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edb0 ) )\r
\r
-#define portMPU_RBAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb4 ) )\r
-#define portMPU_RLAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb8 ) )\r
+#define portMPU_RBAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb4 ) )\r
+#define portMPU_RLAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb8 ) )\r
\r
-#define portMPU_MAIR0_REG ( * ( ( volatile uint32_t * ) 0xe000edc0 ) )\r
-#define portMPU_MAIR1_REG ( * ( ( volatile uint32_t * ) 0xe000edc4 ) )\r
+#define portMPU_MAIR0_REG ( * ( ( volatile uint32_t * ) 0xe000edc0 ) )\r
+#define portMPU_MAIR1_REG ( * ( ( volatile uint32_t * ) 0xe000edc4 ) )\r
\r
-#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
-#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
+#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
+#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
\r
-#define portMPU_MAIR_ATTR0_POS ( 0UL )\r
-#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )\r
+#define portMPU_MAIR_ATTR0_POS ( 0UL )\r
+#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )\r
\r
-#define portMPU_MAIR_ATTR1_POS ( 8UL )\r
-#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )\r
+#define portMPU_MAIR_ATTR1_POS ( 8UL )\r
+#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )\r
\r
-#define portMPU_MAIR_ATTR2_POS ( 16UL )\r
-#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )\r
+#define portMPU_MAIR_ATTR2_POS ( 16UL )\r
+#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )\r
\r
-#define portMPU_MAIR_ATTR3_POS ( 24UL )\r
-#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )\r
+#define portMPU_MAIR_ATTR3_POS ( 24UL )\r
+#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )\r
\r
-#define portMPU_MAIR_ATTR4_POS ( 0UL )\r
-#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )\r
+#define portMPU_MAIR_ATTR4_POS ( 0UL )\r
+#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )\r
\r
-#define portMPU_MAIR_ATTR5_POS ( 8UL )\r
-#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )\r
+#define portMPU_MAIR_ATTR5_POS ( 8UL )\r
+#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )\r
\r
-#define portMPU_MAIR_ATTR6_POS ( 16UL )\r
-#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )\r
+#define portMPU_MAIR_ATTR6_POS ( 16UL )\r
+#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )\r
\r
-#define portMPU_MAIR_ATTR7_POS ( 24UL )\r
-#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )\r
+#define portMPU_MAIR_ATTR7_POS ( 24UL )\r
+#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )\r
\r
-#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )\r
-#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )\r
-#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )\r
-#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )\r
-#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )\r
-#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )\r
-#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )\r
-#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )\r
\r
-#define portMPU_RLAR_REGION_ENABLE ( 1UL )\r
+#define portMPU_RLAR_REGION_ENABLE ( 1UL )\r
\r
/* Enable privileged access to unmapped region. */\r
-#define portMPU_PRIV_BACKGROUND_ENABLE ( 1UL << 2UL )\r
+#define portMPU_PRIV_BACKGROUND_ENABLE ( 1UL << 2UL )\r
\r
/* Enable MPU. */\r
-#define portMPU_ENABLE ( 1UL << 0UL )\r
+#define portMPU_ENABLE ( 1UL << 0UL )\r
\r
/* Expected value of the portMPU_TYPE register. */\r
-#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */\r
+#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Constants required to set up the initial stack.\r
*/\r
-#define portINITIAL_XPSR ( 0x01000000 )\r
-\r
-/**\r
- * @brief Initial EXC_RETURN value.\r
- *\r
- * FF FF FF BC\r
- * 1111 1111 1111 1111 1111 1111 1011 1100\r
- *\r
- * Bit[6] - 0 --> The exception was taken from the Non-Secure state.\r
- * Bit[5] - 1 --> Do not skip stacking of additional state context.\r
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\r
- * Bit[3] - 1 --> Return to the Thread mode.\r
- * Bit[2] - 1 --> Restore registers from the process stack.\r
- * Bit[1] - 0 --> Reserved, 0.\r
- * Bit[0] - 0 --> The exception was taken to the Non-Secure state.\r
- */\r
-#define portINITIAL_EXC_RETURN ( 0xffffffbc )\r
+#define portINITIAL_XPSR ( 0x01000000 )\r
+\r
+#if( configRUN_FREERTOS_SECURE_ONLY == 1 )\r
+ /**\r
+ * @brief Initial EXC_RETURN value.\r
+ *\r
+ * FF FF FF FD\r
+ * 1111 1111 1111 1111 1111 1111 1111 1101\r
+ *\r
+ * Bit[6] - 1 --> The exception was taken from the Secure state.\r
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.\r
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\r
+ * Bit[3] - 1 --> Return to the Thread mode.\r
+ * Bit[2] - 1 --> Restore registers from the process stack.\r
+ * Bit[1] - 0 --> Reserved, 0.\r
+ * Bit[0] - 1 --> The exception was taken to the Secure state.\r
+ */\r
+ #define portINITIAL_EXC_RETURN ( 0xfffffffd )\r
+#else\r
+ /**\r
+ * @brief Initial EXC_RETURN value.\r
+ *\r
+ * FF FF FF BC\r
+ * 1111 1111 1111 1111 1111 1111 1011 1100\r
+ *\r
+ * Bit[6] - 0 --> The exception was taken from the Non-Secure state.\r
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.\r
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\r
+ * Bit[3] - 1 --> Return to the Thread mode.\r
+ * Bit[2] - 1 --> Restore registers from the process stack.\r
+ * Bit[1] - 0 --> Reserved, 0.\r
+ * Bit[0] - 0 --> The exception was taken to the Non-Secure state.\r
+ */\r
+ #define portINITIAL_EXC_RETURN ( 0xffffffbc )\r
+#endif /* configRUN_FREERTOS_SECURE_ONLY */\r
\r
/**\r
* @brief CONTROL register privileged bit mask.\r
* Bit[0] = 0 ==> The task is privileged.\r
* Bit[0] = 1 ==> The task is not privileged.\r
*/\r
-#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL )\r
+#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL )\r
\r
/**\r
* @brief Initial CONTROL register values.\r
*/\r
-#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 )\r
-#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 )\r
+#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 )\r
+#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 )\r
\r
/**\r
* @brief Let the user override the pre-loading of the initial LR with the\r
* in the debugger.\r
*/\r
#ifdef configTASK_RETURN_ADDRESS\r
- #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS\r
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS\r
#else\r
- #define portTASK_RETURN_ADDRESS prvTaskExitError\r
+ #define portTASK_RETURN_ADDRESS prvTaskExitError\r
#endif\r
\r
/**\r
* @brief If portPRELOAD_REGISTERS then registers will be given an initial value\r
* when a task is created. This helps in debugging at the cost of code size.\r
*/\r
-#define portPRELOAD_REGISTERS 1\r
+#define portPRELOAD_REGISTERS 1\r
\r
/**\r
* @brief A task is created without a secure context, and must call\r
* portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes\r
* any secure calls.\r
*/\r
-#define portNO_SECURE_CONTEXT 0\r
+#define portNO_SECURE_CONTEXT 0\r
/*-----------------------------------------------------------*/\r
\r
/**\r
static void prvTaskExitError( void );\r
\r
#if( configENABLE_MPU == 1 )\r
- /**\r
- * @brief Setup the Memory Protection Unit (MPU).\r
- */\r
- static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\r
+ /**\r
+ * @brief Setup the Memory Protection Unit (MPU).\r
+ */\r
+ static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\r
#endif /* configENABLE_MPU */\r
\r
#if( configENABLE_FPU == 1 )\r
- /**\r
- * @brief Setup the Floating Point Unit (FPU).\r
- */\r
- static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\r
+ /**\r
+ * @brief Setup the Floating Point Unit (FPU).\r
+ */\r
+ static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\r
#endif /* configENABLE_FPU */\r
\r
/**\r
static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
- /**\r
- * @brief Saved as part of the task context to indicate which context the\r
- * task is using on the secure side.\r
- */\r
- volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\r
+ /**\r
+ * @brief Saved as part of the task context to indicate which context the\r
+ * task is using on the secure side.\r
+ */\r
+ volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\r
#endif /* configENABLE_TRUSTZONE */\r
/*-----------------------------------------------------------*/\r
\r
static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\r
{\r
- /* Stop and reset the SysTick. */\r
- *( portNVIC_SYSTICK_CTRL ) = 0UL;\r
- *( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;\r
+ /* Stop and reset the SysTick. */\r
+ *( portNVIC_SYSTICK_CTRL ) = 0UL;\r
+ *( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;\r
\r
- /* Configure SysTick to interrupt at the requested rate. */\r
- *( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
- *( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
+ /* Configure SysTick to interrupt at the requested rate. */\r
+ *( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
+ *( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
}\r
/*-----------------------------------------------------------*/\r
\r
{\r
volatile uint32_t ulDummy = 0UL;\r
\r
- /* A function that implements a task must not exit or attempt to return to\r
- * its caller as there is nothing to return to. If a task wants to exit it\r
- * should instead call vTaskDelete( NULL ). Artificially force an assert()\r
- * to be triggered if configASSERT() is defined, then stop here so\r
- * application writers can catch the error. */\r
- configASSERT( ulCriticalNesting == ~0UL );\r
- portDISABLE_INTERRUPTS();\r
-\r
- while( ulDummy == 0 )\r
- {\r
- /* This file calls prvTaskExitError() after the scheduler has been\r
- * started to remove a compiler warning about the function being\r
- * defined but never called. ulDummy is used purely to quieten other\r
- * warnings about code appearing after this function is called - making\r
- * ulDummy volatile makes the compiler think the function could return\r
- * and therefore not output an 'unreachable code' warning for code that\r
- * appears after it. */\r
- }\r
+ /* A function that implements a task must not exit or attempt to return to\r
+ * its caller as there is nothing to return to. If a task wants to exit it\r
+ * should instead call vTaskDelete( NULL ). Artificially force an assert()\r
+ * to be triggered if configASSERT() is defined, then stop here so\r
+ * application writers can catch the error. */\r
+ configASSERT( ulCriticalNesting == ~0UL );\r
+ portDISABLE_INTERRUPTS();\r
+\r
+ while( ulDummy == 0 )\r
+ {\r
+ /* This file calls prvTaskExitError() after the scheduler has been\r
+ * started to remove a compiler warning about the function being\r
+ * defined but never called. ulDummy is used purely to quieten other\r
+ * warnings about code appearing after this function is called - making\r
+ * ulDummy volatile makes the compiler think the function could return\r
+ * and therefore not output an 'unreachable code' warning for code that\r
+ * appears after it. */\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
\r
#if( configENABLE_MPU == 1 )\r
- static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */\r
- {\r
- #if defined( __ARMCC_VERSION )\r
- /* Declaration when these variable are defined in code instead of being\r
- * exported from linker scripts. */\r
- extern uint32_t * __privileged_functions_start__;\r
- extern uint32_t * __privileged_functions_end__;\r
- extern uint32_t * __syscalls_flash_start__;\r
- extern uint32_t * __unprivileged_flash_end__;\r
- extern uint32_t * __privileged_sram_start__;\r
- extern uint32_t * __privileged_sram_end__;\r
- #else\r
- /* Declaration when these variable are exported from linker scripts. */\r
- extern uint32_t __privileged_functions_start__[];\r
- extern uint32_t __privileged_functions_end__[];\r
- extern uint32_t __syscalls_flash_start__[];\r
- extern uint32_t __unprivileged_flash_end__[];\r
- extern uint32_t __privileged_sram_start__[];\r
- extern uint32_t __privileged_sram_end__[];\r
- #endif /* defined( __ARMCC_VERSION ) */\r
-\r
- /* Check that the MPU is present. */\r
- if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\r
- {\r
- /* MAIR0 - Index 0. */\r
- portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
- /* MAIR0 - Index 1. */\r
- portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
-\r
- /* Setup privileged flash as Read Only so that privileged tasks can\r
- * read it but not modify. */\r
- portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;\r
- portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
- ( portMPU_REGION_NON_SHAREABLE ) |\r
- ( portMPU_REGION_PRIVILEGED_READ_ONLY );\r
- portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
- ( portMPU_RLAR_ATTR_INDEX0 ) |\r
- ( portMPU_RLAR_REGION_ENABLE );\r
-\r
- /* Setup unprivileged flash and system calls flash as Read Only by\r
- * both privileged and unprivileged tasks. All tasks can read it but\r
- * no-one can modify. */\r
- portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;\r
- portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
- ( portMPU_REGION_NON_SHAREABLE ) |\r
- ( portMPU_REGION_READ_ONLY );\r
- portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
- ( portMPU_RLAR_ATTR_INDEX0 ) |\r
- ( portMPU_RLAR_REGION_ENABLE );\r
-\r
- /* Setup RAM containing kernel data for privileged access only. */\r
- portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;\r
- portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
- ( portMPU_REGION_NON_SHAREABLE ) |\r
- ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
- ( portMPU_REGION_EXECUTE_NEVER );\r
- portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
- ( portMPU_RLAR_ATTR_INDEX0 ) |\r
- ( portMPU_RLAR_REGION_ENABLE );\r
-\r
- /* By default allow everything to access the general peripherals.\r
- * The system peripherals and registers are protected. */\r
- portMPU_RNR_REG = portUNPRIVILEGED_DEVICE_REGION;\r
- portMPU_RBAR_REG = ( ( ( uint32_t ) portDEVICE_REGION_START_ADDRESS ) & portMPU_RBAR_ADDRESS_MASK ) |\r
- ( portMPU_REGION_NON_SHAREABLE ) |\r
- ( portMPU_REGION_READ_WRITE ) |\r
- ( portMPU_REGION_EXECUTE_NEVER );\r
- portMPU_RLAR_REG = ( ( ( uint32_t ) portDEVICE_REGION_END_ADDRESS ) & portMPU_RLAR_ADDRESS_MASK ) |\r
- ( portMPU_RLAR_ATTR_INDEX1 ) |\r
- ( portMPU_RLAR_REGION_ENABLE );\r
-\r
- /* Enable mem fault. */\r
- portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;\r
-\r
- /* Enable MPU with privileged background access i.e. unmapped\r
- * regions have privileged access. */\r
- portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );\r
- }\r
- }\r
+ static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */\r
+ {\r
+ #if defined( __ARMCC_VERSION )\r
+ /* Declaration when these variable are defined in code instead of being\r
+ * exported from linker scripts. */\r
+ extern uint32_t * __privileged_functions_start__;\r
+ extern uint32_t * __privileged_functions_end__;\r
+ extern uint32_t * __syscalls_flash_start__;\r
+ extern uint32_t * __unprivileged_flash_end__;\r
+ extern uint32_t * __privileged_sram_start__;\r
+ extern uint32_t * __privileged_sram_end__;\r
+ #else\r
+ /* Declaration when these variable are exported from linker scripts. */\r
+ extern uint32_t __privileged_functions_start__[];\r
+ extern uint32_t __privileged_functions_end__[];\r
+ extern uint32_t __syscalls_flash_start__[];\r
+ extern uint32_t __unprivileged_flash_end__[];\r
+ extern uint32_t __privileged_sram_start__[];\r
+ extern uint32_t __privileged_sram_end__[];\r
+ #endif /* defined( __ARMCC_VERSION ) */\r
+\r
+ /* Check that the MPU is present. */\r
+ if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\r
+ {\r
+ /* MAIR0 - Index 0. */\r
+ portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
+ /* MAIR0 - Index 1. */\r
+ portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
+\r
+ /* Setup privileged flash as Read Only so that privileged tasks can\r
+ * read it but not modify. */\r
+ portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_PRIVILEGED_READ_ONLY );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Setup unprivileged flash and system calls flash as Read Only by\r
+ * both privileged and unprivileged tasks. All tasks can read it but\r
+ * no-one can modify. */\r
+ portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_ONLY );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Setup RAM containing kernel data for privileged access only. */\r
+ portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
+ ( portMPU_REGION_EXECUTE_NEVER );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* By default allow everything to access the general peripherals.\r
+ * The system peripherals and registers are protected. */\r
+ portMPU_RNR_REG = portUNPRIVILEGED_DEVICE_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) portDEVICE_REGION_START_ADDRESS ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_WRITE ) |\r
+ ( portMPU_REGION_EXECUTE_NEVER );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) portDEVICE_REGION_END_ADDRESS ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX1 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Enable mem fault. */\r
+ portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;\r
+\r
+ /* Enable MPU with privileged background access i.e. unmapped\r
+ * regions have privileged access. */\r
+ portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );\r
+ }\r
+ }\r
#endif /* configENABLE_MPU */\r
/*-----------------------------------------------------------*/\r
\r
#if( configENABLE_FPU == 1 )\r
- static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */\r
- {\r
- #if( configENABLE_TRUSTZONE == 1 )\r
- {\r
- /* Enable non-secure access to the FPU. */\r
- SecureInit_EnableNSFPUAccess();\r
- }\r
- #endif /* configENABLE_TRUSTZONE */\r
-\r
- /* CP10 = 11 ==> Full access to FPU i.e. both privileged and\r
- * unprivileged code should be able to access FPU. CP11 should be\r
- * programmed to the same value as CP10. */\r
- *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |\r
- ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )\r
- );\r
-\r
- /* ASPEN = 1 ==> Hardware should automatically preserve floating point\r
- * context on exception entry and restore on exception return.\r
- * LSPEN = 1 ==> Enable lazy context save of FP state. */\r
- *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );\r
- }\r
+ static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */\r
+ {\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ /* Enable non-secure access to the FPU. */\r
+ SecureInit_EnableNSFPUAccess();\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+\r
+ /* CP10 = 11 ==> Full access to FPU i.e. both privileged and\r
+ * unprivileged code should be able to access FPU. CP11 should be\r
+ * programmed to the same value as CP10. */\r
+ *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |\r
+ ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )\r
+ );\r
+\r
+ /* ASPEN = 1 ==> Hardware should automatically preserve floating point\r
+ * context on exception entry and restore on exception return.\r
+ * LSPEN = 1 ==> Enable lazy context save of FP state. */\r
+ *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );\r
+ }\r
#endif /* configENABLE_FPU */\r
/*-----------------------------------------------------------*/\r
\r
void vPortYield( void ) /* PRIVILEGED_FUNCTION */\r
{\r
- /* Set a PendSV to request a context switch. */\r
- *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
+ /* Set a PendSV to request a context switch. */\r
+ *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
\r
- /* Barriers are normally not required but do ensure the code is\r
- * completely within the specified behaviour for the architecture. */\r
- __asm volatile( "dsb" ::: "memory" );\r
- __asm volatile( "isb" );\r
+ /* Barriers are normally not required but do ensure the code is\r
+ * completely within the specified behaviour for the architecture. */\r
+ __asm volatile( "dsb" ::: "memory" );\r
+ __asm volatile( "isb" );\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */\r
{\r
- portDISABLE_INTERRUPTS();\r
- ulCriticalNesting++;\r
+ portDISABLE_INTERRUPTS();\r
+ ulCriticalNesting++;\r
\r
- /* Barriers are normally not required but do ensure the code is\r
- * completely within the specified behaviour for the architecture. */\r
- __asm volatile( "dsb" ::: "memory" );\r
- __asm volatile( "isb" );\r
+ /* Barriers are normally not required but do ensure the code is\r
+ * completely within the specified behaviour for the architecture. */\r
+ __asm volatile( "dsb" ::: "memory" );\r
+ __asm volatile( "isb" );\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */\r
{\r
- configASSERT( ulCriticalNesting );\r
- ulCriticalNesting--;\r
+ configASSERT( ulCriticalNesting );\r
+ ulCriticalNesting--;\r
\r
- if( ulCriticalNesting == 0 )\r
- {\r
- portENABLE_INTERRUPTS();\r
- }\r
+ if( ulCriticalNesting == 0 )\r
+ {\r
+ portENABLE_INTERRUPTS();\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
\r
{\r
uint32_t ulPreviousMask;\r
\r
- ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();\r
- {\r
- /* Increment the RTOS tick. */\r
- if( xTaskIncrementTick() != pdFALSE )\r
- {\r
- /* Pend a context switch. */\r
- *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
- }\r
- }\r
- portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );\r
+ ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();\r
+ {\r
+ /* Increment the RTOS tick. */\r
+ if( xTaskIncrementTick() != pdFALSE )\r
+ {\r
+ /* Pend a context switch. */\r
+ *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
+ }\r
+ }\r
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION */\r
{\r
#if( configENABLE_MPU == 1 )\r
- #if defined( __ARMCC_VERSION )\r
- /* Declaration when these variable are defined in code instead of being\r
- * exported from linker scripts. */\r
- extern uint32_t * __syscalls_flash_start__;\r
- extern uint32_t * __syscalls_flash_end__;\r
- #else\r
- /* Declaration when these variable are exported from linker scripts. */\r
- extern uint32_t __syscalls_flash_start__[];\r
- extern uint32_t __syscalls_flash_end__[];\r
- #endif /* defined( __ARMCC_VERSION ) */\r
+ #if defined( __ARMCC_VERSION )\r
+ /* Declaration when these variable are defined in code instead of being\r
+ * exported from linker scripts. */\r
+ extern uint32_t * __syscalls_flash_start__;\r
+ extern uint32_t * __syscalls_flash_end__;\r
+ #else\r
+ /* Declaration when these variable are exported from linker scripts. */\r
+ extern uint32_t __syscalls_flash_start__[];\r
+ extern uint32_t __syscalls_flash_end__[];\r
+ #endif /* defined( __ARMCC_VERSION ) */\r
#endif /* configENABLE_MPU */\r
\r
uint32_t ulPC;\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
- uint32_t ulR0;\r
- #if( configENABLE_MPU == 1 )\r
- uint32_t ulControl, ulIsTaskPrivileged;\r
- #endif /* configENABLE_MPU */\r
+ uint32_t ulR0;\r
+ #if( configENABLE_MPU == 1 )\r
+ uint32_t ulControl, ulIsTaskPrivileged;\r
+ #endif /* configENABLE_MPU */\r
#endif /* configENABLE_TRUSTZONE */\r
uint8_t ucSVCNumber;\r
\r
- /* Register are stored on the stack in the following order - R0, R1, R2, R3,\r
- * R12, LR, PC, xPSR. */\r
- ulPC = pulCallerStackAddress[ 6 ];\r
- ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];\r
-\r
- switch( ucSVCNumber )\r
- {\r
- #if( configENABLE_TRUSTZONE == 1 )\r
- case portSVC_ALLOCATE_SECURE_CONTEXT:\r
- {\r
- /* R0 contains the stack size passed as parameter to the\r
- * vPortAllocateSecureContext function. */\r
- ulR0 = pulCallerStackAddress[ 0 ];\r
-\r
- #if( configENABLE_MPU == 1 )\r
- {\r
- /* Read the CONTROL register value. */\r
- __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );\r
-\r
- /* The task that raised the SVC is privileged if Bit[0]\r
- * in the CONTROL register is 0. */\r
- ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );\r
-\r
- /* Allocate and load a context for the secure task. */\r
- xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );\r
- }\r
- #else\r
- {\r
- /* Allocate and load a context for the secure task. */\r
- xSecureContext = SecureContext_AllocateContext( ulR0 );\r
- }\r
- #endif /* configENABLE_MPU */\r
-\r
- configASSERT( xSecureContext != NULL );\r
- SecureContext_LoadContext( xSecureContext );\r
- }\r
- break;\r
-\r
- case portSVC_FREE_SECURE_CONTEXT:\r
- {\r
- /* R0 contains the secure context handle to be freed. */\r
- ulR0 = pulCallerStackAddress[ 0 ];\r
-\r
- /* Free the secure context. */\r
- SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );\r
- }\r
- break;\r
- #endif /* configENABLE_TRUSTZONE */\r
-\r
- case portSVC_START_SCHEDULER:\r
- {\r
- #if( configENABLE_TRUSTZONE == 1 )\r
- {\r
- /* De-prioritize the non-secure exceptions so that the\r
- * non-secure pendSV runs at the lowest priority. */\r
- SecureInit_DePrioritizeNSExceptions();\r
-\r
- /* Initialize the secure context management system. */\r
- SecureContext_Init();\r
- }\r
- #endif /* configENABLE_TRUSTZONE */\r
-\r
- #if( configENABLE_FPU == 1 )\r
- {\r
- /* Setup the Floating Point Unit (FPU). */\r
- prvSetupFPU();\r
- }\r
- #endif /* configENABLE_FPU */\r
-\r
- /* Setup the context of the first task so that the first task starts\r
- * executing. */\r
- vRestoreContextOfFirstTask();\r
- }\r
- break;\r
-\r
- #if( configENABLE_MPU == 1 )\r
- case portSVC_RAISE_PRIVILEGE:\r
- {\r
- /* Only raise the privilege, if the svc was raised from any of\r
- * the system calls. */\r
- if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&\r
- ulPC <= ( uint32_t ) __syscalls_flash_end__ )\r
- {\r
- vRaisePrivilege();\r
- }\r
- }\r
- break;\r
- #endif /* configENABLE_MPU */\r
-\r
- default:\r
- {\r
- /* Incorrect SVC call. */\r
- configASSERT( pdFALSE );\r
- }\r
- }\r
+ /* Register are stored on the stack in the following order - R0, R1, R2, R3,\r
+ * R12, LR, PC, xPSR. */\r
+ ulPC = pulCallerStackAddress[ 6 ];\r
+ ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];\r
+\r
+ switch( ucSVCNumber )\r
+ {\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ case portSVC_ALLOCATE_SECURE_CONTEXT:\r
+ {\r
+ /* R0 contains the stack size passed as parameter to the\r
+ * vPortAllocateSecureContext function. */\r
+ ulR0 = pulCallerStackAddress[ 0 ];\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ /* Read the CONTROL register value. */\r
+ __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );\r
+\r
+ /* The task that raised the SVC is privileged if Bit[0]\r
+ * in the CONTROL register is 0. */\r
+ ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );\r
+\r
+ /* Allocate and load a context for the secure task. */\r
+ xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );\r
+ }\r
+ #else\r
+ {\r
+ /* Allocate and load a context for the secure task. */\r
+ xSecureContext = SecureContext_AllocateContext( ulR0 );\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ configASSERT( xSecureContext != NULL );\r
+ SecureContext_LoadContext( xSecureContext );\r
+ }\r
+ break;\r
+\r
+ case portSVC_FREE_SECURE_CONTEXT:\r
+ {\r
+ /* R0 contains the secure context handle to be freed. */\r
+ ulR0 = pulCallerStackAddress[ 0 ];\r
+\r
+ /* Free the secure context. */\r
+ SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );\r
+ }\r
+ break;\r
+ #endif /* configENABLE_TRUSTZONE */\r
+\r
+ case portSVC_START_SCHEDULER:\r
+ {\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ /* De-prioritize the non-secure exceptions so that the\r
+ * non-secure pendSV runs at the lowest priority. */\r
+ SecureInit_DePrioritizeNSExceptions();\r
+\r
+ /* Initialize the secure context management system. */\r
+ SecureContext_Init();\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+\r
+ #if( configENABLE_FPU == 1 )\r
+ {\r
+ /* Setup the Floating Point Unit (FPU). */\r
+ prvSetupFPU();\r
+ }\r
+ #endif /* configENABLE_FPU */\r
+\r
+ /* Setup the context of the first task so that the first task starts\r
+ * executing. */\r
+ vRestoreContextOfFirstTask();\r
+ }\r
+ break;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ case portSVC_RAISE_PRIVILEGE:\r
+ {\r
+ /* Only raise the privilege, if the svc was raised from any of\r
+ * the system calls. */\r
+ if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&\r
+ ulPC <= ( uint32_t ) __syscalls_flash_end__ )\r
+ {\r
+ vRaisePrivilege();\r
+ }\r
+ }\r
+ break;\r
+ #endif /* configENABLE_MPU */\r
+\r
+ default:\r
+ {\r
+ /* Incorrect SVC call. */\r
+ configASSERT( pdFALSE );\r
+ }\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
\r
#if( configENABLE_MPU == 1 )\r
- StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */\r
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */\r
#else\r
- StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */\r
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */\r
#endif /* configENABLE_MPU */\r
{\r
- /* Simulate the stack frame as it would be created by a context switch\r
- * interrupt. */\r
- #if( portPRELOAD_REGISTERS == 0 )\r
- {\r
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
- *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\r
- pxTopOfStack -= 5; /* R12, R3, R2 and R1. */\r
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
- pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */\r
- *pxTopOfStack = portINITIAL_EXC_RETURN;\r
-\r
- #if( configENABLE_MPU == 1 )\r
- {\r
- pxTopOfStack--;\r
- if( xRunPrivileged == pdTRUE )\r
- {\r
- *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
- }\r
- else\r
- {\r
- *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
- }\r
- }\r
- #endif /* configENABLE_MPU */\r
-\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\r
-\r
- #if( configENABLE_TRUSTZONE == 1 )\r
- {\r
- pxTopOfStack--;\r
- *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\r
- }\r
- #endif /* configENABLE_TRUSTZONE */\r
- }\r
- #else /* portPRELOAD_REGISTERS */\r
- {\r
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
- *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */\r
-\r
- #if( configENABLE_MPU == 1 )\r
- {\r
- pxTopOfStack--;\r
- if( xRunPrivileged == pdTRUE )\r
- {\r
- *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
- }\r
- else\r
- {\r
- *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
- }\r
- }\r
- #endif /* configENABLE_MPU */\r
-\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\r
-\r
- #if( configENABLE_TRUSTZONE == 1 )\r
- {\r
- pxTopOfStack--;\r
- *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\r
- }\r
- #endif /* configENABLE_TRUSTZONE */\r
- }\r
- #endif /* portPRELOAD_REGISTERS */\r
-\r
- return pxTopOfStack;\r
+ /* Simulate the stack frame as it would be created by a context switch\r
+ * interrupt. */\r
+ #if( portPRELOAD_REGISTERS == 0 )\r
+ {\r
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\r
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */\r
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
+ pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */\r
+ *pxTopOfStack = portINITIAL_EXC_RETURN;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ if( xRunPrivileged == pdTRUE )\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ else\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\r
+\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+ }\r
+ #else /* portPRELOAD_REGISTERS */\r
+ {\r
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ if( xRunPrivileged == pdTRUE )\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ else\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\r
+\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+ }\r
+ #endif /* portPRELOAD_REGISTERS */\r
+\r
+ return pxTopOfStack;\r
}\r
/*-----------------------------------------------------------*/\r
\r
BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */\r
{\r
- /* Make PendSV, CallSV and SysTick the same priority as the kernel. */\r
- *( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;\r
- *( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;\r
-\r
- #if( configENABLE_MPU == 1 )\r
- {\r
- /* Setup the Memory Protection Unit (MPU). */\r
- prvSetupMPU();\r
- }\r
- #endif /* configENABLE_MPU */\r
-\r
- /* Start the timer that generates the tick ISR. Interrupts are disabled\r
- * here already. */\r
- prvSetupTimerInterrupt();\r
-\r
- /* Initialize the critical nesting count ready for the first task. */\r
- ulCriticalNesting = 0;\r
-\r
- /* Start the first task. */\r
- vStartFirstTask();\r
-\r
- /* Should never get here as the tasks will now be executing. Call the task\r
- * exit error function to prevent compiler warnings about a static function\r
- * not being called in the case that the application writer overrides this\r
- * functionality by defining configTASK_RETURN_ADDRESS. Call\r
- * vTaskSwitchContext() so link time optimization does not remove the\r
- * symbol. */\r
- vTaskSwitchContext();\r
- prvTaskExitError();\r
-\r
- /* Should not get here. */\r
- return 0;\r
+ /* Make PendSV, CallSV and SysTick the same priority as the kernel. */\r
+ *( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;\r
+ *( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ /* Setup the Memory Protection Unit (MPU). */\r
+ prvSetupMPU();\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ /* Start the timer that generates the tick ISR. Interrupts are disabled\r
+ * here already. */\r
+ prvSetupTimerInterrupt();\r
+\r
+ /* Initialize the critical nesting count ready for the first task. */\r
+ ulCriticalNesting = 0;\r
+\r
+ /* Start the first task. */\r
+ vStartFirstTask();\r
+\r
+ /* Should never get here as the tasks will now be executing. Call the task\r
+ * exit error function to prevent compiler warnings about a static function\r
+ * not being called in the case that the application writer overrides this\r
+ * functionality by defining configTASK_RETURN_ADDRESS. Call\r
+ * vTaskSwitchContext() so link time optimization does not remove the\r
+ * symbol. */\r
+ vTaskSwitchContext();\r
+ prvTaskExitError();\r
+\r
+ /* Should not get here. */\r
+ return 0;\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */\r
{\r
- /* Not implemented in ports where there is nothing to return to.\r
- * Artificially force an assert. */\r
- configASSERT( ulCriticalNesting == 1000UL );\r
+ /* Not implemented in ports where there is nothing to return to.\r
+ * Artificially force an assert. */\r
+ configASSERT( ulCriticalNesting == 1000UL );\r
}\r
/*-----------------------------------------------------------*/\r
\r
#if( configENABLE_MPU == 1 )\r
- void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )\r
- {\r
- uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;\r
- int32_t lIndex = 0;\r
-\r
- /* Setup MAIR0. */\r
- xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
- xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
-\r
- /* This function is called automatically when the task is created - in\r
- * which case the stack region parameters will be valid. At all other\r
- * times the stack parameters will not be valid and it is assumed that\r
- * the stack region has already been configured. */\r
- if( ulStackDepth > 0 )\r
- {\r
- /* Define the region that allows access to the stack. */\r
- ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;\r
- ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;\r
- ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\r
-\r
- xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |\r
- ( portMPU_REGION_NON_SHAREABLE ) |\r
- ( portMPU_REGION_READ_WRITE ) |\r
- ( portMPU_REGION_EXECUTE_NEVER );\r
-\r
- xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |\r
- ( portMPU_RLAR_ATTR_INDEX0 ) |\r
- ( portMPU_RLAR_REGION_ENABLE );\r
- }\r
-\r
- /* User supplied configurable regions. */\r
- for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )\r
- {\r
- /* If xRegions is NULL i.e. the task has not specified any MPU\r
- * region, the else part ensures that all the configurable MPU\r
- * regions are invalidated. */\r
- if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )\r
- {\r
- /* Translate the generic region definition contained in xRegions\r
- * into the ARMv8 specific MPU settings that are then stored in\r
- * xMPUSettings. */\r
- ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;\r
- ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;\r
- ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\r
-\r
- /* Start address. */\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |\r
- ( portMPU_REGION_NON_SHAREABLE );\r
-\r
- /* RO/RW. */\r
- if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )\r
- {\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );\r
- }\r
- else\r
- {\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );\r
- }\r
-\r
- /* XN. */\r
- if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )\r
- {\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );\r
- }\r
-\r
- /* End Address. */\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |\r
- ( portMPU_RLAR_REGION_ENABLE );\r
-\r
- /* Normal memory/ Device memory. */\r
- if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )\r
- {\r
- /* Attr1 in MAIR0 is configured as device memory. */\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;\r
- }\r
- else\r
- {\r
- /* Attr1 in MAIR0 is configured as normal memory. */\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;\r
- }\r
- }\r
- else\r
- {\r
- /* Invalidate the region. */\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;\r
- }\r
-\r
- lIndex++;\r
- }\r
- }\r
+ void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )\r
+ {\r
+ uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;\r
+ int32_t lIndex = 0;\r
+\r
+ /* Setup MAIR0. */\r
+ xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
+ xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
+\r
+ /* This function is called automatically when the task is created - in\r
+ * which case the stack region parameters will be valid. At all other\r
+ * times the stack parameters will not be valid and it is assumed that\r
+ * the stack region has already been configured. */\r
+ if( ulStackDepth > 0 )\r
+ {\r
+ /* Define the region that allows access to the stack. */\r
+ ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;\r
+ ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;\r
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\r
+\r
+ xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_WRITE ) |\r
+ ( portMPU_REGION_EXECUTE_NEVER );\r
+\r
+ xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+ }\r
+\r
+ /* User supplied configurable regions. */\r
+ for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )\r
+ {\r
+ /* If xRegions is NULL i.e. the task has not specified any MPU\r
+ * region, the else part ensures that all the configurable MPU\r
+ * regions are invalidated. */\r
+ if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )\r
+ {\r
+ /* Translate the generic region definition contained in xRegions\r
+ * into the ARMv8 specific MPU settings that are then stored in\r
+ * xMPUSettings. */\r
+ ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;\r
+ ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;\r
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\r
+\r
+ /* Start address. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |\r
+ ( portMPU_REGION_NON_SHAREABLE );\r
+\r
+ /* RO/RW. */\r
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )\r
+ {\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );\r
+ }\r
+ else\r
+ {\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );\r
+ }\r
+\r
+ /* XN. */\r
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )\r
+ {\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );\r
+ }\r
+\r
+ /* End Address. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Normal memory/ Device memory. */\r
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )\r
+ {\r
+ /* Attr1 in MAIR0 is configured as device memory. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;\r
+ }\r
+ else\r
+ {\r
+ /* Attr1 in MAIR0 is configured as normal memory. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Invalidate the region. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;\r
+ }\r
+\r
+ lIndex++;\r
+ }\r
+ }\r
#endif /* configENABLE_MPU */\r
/*-----------------------------------------------------------*/\r
\r
void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
{\r
- __asm volatile\r
- (\r
- " .syntax unified \n"\r
- " \n"\r
- " ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
- " ldr r3, [r2] \n" /* Read pxCurrentTCB. */\r
- " ldr r0, [r3] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
- " \n"\r
- #if( configENABLE_MPU == 1 )\r
- " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
- " ldr r4, [r3] \n" /* r4 = *r3 i.e. r4 = MAIR0. */\r
- " ldr r2, xMAIR0Const2 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
- " str r4, [r2] \n" /* Program MAIR0. */\r
- " ldr r2, xRNRConst2 \n" /* r2 = 0xe000ed98 [Location of RNR]. */\r
- " movs r4, #4 \n" /* r4 = 4. */\r
- " str r4, [r2] \n" /* Program RNR = 4. */\r
- " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\r
- " ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */\r
- " ldmia r3!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */\r
- " stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
- #endif /* configENABLE_MPU */\r
- " \n"\r
- #if( configENABLE_MPU == 1 )\r
- " ldm r0!, {r1-r4} \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */\r
- " ldr r5, xSecureContextConst2 \n"\r
- " str r1, [r5] \n" /* Set xSecureContext to this task's value for the same. */\r
- " msr psplim, r2 \n" /* Set this task's PSPLIM value. */\r
- " msr control, r3 \n" /* Set this task's CONTROL value. */\r
- " adds r0, #32 \n" /* Discard everything up to r0. */\r
- " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */\r
- " isb \n"\r
- " bx r4 \n" /* Finally, branch to EXC_RETURN. */\r
- #else /* configENABLE_MPU */\r
- " ldm r0!, {r1-r3} \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */\r
- " ldr r4, xSecureContextConst2 \n"\r
- " str r1, [r4] \n" /* Set xSecureContext to this task's value for the same. */\r
- " msr psplim, r2 \n" /* Set this task's PSPLIM value. */\r
- " movs r1, #2 \n" /* r1 = 2. */\r
- " msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */\r
- " adds r0, #32 \n" /* Discard everything up to r0. */\r
- " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */\r
- " isb \n"\r
- " bx r3 \n" /* Finally, branch to EXC_RETURN. */\r
- #endif /* configENABLE_MPU */\r
- " \n"\r
- " .align 4 \n"\r
- "pxCurrentTCBConst2: .word pxCurrentTCB \n"\r
- "xSecureContextConst2: .word xSecureContext \n"\r
- #if( configENABLE_MPU == 1 )\r
- "xMAIR0Const2: .word 0xe000edc0 \n"\r
- "xRNRConst2: .word 0xe000ed98 \n"\r
- "xRBARConst2: .word 0xe000ed9c \n"\r
- #endif /* configENABLE_MPU */\r
- );\r
+ __asm volatile\r
+ (\r
+ " .syntax unified \n"\r
+ " \n"\r
+ " ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ " ldr r3, [r2] \n" /* Read pxCurrentTCB. */\r
+ " ldr r0, [r3] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
+ " ldr r4, [r3] \n" /* r4 = *r3 i.e. r4 = MAIR0. */\r
+ " ldr r2, xMAIR0Const2 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ " str r4, [r2] \n" /* Program MAIR0. */\r
+ " ldr r2, xRNRConst2 \n" /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ " movs r4, #4 \n" /* r4 = 4. */\r
+ " str r4, [r2] \n" /* Program RNR = 4. */\r
+ " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\r
+ " ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */\r
+ " ldmia r3!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */\r
+ " stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " ldm r0!, {r1-r4} \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */\r
+ " ldr r5, xSecureContextConst2 \n"\r
+ " str r1, [r5] \n" /* Set xSecureContext to this task's value for the same. */\r
+ " msr psplim, r2 \n" /* Set this task's PSPLIM value. */\r
+ " msr control, r3 \n" /* Set this task's CONTROL value. */\r
+ " adds r0, #32 \n" /* Discard everything up to r0. */\r
+ " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */\r
+ " isb \n"\r
+ " bx r4 \n" /* Finally, branch to EXC_RETURN. */\r
+ #else /* configENABLE_MPU */\r
+ " ldm r0!, {r1-r3} \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */\r
+ " ldr r4, xSecureContextConst2 \n"\r
+ " str r1, [r4] \n" /* Set xSecureContext to this task's value for the same. */\r
+ " msr psplim, r2 \n" /* Set this task's PSPLIM value. */\r
+ " movs r1, #2 \n" /* r1 = 2. */\r
+ " msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */\r
+ " adds r0, #32 \n" /* Discard everything up to r0. */\r
+ " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */\r
+ " isb \n"\r
+ " bx r3 \n" /* Finally, branch to EXC_RETURN. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ " .align 4 \n"\r
+ "pxCurrentTCBConst2: .word pxCurrentTCB \n"\r
+ "xSecureContextConst2: .word xSecureContext \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ "xMAIR0Const2: .word 0xe000edc0 \n"\r
+ "xRNRConst2: .word 0xe000ed98 \n"\r
+ "xRBARConst2: .word 0xe000ed9c \n"\r
+ #endif /* configENABLE_MPU */\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
\r
BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */\r
{\r
- __asm volatile\r
- (\r
- " mrs r0, control \n" /* r0 = CONTROL. */\r
- " tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\r
- " ite ne \n"\r
- " movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
- " moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\r
- " bx lr \n" /* Return. */\r
- " \n"\r
- " .align 4 \n"\r
- ::: "r0", "memory"\r
- );\r
+ __asm volatile\r
+ (\r
+ " mrs r0, control \n" /* r0 = CONTROL. */\r
+ " tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\r
+ " ite ne \n"\r
+ " movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
+ " moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\r
+ " bx lr \n" /* Return. */\r
+ " \n"\r
+ " .align 4 \n"\r
+ ::: "r0", "memory"\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
{\r
- __asm volatile\r
- (\r
- " mrs r0, control \n" /* Read the CONTROL register. */\r
- " bic r0, #1 \n" /* Clear the bit 0. */\r
- " msr control, r0 \n" /* Write back the new CONTROL value. */\r
- " bx lr \n" /* Return to the caller. */\r
- ::: "r0", "memory"\r
- );\r
+ __asm volatile\r
+ (\r
+ " mrs r0, control \n" /* Read the CONTROL register. */\r
+ " bic r0, #1 \n" /* Clear the bit 0. */\r
+ " msr control, r0 \n" /* Write back the new CONTROL value. */\r
+ " bx lr \n" /* Return to the caller. */\r
+ ::: "r0", "memory"\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vResetPrivilege( void ) /* __attribute__ (( naked )) */\r
{\r
- __asm volatile\r
- (\r
- " mrs r0, control \n" /* r0 = CONTROL. */\r
- " orr r0, #1 \n" /* r0 = r0 | 1. */\r
- " msr control, r0 \n" /* CONTROL = r0. */\r
- " bx lr \n" /* Return to the caller. */\r
- :::"r0", "memory"\r
- );\r
+ __asm volatile\r
+ (\r
+ " mrs r0, control \n" /* r0 = CONTROL. */\r
+ " orr r0, #1 \n" /* r0 = r0 | 1. */\r
+ " msr control, r0 \n" /* CONTROL = r0. */\r
+ " bx lr \n" /* Return to the caller. */\r
+ :::"r0", "memory"\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
{\r
- __asm volatile\r
- (\r
- " ldr r0, xVTORConst \n" /* Use the NVIC offset register to locate the stack. */\r
- " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */\r
- " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */\r
- " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */\r
- " cpsie i \n" /* Globally enable interrupts. */\r
- " cpsie f \n"\r
- " dsb \n"\r
- " isb \n"\r
- " svc %0 \n" /* System call to start the first task. */\r
- " nop \n"\r
- " \n"\r
- " .align 4 \n"\r
- "xVTORConst: .word 0xe000ed08 \n"\r
- :: "i" ( portSVC_START_SCHEDULER ) : "memory"\r
- );\r
+ __asm volatile\r
+ (\r
+ " ldr r0, xVTORConst \n" /* Use the NVIC offset register to locate the stack. */\r
+ " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */\r
+ " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */\r
+ " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */\r
+ " cpsie i \n" /* Globally enable interrupts. */\r
+ " cpsie f \n"\r
+ " dsb \n"\r
+ " isb \n"\r
+ " svc %0 \n" /* System call to start the first task. */\r
+ " nop \n"\r
+ " \n"\r
+ " .align 4 \n"\r
+ "xVTORConst: .word 0xe000ed08 \n"\r
+ :: "i" ( portSVC_START_SCHEDULER ) : "memory"\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
\r
uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
{\r
- __asm volatile\r
- (\r
- " mrs r0, PRIMASK \n"\r
- " cpsid i \n"\r
- " bx lr \n"\r
- ::: "memory"\r
- );\r
+ __asm volatile\r
+ (\r
+ " mrs r0, PRIMASK \n"\r
+ " cpsid i \n"\r
+ " bx lr \n"\r
+ ::: "memory"\r
+ );\r
\r
#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- /* To avoid compiler warnings. The return statement will never be reached,\r
- * but some compilers warn if it is not included, while others won't compile\r
- * if it is. */\r
- return 0;\r
+ /* To avoid compiler warnings. The return statement will never be reached,\r
+ * but some compilers warn if it is not included, while others won't compile\r
+ * if it is. */\r
+ return 0;\r
#endif\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
{\r
- __asm volatile\r
- (\r
- " msr PRIMASK, r0 \n"\r
- " bx lr \n"\r
- ::: "memory"\r
- );\r
+ __asm volatile\r
+ (\r
+ " msr PRIMASK, r0 \n"\r
+ " bx lr \n"\r
+ ::: "memory"\r
+ );\r
\r
#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- /* Just to avoid compiler warning. ulMask is used from the asm code but\r
- * the compiler can't see that. Some compilers generate warnings without\r
- * the following line, while others generate warnings if the line is\r
- * included. */\r
- ( void ) ulMask;\r
+ /* Just to avoid compiler warning. ulMask is used from the asm code but\r
+ * the compiler can't see that. Some compilers generate warnings without\r
+ * the following line, while others generate warnings if the line is\r
+ * included. */\r
+ ( void ) ulMask;\r
#endif\r
}\r
/*-----------------------------------------------------------*/\r
\r
void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
{\r
- __asm volatile\r
- (\r
- " .syntax unified \n"\r
- " .extern SecureContext_SaveContext \n"\r
- " .extern SecureContext_LoadContext \n"\r
- " \n"\r
- " mrs r1, psp \n" /* Read PSP in r1. */\r
- " ldr r2, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
- " ldr r0, [r2] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */\r
- " \n"\r
- " cbz r0, save_ns_context \n" /* No secure context to save. */\r
- " push {r0-r2, r14} \n"\r
- " bl SecureContext_SaveContext \n"\r
- " pop {r0-r3} \n" /* LR is now in r3. */\r
- " mov lr, r3 \n" /* LR = r3. */\r
- " lsls r2, r3, #25 \n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
- " bpl save_ns_context \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
- " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
- " ldr r2, [r3] \n" /* Read pxCurrentTCB. */\r
- #if( configENABLE_MPU == 1 )\r
- " subs r1, r1, #16 \n" /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
- " str r1, [r2] \n" /* Save the new top of stack in TCB. */\r
- " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
- " mrs r3, control \n" /* r3 = CONTROL. */\r
- " mov r4, lr \n" /* r4 = LR/EXC_RETURN. */\r
- " stmia r1!, {r0, r2-r4} \n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
- #else /* configENABLE_MPU */\r
- " subs r1, r1, #12 \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */\r
- " str r1, [r2] \n" /* Save the new top of stack in TCB. */\r
- " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
- " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */\r
- " stmia r1!, {r0, r2-r3} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */\r
- #endif /* configENABLE_MPU */\r
- " b select_next_task \n"\r
- " \n"\r
- " save_ns_context: \n"\r
- " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
- " ldr r2, [r3] \n" /* Read pxCurrentTCB. */\r
- #if( configENABLE_FPU == 1 )\r
- " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
- " it eq \n"\r
- " vstmdbeq r1!, {s16-s31} \n" /* Store the FPU registers which are not saved automatically. */\r
- #endif /* configENABLE_FPU */\r
- #if( configENABLE_MPU == 1 )\r
- " subs r1, r1, #48 \n" /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */\r
- " str r1, [r2] \n" /* Save the new top of stack in TCB. */\r
- " adds r1, r1, #16 \n" /* r1 = r1 + 16. */\r
- " stm r1, {r4-r11} \n" /* Store the registers that are not saved automatically. */\r
- " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
- " mrs r3, control \n" /* r3 = CONTROL. */\r
- " mov r4, lr \n" /* r4 = LR/EXC_RETURN. */\r
- " subs r1, r1, #16 \n" /* r1 = r1 - 16. */\r
- " stm r1, {r0, r2-r4} \n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
- #else /* configENABLE_MPU */\r
- " subs r1, r1, #44 \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */\r
- " str r1, [r2] \n" /* Save the new top of stack in TCB. */\r
- " adds r1, r1, #12 \n" /* r1 = r1 + 12. */\r
- " stm r1, {r4-r11} \n" /* Store the registers that are not saved automatically. */\r
- " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
- " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */\r
- " subs r1, r1, #12 \n" /* r1 = r1 - 12. */\r
- " stmia r1!, {r0, r2-r3} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */\r
- #endif /* configENABLE_MPU */\r
- " \n"\r
- " select_next_task: \n"\r
- " cpsid i \n"\r
- " bl vTaskSwitchContext \n"\r
- " cpsie i \n"\r
- " \n"\r
- " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
- " ldr r3, [r2] \n" /* Read pxCurrentTCB. */\r
- " ldr r1, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */\r
- " \n"\r
- #if( configENABLE_MPU == 1 )\r
- " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
- " ldr r4, [r3] \n" /* r4 = *r3 i.e. r4 = MAIR0. */\r
- " ldr r2, xMAIR0Const \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
- " str r4, [r2] \n" /* Program MAIR0. */\r
- " ldr r2, xRNRConst \n" /* r2 = 0xe000ed98 [Location of RNR]. */\r
- " movs r4, #4 \n" /* r4 = 4. */\r
- " str r4, [r2] \n" /* Program RNR = 4. */\r
- " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\r
- " ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */\r
- " ldmia r3!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
- " stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
- #endif /* configENABLE_MPU */\r
- " \n"\r
- #if( configENABLE_MPU == 1 )\r
- " ldmia r1!, {r0, r2-r4} \n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */\r
- " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */\r
- " msr control, r3 \n" /* Restore the CONTROL register value for the task. */\r
- " mov lr, r4 \n" /* LR = r4. */\r
- " ldr r2, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
- " str r0, [r2] \n" /* Restore the task's xSecureContext. */\r
- " cbz r0, restore_ns_context \n" /* If there is no secure context for the task, restore the non-secure context. */\r
- " push {r1,r4} \n"\r
- " bl SecureContext_LoadContext \n" /* Restore the secure context. */\r
- " pop {r1,r4} \n"\r
- " mov lr, r4 \n" /* LR = r4. */\r
- " lsls r2, r4, #25 \n" /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
- " bpl restore_ns_context \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
- " msr psp, r1 \n" /* Remember the new top of stack for the task. */\r
- " bx lr \n"\r
- #else /* configENABLE_MPU */\r
- " ldmia r1!, {r0, r2-r3} \n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */\r
- " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */\r
- " mov lr, r3 \n" /* LR = r3. */\r
- " ldr r2, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
- " str r0, [r2] \n" /* Restore the task's xSecureContext. */\r
- " cbz r0, restore_ns_context \n" /* If there is no secure context for the task, restore the non-secure context. */\r
- " push {r1,r3} \n"\r
- " bl SecureContext_LoadContext \n" /* Restore the secure context. */\r
- " pop {r1,r3} \n"\r
- " mov lr, r3 \n" /* LR = r3. */\r
- " lsls r2, r3, #25 \n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
- " bpl restore_ns_context \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
- " msr psp, r1 \n" /* Remember the new top of stack for the task. */\r
- " bx lr \n"\r
- #endif /* configENABLE_MPU */\r
- " \n"\r
- " restore_ns_context: \n"\r
- " ldmia r1!, {r4-r11} \n" /* Restore the registers that are not automatically restored. */\r
- #if( configENABLE_FPU == 1 )\r
- " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
- " it eq \n"\r
- " vldmiaeq r1!, {s16-s31} \n" /* Restore the FPU registers which are not restored automatically. */\r
- #endif /* configENABLE_FPU */\r
- " msr psp, r1 \n" /* Remember the new top of stack for the task. */\r
- " bx lr \n"\r
- " \n"\r
- " .align 4 \n"\r
- "pxCurrentTCBConst: .word pxCurrentTCB \n"\r
- "xSecureContextConst: .word xSecureContext \n"\r
- #if( configENABLE_MPU == 1 )\r
- "xMAIR0Const: .word 0xe000edc0 \n"\r
- "xRNRConst: .word 0xe000ed98 \n"\r
- "xRBARConst: .word 0xe000ed9c \n"\r
- #endif /* configENABLE_MPU */\r
- );\r
+ __asm volatile\r
+ (\r
+ " .syntax unified \n"\r
+ " .extern SecureContext_SaveContext \n"\r
+ " .extern SecureContext_LoadContext \n"\r
+ " \n"\r
+ " mrs r1, psp \n" /* Read PSP in r1. */\r
+ " ldr r2, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
+ " ldr r0, [r2] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */\r
+ " \n"\r
+ " cbz r0, save_ns_context \n" /* No secure context to save. */\r
+ " push {r0-r2, r14} \n"\r
+ " bl SecureContext_SaveContext \n"\r
+ " pop {r0-r3} \n" /* LR is now in r3. */\r
+ " mov lr, r3 \n" /* LR = r3. */\r
+ " lsls r2, r3, #25 \n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
+ " bpl save_ns_context \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
+ " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ " ldr r2, [r3] \n" /* Read pxCurrentTCB. */\r
+ #if( configENABLE_MPU == 1 )\r
+ " subs r1, r1, #16 \n" /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
+ " str r1, [r2] \n" /* Save the new top of stack in TCB. */\r
+ " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
+ " mrs r3, control \n" /* r3 = CONTROL. */\r
+ " mov r4, lr \n" /* r4 = LR/EXC_RETURN. */\r
+ " stmia r1!, {r0, r2-r4} \n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
+ #else /* configENABLE_MPU */\r
+ " subs r1, r1, #12 \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */\r
+ " str r1, [r2] \n" /* Save the new top of stack in TCB. */\r
+ " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
+ " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */\r
+ " stmia r1!, {r0, r2-r3} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */\r
+ #endif /* configENABLE_MPU */\r
+ " b select_next_task \n"\r
+ " \n"\r
+ " save_ns_context: \n"\r
+ " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ " ldr r2, [r3] \n" /* Read pxCurrentTCB. */\r
+ #if( configENABLE_FPU == 1 )\r
+ " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
+ " it eq \n"\r
+ " vstmdbeq r1!, {s16-s31} \n" /* Store the FPU registers which are not saved automatically. */\r
+ #endif /* configENABLE_FPU */\r
+ #if( configENABLE_MPU == 1 )\r
+ " subs r1, r1, #48 \n" /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */\r
+ " str r1, [r2] \n" /* Save the new top of stack in TCB. */\r
+ " adds r1, r1, #16 \n" /* r1 = r1 + 16. */\r
+ " stm r1, {r4-r11} \n" /* Store the registers that are not saved automatically. */\r
+ " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
+ " mrs r3, control \n" /* r3 = CONTROL. */\r
+ " mov r4, lr \n" /* r4 = LR/EXC_RETURN. */\r
+ " subs r1, r1, #16 \n" /* r1 = r1 - 16. */\r
+ " stm r1, {r0, r2-r4} \n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
+ #else /* configENABLE_MPU */\r
+ " subs r1, r1, #44 \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */\r
+ " str r1, [r2] \n" /* Save the new top of stack in TCB. */\r
+ " adds r1, r1, #12 \n" /* r1 = r1 + 12. */\r
+ " stm r1, {r4-r11} \n" /* Store the registers that are not saved automatically. */\r
+ " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
+ " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */\r
+ " subs r1, r1, #12 \n" /* r1 = r1 - 12. */\r
+ " stmia r1!, {r0, r2-r3} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ " select_next_task: \n"\r
+ " cpsid i \n"\r
+ " bl vTaskSwitchContext \n"\r
+ " cpsie i \n"\r
+ " \n"\r
+ " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ " ldr r3, [r2] \n" /* Read pxCurrentTCB. */\r
+ " ldr r1, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
+ " ldr r4, [r3] \n" /* r4 = *r3 i.e. r4 = MAIR0. */\r
+ " ldr r2, xMAIR0Const \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ " str r4, [r2] \n" /* Program MAIR0. */\r
+ " ldr r2, xRNRConst \n" /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ " movs r4, #4 \n" /* r4 = 4. */\r
+ " str r4, [r2] \n" /* Program RNR = 4. */\r
+ " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\r
+ " ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */\r
+ " ldmia r3!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
+ " stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " ldmia r1!, {r0, r2-r4} \n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */\r
+ " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */\r
+ " msr control, r3 \n" /* Restore the CONTROL register value for the task. */\r
+ " mov lr, r4 \n" /* LR = r4. */\r
+ " ldr r2, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
+ " str r0, [r2] \n" /* Restore the task's xSecureContext. */\r
+ " cbz r0, restore_ns_context \n" /* If there is no secure context for the task, restore the non-secure context. */\r
+ " push {r1,r4} \n"\r
+ " bl SecureContext_LoadContext \n" /* Restore the secure context. */\r
+ " pop {r1,r4} \n"\r
+ " mov lr, r4 \n" /* LR = r4. */\r
+ " lsls r2, r4, #25 \n" /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
+ " bpl restore_ns_context \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
+ " msr psp, r1 \n" /* Remember the new top of stack for the task. */\r
+ " bx lr \n"\r
+ #else /* configENABLE_MPU */\r
+ " ldmia r1!, {r0, r2-r3} \n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */\r
+ " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */\r
+ " mov lr, r3 \n" /* LR = r3. */\r
+ " ldr r2, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
+ " str r0, [r2] \n" /* Restore the task's xSecureContext. */\r
+ " cbz r0, restore_ns_context \n" /* If there is no secure context for the task, restore the non-secure context. */\r
+ " push {r1,r3} \n"\r
+ " bl SecureContext_LoadContext \n" /* Restore the secure context. */\r
+ " pop {r1,r3} \n"\r
+ " mov lr, r3 \n" /* LR = r3. */\r
+ " lsls r2, r3, #25 \n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
+ " bpl restore_ns_context \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
+ " msr psp, r1 \n" /* Remember the new top of stack for the task. */\r
+ " bx lr \n"\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ " restore_ns_context: \n"\r
+ " ldmia r1!, {r4-r11} \n" /* Restore the registers that are not automatically restored. */\r
+ #if( configENABLE_FPU == 1 )\r
+ " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
+ " it eq \n"\r
+ " vldmiaeq r1!, {s16-s31} \n" /* Restore the FPU registers which are not restored automatically. */\r
+ #endif /* configENABLE_FPU */\r
+ " msr psp, r1 \n" /* Remember the new top of stack for the task. */\r
+ " bx lr \n"\r
+ " \n"\r
+ " .align 4 \n"\r
+ "pxCurrentTCBConst: .word pxCurrentTCB \n"\r
+ "xSecureContextConst: .word xSecureContext \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ "xMAIR0Const: .word 0xe000edc0 \n"\r
+ "xRNRConst: .word 0xe000ed98 \n"\r
+ "xRBARConst: .word 0xe000ed9c \n"\r
+ #endif /* configENABLE_MPU */\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
\r
void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
{\r
- __asm volatile\r
- (\r
- " tst lr, #4 \n"\r
- " ite eq \n"\r
- " mrseq r0, msp \n"\r
- " mrsne r0, psp \n"\r
- " ldr r1, svchandler_address_const \n"\r
- " bx r1 \n"\r
- " \n"\r
- " .align 4 \n"\r
- "svchandler_address_const: .word vPortSVCHandler_C \n"\r
- );\r
+ __asm volatile\r
+ (\r
+ " tst lr, #4 \n"\r
+ " ite eq \n"\r
+ " mrseq r0, msp \n"\r
+ " mrsne r0, psp \n"\r
+ " ldr r1, svchandler_address_const \n"\r
+ " bx r1 \n"\r
+ " \n"\r
+ " .align 4 \n"\r
+ "svchandler_address_const: .word vPortSVCHandler_C \n"\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */\r
{\r
- __asm volatile\r
- (\r
- " svc %0 \n" /* Secure context is allocated in the supervisor call. */\r
- " bx lr \n" /* Return. */\r
- :: "i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"\r
- );\r
+ __asm volatile\r
+ (\r
+ " svc %0 \n" /* Secure context is allocated in the supervisor call. */\r
+ " bx lr \n" /* Return. */\r
+ :: "i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
{\r
- __asm volatile\r
- (\r
- " ldr r1, [r0] \n" /* The first item in the TCB is the top of the stack. */\r
- " ldr r0, [r1] \n" /* The first item on the stack is the task's xSecureContext. */\r
- " cmp r0, #0 \n" /* Raise svc if task's xSecureContext is not NULL. */\r
- " it ne \n"\r
- " svcne %0 \n" /* Secure context is freed in the supervisor call. */\r
- " bx lr \n" /* Return. */\r
- :: "i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"\r
- );\r
+ __asm volatile\r
+ (\r
+ " ldr r1, [r0] \n" /* The first item in the TCB is the top of the stack. */\r
+ " ldr r0, [r1] \n" /* The first item on the stack is the task's xSecureContext. */\r
+ " cmp r0, #0 \n" /* Raise svc if task's xSecureContext is not NULL. */\r
+ " it ne \n"\r
+ " svcne %0 \n" /* Secure context is freed in the supervisor call. */\r
+ " bx lr \n" /* Return. */\r
+ :: "i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
*------------------------------------------------------------------------------\r
*/\r
\r
+#ifndef configENABLE_FPU\r
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h.\r
+#endif /* configENABLE_FPU */\r
+\r
+#ifndef configENABLE_MPU\r
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h.\r
+#endif /* configENABLE_MPU */\r
+\r
+#ifndef configENABLE_TRUSTZONE\r
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.\r
+#endif /* configENABLE_TRUSTZONE */\r
+/*-----------------------------------------------------------*/\r
+\r
/**\r
* @brief Type definitions.\r
*/\r
-#define portCHAR char\r
-#define portFLOAT float\r
-#define portDOUBLE double\r
-#define portLONG long\r
-#define portSHORT short\r
-#define portSTACK_TYPE uint32_t\r
-#define portBASE_TYPE long\r
-\r
-typedef portSTACK_TYPE StackType_t;\r
-typedef long BaseType_t;\r
-typedef unsigned long UBaseType_t;\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT short\r
+#define portSTACK_TYPE uint32_t\r
+#define portBASE_TYPE long\r
+\r
+typedef portSTACK_TYPE StackType_t;\r
+typedef long BaseType_t;\r
+typedef unsigned long UBaseType_t;\r
\r
#if( configUSE_16_BIT_TICKS == 1 )\r
- typedef uint16_t TickType_t;\r
- #define portMAX_DELAY ( TickType_t ) 0xffff\r
+ typedef uint16_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffff\r
#else\r
- typedef uint32_t TickType_t;\r
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL\r
+ typedef uint32_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL\r
\r
- /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\r
- * not need to be guarded with a critical section. */\r
- #define portTICK_TYPE_IS_ATOMIC 1\r
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\r
+ * not need to be guarded with a critical section. */\r
+ #define portTICK_TYPE_IS_ATOMIC 1\r
#endif\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* Architecture specifics.\r
*/\r
-#define portSTACK_GROWTH ( -1 )\r
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
-#define portBYTE_ALIGNMENT 8\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
+#define portBYTE_ALIGNMENT 8\r
#define portNOP()\r
-#define portINLINE __inline\r
+#define portINLINE __inline\r
#ifndef portFORCE_INLINE\r
- #define portFORCE_INLINE inline __attribute__(( always_inline ))\r
+ #define portFORCE_INLINE inline __attribute__(( always_inline ))\r
#endif\r
-#define portHAS_STACK_OVERFLOW_CHECKING 1\r
+#define portHAS_STACK_OVERFLOW_CHECKING 1\r
/*-----------------------------------------------------------*/\r
\r
/**\r
extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );\r
- extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* PRIVILEGED_FUNCTION */;\r
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );\r
+ extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* PRIVILEGED_FUNCTION */;\r
#endif /* configENABLE_TRUSTZONE */\r
\r
#if( configENABLE_MPU == 1 )\r
- extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;\r
- extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;\r
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;\r
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;\r
#endif /* configENABLE_MPU */\r
/*-----------------------------------------------------------*/\r
\r
* @brief MPU specific constants.\r
*/\r
#if( configENABLE_MPU == 1 )\r
- #define portUSING_MPU_WRAPPERS 1\r
- #define portPRIVILEGE_BIT ( 0x80000000UL )\r
+ #define portUSING_MPU_WRAPPERS 1\r
+ #define portPRIVILEGE_BIT ( 0x80000000UL )\r
#else\r
- #define portPRIVILEGE_BIT ( 0x0UL )\r
+ #define portPRIVILEGE_BIT ( 0x0UL )\r
#endif /* configENABLE_MPU */\r
\r
\r
/* MPU regions. */\r
-#define portPRIVILEGED_FLASH_REGION ( 0UL )\r
-#define portUNPRIVILEGED_FLASH_REGION ( 1UL )\r
-#define portPRIVILEGED_RAM_REGION ( 2UL )\r
-#define portUNPRIVILEGED_DEVICE_REGION ( 3UL )\r
-#define portSTACK_REGION ( 4UL )\r
-#define portFIRST_CONFIGURABLE_REGION ( 5UL )\r
-#define portLAST_CONFIGURABLE_REGION ( 7UL )\r
-#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\r
-#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */\r
+#define portPRIVILEGED_FLASH_REGION ( 0UL )\r
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )\r
+#define portPRIVILEGED_RAM_REGION ( 2UL )\r
+#define portUNPRIVILEGED_DEVICE_REGION ( 3UL )\r
+#define portSTACK_REGION ( 4UL )\r
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )\r
+#define portLAST_CONFIGURABLE_REGION ( 7UL )\r
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\r
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */\r
\r
/* Devices Region. */\r
-#define portDEVICE_REGION_START_ADDRESS ( 0x50000000 )\r
-#define portDEVICE_REGION_END_ADDRESS ( 0x5FFFFFFF )\r
+#define portDEVICE_REGION_START_ADDRESS ( 0x50000000 )\r
+#define portDEVICE_REGION_END_ADDRESS ( 0x5FFFFFFF )\r
\r
/* Device memory attributes used in MPU_MAIR registers.\r
*\r
* 8-bit values encoded as follows:\r
* Bit[7:4] - 0000 - Device Memory\r
* Bit[3:2] - 00 --> Device-nGnRnE\r
- * 01 --> Device-nGnRE\r
- * 10 --> Device-nGRE\r
- * 11 --> Device-GRE\r
+ * 01 --> Device-nGnRE\r
+ * 10 --> Device-nGRE\r
+ * 11 --> Device-GRE\r
* Bit[1:0] - 00, Reserved.\r
*/\r
-#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */\r
-#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */\r
-#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */\r
-#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */\r
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */\r
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */\r
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */\r
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */\r
\r
/* Normal memory attributes used in MPU_MAIR registers. */\r
-#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */\r
-#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */\r
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */\r
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */\r
\r
/* Attributes used in MPU_RBAR registers. */\r
-#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )\r
-#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )\r
-#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )\r
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )\r
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )\r
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )\r
\r
-#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )\r
-#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )\r
-#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )\r
-#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )\r
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )\r
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )\r
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )\r
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )\r
\r
-#define portMPU_REGION_EXECUTE_NEVER ( 1UL )\r
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )\r
/*-----------------------------------------------------------*/\r
\r
/**\r
*/\r
typedef struct MPURegionSettings\r
{\r
- uint32_t ulRBAR; /**< RBAR for the region. */\r
- uint32_t ulRLAR; /**< RLAR for the region. */\r
+ uint32_t ulRBAR; /**< RBAR for the region. */\r
+ uint32_t ulRLAR; /**< RLAR for the region. */\r
} MPURegionSettings_t;\r
\r
/**\r
*/\r
typedef struct MPU_SETTINGS\r
{\r
- uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */\r
- MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */\r
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */\r
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */\r
} xMPU_SETTINGS;\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief SVC numbers.\r
*/\r
-#define portSVC_ALLOCATE_SECURE_CONTEXT 0\r
-#define portSVC_FREE_SECURE_CONTEXT 1\r
-#define portSVC_START_SCHEDULER 2\r
-#define portSVC_RAISE_PRIVILEGE 3\r
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0\r
+#define portSVC_FREE_SECURE_CONTEXT 1\r
+#define portSVC_START_SCHEDULER 2\r
+#define portSVC_RAISE_PRIVILEGE 3\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Scheduler utilities.\r
*/\r
-#define portYIELD() vPortYield()\r
-#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )\r
-#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )\r
-#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT\r
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
+#define portYIELD() vPortYield()\r
+#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )\r
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )\r
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT\r
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Critical section management.\r
*/\r
-#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()\r
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )\r
-#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )\r
-#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )\r
-#define portENTER_CRITICAL() vPortEnterCritical()\r
-#define portEXIT_CRITICAL() vPortExitCritical()\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )\r
+#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )\r
+#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )\r
+#define portENTER_CRITICAL() vPortEnterCritical()\r
+#define portEXIT_CRITICAL() vPortExitCritical()\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Task function macros as described on the FreeRTOS.org WEB site.\r
*/\r
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
/*-----------------------------------------------------------*/\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
- /**\r
- * @brief Allocate a secure context for the task.\r
- *\r
- * Tasks are not created with a secure context. Any task that is going to call\r
- * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a\r
- * secure context before it calls any secure function.\r
- *\r
- * @param[in] ulSecureStackSize The size of the secure stack to be allocated.\r
- */\r
- #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )\r
-\r
- /**\r
- * @brief Called when a task is deleted to delete the task's secure context,\r
- * if it has one.\r
- *\r
- * @param[in] pxTCB The TCB of the task being deleted.\r
- */\r
- #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )\r
+ /**\r
+ * @brief Allocate a secure context for the task.\r
+ *\r
+ * Tasks are not created with a secure context. Any task that is going to call\r
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a\r
+ * secure context before it calls any secure function.\r
+ *\r
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.\r
+ */\r
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )\r
+\r
+ /**\r
+ * @brief Called when a task is deleted to delete the task's secure context,\r
+ * if it has one.\r
+ *\r
+ * @param[in] pxTCB The TCB of the task being deleted.\r
+ */\r
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )\r
#else\r
- #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )\r
- #define portCLEAN_UP_TCB( pxTCB )\r
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )\r
+ #define portCLEAN_UP_TCB( pxTCB )\r
#endif /* configENABLE_TRUSTZONE */\r
/*-----------------------------------------------------------*/\r
\r
#if( configENABLE_MPU == 1 )\r
- /**\r
- * @brief Checks whether or not the processor is privileged.\r
- *\r
- * @return 1 if the processor is already privileged, 0 otherwise.\r
- */\r
- #define portIS_PRIVILEGED() xIsPrivileged()\r
-\r
- /**\r
- * @brief Raise an SVC request to raise privilege.\r
- *\r
- * The SVC handler checks that the SVC was raised from a system call and only\r
- * then it raises the privilege. If this is called from any other place,\r
- * the privilege is not raised.\r
- */\r
- #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );\r
-\r
- /**\r
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\r
- * register.\r
- */\r
- #define portRESET_PRIVILEGE() vResetPrivilege()\r
+ /**\r
+ * @brief Checks whether or not the processor is privileged.\r
+ *\r
+ * @return 1 if the processor is already privileged, 0 otherwise.\r
+ */\r
+ #define portIS_PRIVILEGED() xIsPrivileged()\r
+\r
+ /**\r
+ * @brief Raise an SVC request to raise privilege.\r
+ *\r
+ * The SVC handler checks that the SVC was raised from a system call and only\r
+ * then it raises the privilege. If this is called from any other place,\r
+ * the privilege is not raised.\r
+ */\r
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );\r
+\r
+ /**\r
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\r
+ * register.\r
+ */\r
+ #define portRESET_PRIVILEGE() vResetPrivilege()\r
#else\r
- #define portIS_PRIVILEGED()\r
- #define portRAISE_PRIVILEGE()\r
- #define portRESET_PRIVILEGE()\r
+ #define portIS_PRIVILEGED()\r
+ #define portRAISE_PRIVILEGE()\r
+ #define portRESET_PRIVILEGE()\r
#endif /* configENABLE_MPU */\r
/*-----------------------------------------------------------*/\r
\r
* Bit[0] - 0 --> Thread mode is privileged.\r
* Bit[1] - 1 --> Thread mode uses PSP.\r
*/\r
-#define securecontextCONTROL_VALUE_PRIVILEGED 0x02\r
+#define securecontextCONTROL_VALUE_PRIVILEGED 0x02\r
\r
/**\r
* @brief CONTROL value for un-privileged tasks.\r
* Bit[0] - 1 --> Thread mode is un-privileged.\r
* Bit[1] - 1 --> Thread mode uses PSP.\r
*/\r
-#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03\r
+#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03\r
/*-----------------------------------------------------------*/\r
\r
/**\r
*/\r
typedef struct SecureContext\r
{\r
- uint8_t *pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */\r
- uint8_t *pucStackLimit; /**< Last location of the stack memory (PSPLIM). */\r
- uint8_t *pucStackStart; /**< First location of the stack memory. */\r
+ uint8_t *pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */\r
+ uint8_t *pucStackLimit; /**< Last location of the stack memory (PSPLIM). */\r
+ uint8_t *pucStackStart; /**< First location of the stack memory. */\r
} SecureContext_t;\r
/*-----------------------------------------------------------*/\r
\r
secureportNON_SECURE_CALLABLE void SecureContext_Init( void )\r
{\r
- uint32_t ulIPSR;\r
-\r
- /* Read the Interrupt Program Status Register (IPSR) value. */\r
- secureportREAD_IPSR( ulIPSR );\r
-\r
- /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
- * when the processor is running in the Thread Mode. */\r
- if( ulIPSR != 0 )\r
- {\r
- /* No stack for thread mode until a task's context is loaded. */\r
- secureportSET_PSPLIM( securecontextNO_STACK );\r
- secureportSET_PSP( securecontextNO_STACK );\r
-\r
- #if( configENABLE_MPU == 1 )\r
- {\r
- /* Configure thread mode to use PSP and to be unprivileged. */\r
- secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );\r
- }\r
- #else /* configENABLE_MPU */\r
- {\r
- /* Configure thread mode to use PSP and to be privileged.. */\r
- secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );\r
- }\r
- #endif /* configENABLE_MPU */\r
- }\r
+ uint32_t ulIPSR;\r
+\r
+ /* Read the Interrupt Program Status Register (IPSR) value. */\r
+ secureportREAD_IPSR( ulIPSR );\r
+\r
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
+ * when the processor is running in the Thread Mode. */\r
+ if( ulIPSR != 0 )\r
+ {\r
+ /* No stack for thread mode until a task's context is loaded. */\r
+ secureportSET_PSPLIM( securecontextNO_STACK );\r
+ secureportSET_PSP( securecontextNO_STACK );\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ /* Configure thread mode to use PSP and to be unprivileged. */\r
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );\r
+ }\r
+ #else /* configENABLE_MPU */\r
+ {\r
+ /* Configure thread mode to use PSP and to be privileged.. */\r
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
\r
#if( configENABLE_MPU == 1 )\r
- secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged )\r
+ secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged )\r
#else /* configENABLE_MPU */\r
- secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize )\r
+ secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize )\r
#endif /* configENABLE_MPU */\r
{\r
- uint8_t *pucStackMemory = NULL;\r
- uint32_t ulIPSR;\r
- SecureContextHandle_t xSecureContextHandle = NULL;\r
- #if( configENABLE_MPU == 1 )\r
- uint32_t *pulCurrentStackPointer = NULL;\r
- #endif /* configENABLE_MPU */\r
-\r
- /* Read the Interrupt Program Status Register (IPSR) value. */\r
- secureportREAD_IPSR( ulIPSR );\r
-\r
- /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
- * when the processor is running in the Thread Mode. */\r
- if( ulIPSR != 0 )\r
- {\r
- /* Allocate the context structure. */\r
- xSecureContextHandle = ( SecureContextHandle_t ) pvPortMalloc( sizeof( SecureContext_t ) );\r
-\r
- if( xSecureContextHandle != NULL )\r
- {\r
- /* Allocate the stack space. */\r
- pucStackMemory = pvPortMalloc( ulSecureStackSize );\r
-\r
- if( pucStackMemory != NULL )\r
- {\r
- /* Since stack grows down, the starting point will be the last\r
- * location. Note that this location is next to the last\r
- * allocated byte because the hardware decrements the stack\r
- * pointer before writing i.e. if stack pointer is 0x2, a push\r
- * operation will decrement the stack pointer to 0x1 and then\r
- * write at 0x1. */\r
- xSecureContextHandle->pucStackStart = pucStackMemory + ulSecureStackSize;\r
-\r
- /* The stack cannot go beyond this location. This value is\r
- * programmed in the PSPLIM register on context switch.*/\r
- xSecureContextHandle->pucStackLimit = pucStackMemory;\r
-\r
- #if( configENABLE_MPU == 1 )\r
- {\r
- /* Store the correct CONTROL value for the task on the stack.\r
- * This value is programmed in the CONTROL register on\r
- * context switch. */\r
- pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;\r
- pulCurrentStackPointer--;\r
- if( ulIsTaskPrivileged )\r
- {\r
- *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;\r
- }\r
- else\r
- {\r
- *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;\r
- }\r
-\r
- /* Store the current stack pointer. This value is programmed in\r
- * the PSP register on context switch. */\r
- xSecureContextHandle->pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;\r
- }\r
- #else /* configENABLE_MPU */\r
- {\r
- /* Current SP is set to the starting of the stack. This\r
- * value programmed in the PSP register on context switch. */\r
- xSecureContextHandle->pucCurrentStackPointer = xSecureContextHandle->pucStackStart;\r
-\r
- }\r
- #endif /* configENABLE_MPU */\r
- }\r
- else\r
- {\r
- /* Free the context to avoid memory leak and make sure to return\r
- * NULL to indicate failure. */\r
- vPortFree( xSecureContextHandle );\r
- xSecureContextHandle = NULL;\r
- }\r
- }\r
- }\r
-\r
- return xSecureContextHandle;\r
+ uint8_t *pucStackMemory = NULL;\r
+ uint32_t ulIPSR;\r
+ SecureContextHandle_t xSecureContextHandle = NULL;\r
+ #if( configENABLE_MPU == 1 )\r
+ uint32_t *pulCurrentStackPointer = NULL;\r
+ #endif /* configENABLE_MPU */\r
+\r
+ /* Read the Interrupt Program Status Register (IPSR) value. */\r
+ secureportREAD_IPSR( ulIPSR );\r
+\r
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
+ * when the processor is running in the Thread Mode. */\r
+ if( ulIPSR != 0 )\r
+ {\r
+ /* Allocate the context structure. */\r
+ xSecureContextHandle = ( SecureContextHandle_t ) pvPortMalloc( sizeof( SecureContext_t ) );\r
+\r
+ if( xSecureContextHandle != NULL )\r
+ {\r
+ /* Allocate the stack space. */\r
+ pucStackMemory = pvPortMalloc( ulSecureStackSize );\r
+\r
+ if( pucStackMemory != NULL )\r
+ {\r
+ /* Since stack grows down, the starting point will be the last\r
+ * location. Note that this location is next to the last\r
+ * allocated byte because the hardware decrements the stack\r
+ * pointer before writing i.e. if stack pointer is 0x2, a push\r
+ * operation will decrement the stack pointer to 0x1 and then\r
+ * write at 0x1. */\r
+ xSecureContextHandle->pucStackStart = pucStackMemory + ulSecureStackSize;\r
+\r
+ /* The stack cannot go beyond this location. This value is\r
+ * programmed in the PSPLIM register on context switch.*/\r
+ xSecureContextHandle->pucStackLimit = pucStackMemory;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ /* Store the correct CONTROL value for the task on the stack.\r
+ * This value is programmed in the CONTROL register on\r
+ * context switch. */\r
+ pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;\r
+ pulCurrentStackPointer--;\r
+ if( ulIsTaskPrivileged )\r
+ {\r
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;\r
+ }\r
+ else\r
+ {\r
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;\r
+ }\r
+\r
+ /* Store the current stack pointer. This value is programmed in\r
+ * the PSP register on context switch. */\r
+ xSecureContextHandle->pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;\r
+ }\r
+ #else /* configENABLE_MPU */\r
+ {\r
+ /* Current SP is set to the starting of the stack. This\r
+ * value programmed in the PSP register on context switch. */\r
+ xSecureContextHandle->pucCurrentStackPointer = xSecureContextHandle->pucStackStart;\r
+\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+ }\r
+ else\r
+ {\r
+ /* Free the context to avoid memory leak and make sure to return\r
+ * NULL to indicate failure. */\r
+ vPortFree( xSecureContextHandle );\r
+ xSecureContextHandle = NULL;\r
+ }\r
+ }\r
+ }\r
+\r
+ return xSecureContextHandle;\r
}\r
/*-----------------------------------------------------------*/\r
\r
secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle )\r
{\r
- uint32_t ulIPSR;\r
+ uint32_t ulIPSR;\r
\r
- /* Read the Interrupt Program Status Register (IPSR) value. */\r
- secureportREAD_IPSR( ulIPSR );\r
+ /* Read the Interrupt Program Status Register (IPSR) value. */\r
+ secureportREAD_IPSR( ulIPSR );\r
\r
- /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
- * when the processor is running in the Thread Mode. */\r
- if( ulIPSR != 0 )\r
- {\r
- /* Ensure that valid parameters are passed. */\r
- secureportASSERT( xSecureContextHandle != NULL );\r
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
+ * when the processor is running in the Thread Mode. */\r
+ if( ulIPSR != 0 )\r
+ {\r
+ /* Ensure that valid parameters are passed. */\r
+ secureportASSERT( xSecureContextHandle != NULL );\r
\r
- /* Free the stack space. */\r
- vPortFree( xSecureContextHandle->pucStackLimit );\r
+ /* Free the stack space. */\r
+ vPortFree( xSecureContextHandle->pucStackLimit );\r
\r
- /* Free the context itself. */\r
- vPortFree( xSecureContextHandle );\r
- }\r
+ /* Free the context itself. */\r
+ vPortFree( xSecureContextHandle );\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
/**\r
* @brief PSP value when no task's context is loaded.\r
*/\r
-#define securecontextNO_STACK 0x0\r
+#define securecontextNO_STACK 0x0\r
\r
/**\r
* @brief Opaque handle.\r
*/\r
struct SecureContext;\r
-typedef struct SecureContext* SecureContextHandle_t;\r
+typedef struct SecureContext* SecureContextHandle_t;\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* otherwise.\r
*/\r
#if( configENABLE_MPU == 1 )\r
- SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged );\r
+ SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged );\r
#else /* configENABLE_MPU */\r
- SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize );\r
+ SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize );\r
#endif /* configENABLE_MPU */\r
\r
/**\r
\r
secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )\r
{\r
- /* xSecureContextHandle value is in r0. */\r
- __asm volatile\r
- (\r
- " .syntax unified \n"\r
- " \n"\r
- " mrs r1, ipsr \n" /* r1 = IPSR. */\r
- " cbz r1, load_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */\r
- " ldmia r0!, {r1, r2} \n" /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */\r
- #if( configENABLE_MPU == 1 )\r
- " ldmia r1!, {r3} \n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */\r
- " msr control, r3 \n" /* CONTROL = r3. */\r
- #endif /* configENABLE_MPU */\r
- " msr psplim, r2 \n" /* PSPLIM = r2. */\r
- " msr psp, r1 \n" /* PSP = r1. */\r
- " \n"\r
- " load_ctx_therad_mode: \n"\r
- " nop \n"\r
- " \n"\r
- :::"r0", "r1", "r2"\r
- );\r
+ /* xSecureContextHandle value is in r0. */\r
+ __asm volatile\r
+ (\r
+ " .syntax unified \n"\r
+ " \n"\r
+ " mrs r1, ipsr \n" /* r1 = IPSR. */\r
+ " cbz r1, load_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */\r
+ " ldmia r0!, {r1, r2} \n" /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */\r
+ #if( configENABLE_MPU == 1 )\r
+ " ldmia r1!, {r3} \n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */\r
+ " msr control, r3 \n" /* CONTROL = r3. */\r
+ #endif /* configENABLE_MPU */\r
+ " msr psplim, r2 \n" /* PSPLIM = r2. */\r
+ " msr psp, r1 \n" /* PSP = r1. */\r
+ " \n"\r
+ " load_ctx_therad_mode: \n"\r
+ " nop \n"\r
+ " \n"\r
+ :::"r0", "r1", "r2"\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
\r
secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )\r
{\r
- /* xSecureContextHandle value is in r0. */\r
- __asm volatile\r
- (\r
- " .syntax unified \n"\r
- " \n"\r
- " mrs r1, ipsr \n" /* r1 = IPSR. */\r
- " cbz r1, save_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */\r
- " mrs r1, psp \n" /* r1 = PSP. */\r
- #if( configENABLE_FPU == 1 )\r
- " vstmdb r1!, {s0} \n" /* Trigger the defferred stacking of FPU registers. */\r
- " vldmia r1!, {s0} \n" /* Nullify the effect of the pervious statement. */\r
- #endif /* configENABLE_FPU */\r
- #if( configENABLE_MPU == 1 )\r
- " mrs r2, control \n" /* r2 = CONTROL. */\r
- " stmdb r1!, {r2} \n" /* Store CONTROL value on the stack. */\r
- #endif /* configENABLE_MPU */\r
- " str r1, [r0] \n" /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */\r
- " movs r1, %0 \n" /* r1 = securecontextNO_STACK. */\r
- " msr psplim, r1 \n" /* PSPLIM = securecontextNO_STACK. */\r
- " msr psp, r1 \n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */\r
- " \n"\r
- " save_ctx_therad_mode: \n"\r
- " nop \n"\r
- " \n"\r
- :: "i" ( securecontextNO_STACK ) : "r1", "memory"\r
- );\r
+ /* xSecureContextHandle value is in r0. */\r
+ __asm volatile\r
+ (\r
+ " .syntax unified \n"\r
+ " \n"\r
+ " mrs r1, ipsr \n" /* r1 = IPSR. */\r
+ " cbz r1, save_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */\r
+ " mrs r1, psp \n" /* r1 = PSP. */\r
+ #if( configENABLE_FPU == 1 )\r
+ " vstmdb r1!, {s0} \n" /* Trigger the defferred stacking of FPU registers. */\r
+ " vldmia r1!, {s0} \n" /* Nullify the effect of the pervious statement. */\r
+ #endif /* configENABLE_FPU */\r
+ #if( configENABLE_MPU == 1 )\r
+ " mrs r2, control \n" /* r2 = CONTROL. */\r
+ " stmdb r1!, {r2} \n" /* Store CONTROL value on the stack. */\r
+ #endif /* configENABLE_MPU */\r
+ " str r1, [r0] \n" /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */\r
+ " movs r1, %0 \n" /* r1 = securecontextNO_STACK. */\r
+ " msr psplim, r1 \n" /* PSPLIM = securecontextNO_STACK. */\r
+ " msr psp, r1 \n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */\r
+ " \n"\r
+ " save_ctx_therad_mode: \n"\r
+ " nop \n"\r
+ " \n"\r
+ :: "i" ( securecontextNO_STACK ) : "r1", "memory"\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
/**\r
* @brief Total heap size.\r
*/\r
-#define secureconfigTOTAL_HEAP_SIZE ( ( ( size_t ) ( 10 * 1024 ) ) )\r
+#define secureconfigTOTAL_HEAP_SIZE ( ( ( size_t ) ( 10 * 1024 ) ) )\r
\r
/* No test marker by default. */\r
#ifndef mtCOVERAGE_TEST_MARKER\r
- #define mtCOVERAGE_TEST_MARKER()\r
+ #define mtCOVERAGE_TEST_MARKER()\r
#endif\r
\r
/* No tracing by default. */\r
#ifndef traceMALLOC\r
- #define traceMALLOC( pvReturn, xWantedSize )\r
+ #define traceMALLOC( pvReturn, xWantedSize )\r
#endif\r
\r
/* No tracing by default. */\r
#ifndef traceFREE\r
- #define traceFREE( pv, xBlockSize )\r
+ #define traceFREE( pv, xBlockSize )\r
#endif\r
\r
/* Block sizes must not get too small. */\r
-#define secureheapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) )\r
+#define secureheapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) )\r
\r
/* Assumes 8bit bytes! */\r
-#define secureheapBITS_PER_BYTE ( ( size_t ) 8 )\r
+#define secureheapBITS_PER_BYTE ( ( size_t ) 8 )\r
/*-----------------------------------------------------------*/\r
\r
/* Allocate the memory for the heap. */\r
#if( configAPPLICATION_ALLOCATED_HEAP == 1 )\r
- /* The application writer has already defined the array used for the RTOS\r
- * heap - probably so it can be placed in a special segment or address. */\r
- extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];\r
+ /* The application writer has already defined the array used for the RTOS\r
+ * heap - probably so it can be placed in a special segment or address. */\r
+ extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];\r
#else /* configAPPLICATION_ALLOCATED_HEAP */\r
- static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];\r
+ static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];\r
#endif /* configAPPLICATION_ALLOCATED_HEAP */\r
\r
/**\r
*/\r
typedef struct A_BLOCK_LINK\r
{\r
- struct A_BLOCK_LINK *pxNextFreeBlock; /**< The next free block in the list. */\r
- size_t xBlockSize; /**< The size of the free block. */\r
+ struct A_BLOCK_LINK *pxNextFreeBlock; /**< The next free block in the list. */\r
+ size_t xBlockSize; /**< The size of the free block. */\r
} BlockLink_t;\r
/*-----------------------------------------------------------*/\r
\r
size_t uxAddress;\r
size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;\r
\r
- /* Ensure the heap starts on a correctly aligned boundary. */\r
- uxAddress = ( size_t ) ucHeap;\r
-\r
- if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )\r
- {\r
- uxAddress += ( secureportBYTE_ALIGNMENT - 1 );\r
- uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\r
- xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;\r
- }\r
-\r
- pucAlignedHeap = ( uint8_t * ) uxAddress;\r
-\r
- /* xStart is used to hold a pointer to the first item in the list of free\r
- * blocks. The void cast is used to prevent compiler warnings. */\r
- xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;\r
- xStart.xBlockSize = ( size_t ) 0;\r
-\r
- /* pxEnd is used to mark the end of the list of free blocks and is inserted\r
- * at the end of the heap space. */\r
- uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;\r
- uxAddress -= xHeapStructSize;\r
- uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\r
- pxEnd = ( void * ) uxAddress;\r
- pxEnd->xBlockSize = 0;\r
- pxEnd->pxNextFreeBlock = NULL;\r
-\r
- /* To start with there is a single free block that is sized to take up the\r
- * entire heap space, minus the space taken by pxEnd. */\r
- pxFirstFreeBlock = ( void * ) pucAlignedHeap;\r
- pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;\r
- pxFirstFreeBlock->pxNextFreeBlock = pxEnd;\r
-\r
- /* Only one block exists - and it covers the entire usable heap space. */\r
- xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;\r
- xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;\r
-\r
- /* Work out the position of the top bit in a size_t variable. */\r
- xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );\r
+ /* Ensure the heap starts on a correctly aligned boundary. */\r
+ uxAddress = ( size_t ) ucHeap;\r
+\r
+ if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )\r
+ {\r
+ uxAddress += ( secureportBYTE_ALIGNMENT - 1 );\r
+ uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\r
+ xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;\r
+ }\r
+\r
+ pucAlignedHeap = ( uint8_t * ) uxAddress;\r
+\r
+ /* xStart is used to hold a pointer to the first item in the list of free\r
+ * blocks. The void cast is used to prevent compiler warnings. */\r
+ xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;\r
+ xStart.xBlockSize = ( size_t ) 0;\r
+\r
+ /* pxEnd is used to mark the end of the list of free blocks and is inserted\r
+ * at the end of the heap space. */\r
+ uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;\r
+ uxAddress -= xHeapStructSize;\r
+ uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\r
+ pxEnd = ( void * ) uxAddress;\r
+ pxEnd->xBlockSize = 0;\r
+ pxEnd->pxNextFreeBlock = NULL;\r
+\r
+ /* To start with there is a single free block that is sized to take up the\r
+ * entire heap space, minus the space taken by pxEnd. */\r
+ pxFirstFreeBlock = ( void * ) pucAlignedHeap;\r
+ pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;\r
+ pxFirstFreeBlock->pxNextFreeBlock = pxEnd;\r
+\r
+ /* Only one block exists - and it covers the entire usable heap space. */\r
+ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;\r
+ xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;\r
+\r
+ /* Work out the position of the top bit in a size_t variable. */\r
+ xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );\r
}\r
/*-----------------------------------------------------------*/\r
\r
BlockLink_t *pxIterator;\r
uint8_t *puc;\r
\r
- /* Iterate through the list until a block is found that has a higher address\r
- * than the block being inserted. */\r
- for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )\r
- {\r
- /* Nothing to do here, just iterate to the right position. */\r
- }\r
-\r
- /* Do the block being inserted, and the block it is being inserted after\r
- * make a contiguous block of memory? */\r
- puc = ( uint8_t * ) pxIterator;\r
- if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )\r
- {\r
- pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;\r
- pxBlockToInsert = pxIterator;\r
- }\r
- else\r
- {\r
- mtCOVERAGE_TEST_MARKER();\r
- }\r
-\r
- /* Do the block being inserted, and the block it is being inserted before\r
- * make a contiguous block of memory? */\r
- puc = ( uint8_t * ) pxBlockToInsert;\r
- if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )\r
- {\r
- if( pxIterator->pxNextFreeBlock != pxEnd )\r
- {\r
- /* Form one big block from the two blocks. */\r
- pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;\r
- pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;\r
- }\r
- else\r
- {\r
- pxBlockToInsert->pxNextFreeBlock = pxEnd;\r
- }\r
- }\r
- else\r
- {\r
- pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;\r
- }\r
-\r
- /* If the block being inserted plugged a gab, so was merged with the block\r
- * before and the block after, then it's pxNextFreeBlock pointer will have\r
- * already been set, and should not be set here as that would make it point\r
- * to itself. */\r
- if( pxIterator != pxBlockToInsert )\r
- {\r
- pxIterator->pxNextFreeBlock = pxBlockToInsert;\r
- }\r
- else\r
- {\r
- mtCOVERAGE_TEST_MARKER();\r
- }\r
+ /* Iterate through the list until a block is found that has a higher address\r
+ * than the block being inserted. */\r
+ for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )\r
+ {\r
+ /* Nothing to do here, just iterate to the right position. */\r
+ }\r
+\r
+ /* Do the block being inserted, and the block it is being inserted after\r
+ * make a contiguous block of memory? */\r
+ puc = ( uint8_t * ) pxIterator;\r
+ if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )\r
+ {\r
+ pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;\r
+ pxBlockToInsert = pxIterator;\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+\r
+ /* Do the block being inserted, and the block it is being inserted before\r
+ * make a contiguous block of memory? */\r
+ puc = ( uint8_t * ) pxBlockToInsert;\r
+ if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )\r
+ {\r
+ if( pxIterator->pxNextFreeBlock != pxEnd )\r
+ {\r
+ /* Form one big block from the two blocks. */\r
+ pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;\r
+ pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;\r
+ }\r
+ else\r
+ {\r
+ pxBlockToInsert->pxNextFreeBlock = pxEnd;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;\r
+ }\r
+\r
+ /* If the block being inserted plugged a gab, so was merged with the block\r
+ * before and the block after, then it's pxNextFreeBlock pointer will have\r
+ * already been set, and should not be set here as that would make it point\r
+ * to itself. */\r
+ if( pxIterator != pxBlockToInsert )\r
+ {\r
+ pxIterator->pxNextFreeBlock = pxBlockToInsert;\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
\r
BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;\r
void *pvReturn = NULL;\r
\r
- /* If this is the first call to malloc then the heap will require\r
- * initialisation to setup the list of free blocks. */\r
- if( pxEnd == NULL )\r
- {\r
- prvHeapInit();\r
- }\r
- else\r
- {\r
- mtCOVERAGE_TEST_MARKER();\r
- }\r
-\r
- /* Check the requested block size is not so large that the top bit is set.\r
- * The top bit of the block size member of the BlockLink_t structure is used\r
- * to determine who owns the block - the application or the kernel, so it\r
- * must be free. */\r
- if( ( xWantedSize & xBlockAllocatedBit ) == 0 )\r
- {\r
- /* The wanted size is increased so it can contain a BlockLink_t\r
- * structure in addition to the requested amount of bytes. */\r
- if( xWantedSize > 0 )\r
- {\r
- xWantedSize += xHeapStructSize;\r
-\r
- /* Ensure that blocks are always aligned to the required number of\r
- * bytes. */\r
- if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )\r
- {\r
- /* Byte alignment required. */\r
- xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );\r
- secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );\r
- }\r
- else\r
- {\r
- mtCOVERAGE_TEST_MARKER();\r
- }\r
- }\r
- else\r
- {\r
- mtCOVERAGE_TEST_MARKER();\r
- }\r
-\r
- if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )\r
- {\r
- /* Traverse the list from the start (lowest address) block until\r
- * one of adequate size is found. */\r
- pxPreviousBlock = &xStart;\r
- pxBlock = xStart.pxNextFreeBlock;\r
- while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )\r
- {\r
- pxPreviousBlock = pxBlock;\r
- pxBlock = pxBlock->pxNextFreeBlock;\r
- }\r
-\r
- /* If the end marker was reached then a block of adequate size was\r
- * not found. */\r
- if( pxBlock != pxEnd )\r
- {\r
- /* Return the memory space pointed to - jumping over the\r
- * BlockLink_t structure at its start. */\r
- pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );\r
-\r
- /* This block is being returned for use so must be taken out\r
- * of the list of free blocks. */\r
- pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;\r
-\r
- /* If the block is larger than required it can be split into\r
- * two. */\r
- if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )\r
- {\r
- /* This block is to be split into two. Create a new\r
- * block following the number of bytes requested. The void\r
- * cast is used to prevent byte alignment warnings from the\r
- * compiler. */\r
- pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );\r
- secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );\r
-\r
- /* Calculate the sizes of two blocks split from the single\r
- * block. */\r
- pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;\r
- pxBlock->xBlockSize = xWantedSize;\r
-\r
- /* Insert the new block into the list of free blocks. */\r
- prvInsertBlockIntoFreeList( pxNewBlockLink );\r
- }\r
- else\r
- {\r
- mtCOVERAGE_TEST_MARKER();\r
- }\r
-\r
- xFreeBytesRemaining -= pxBlock->xBlockSize;\r
-\r
- if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )\r
- {\r
- xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;\r
- }\r
- else\r
- {\r
- mtCOVERAGE_TEST_MARKER();\r
- }\r
-\r
- /* The block is being returned - it is allocated and owned by\r
- * the application and has no "next" block. */\r
- pxBlock->xBlockSize |= xBlockAllocatedBit;\r
- pxBlock->pxNextFreeBlock = NULL;\r
- }\r
- else\r
- {\r
- mtCOVERAGE_TEST_MARKER();\r
- }\r
- }\r
- else\r
- {\r
- mtCOVERAGE_TEST_MARKER();\r
- }\r
- }\r
- else\r
- {\r
- mtCOVERAGE_TEST_MARKER();\r
- }\r
-\r
- traceMALLOC( pvReturn, xWantedSize );\r
-\r
- #if( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )\r
- {\r
- if( pvReturn == NULL )\r
- {\r
- extern void vApplicationMallocFailedHook( void );\r
- vApplicationMallocFailedHook();\r
- }\r
- else\r
- {\r
- mtCOVERAGE_TEST_MARKER();\r
- }\r
- }\r
- #endif\r
-\r
- secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );\r
- return pvReturn;\r
+ /* If this is the first call to malloc then the heap will require\r
+ * initialisation to setup the list of free blocks. */\r
+ if( pxEnd == NULL )\r
+ {\r
+ prvHeapInit();\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+\r
+ /* Check the requested block size is not so large that the top bit is set.\r
+ * The top bit of the block size member of the BlockLink_t structure is used\r
+ * to determine who owns the block - the application or the kernel, so it\r
+ * must be free. */\r
+ if( ( xWantedSize & xBlockAllocatedBit ) == 0 )\r
+ {\r
+ /* The wanted size is increased so it can contain a BlockLink_t\r
+ * structure in addition to the requested amount of bytes. */\r
+ if( xWantedSize > 0 )\r
+ {\r
+ xWantedSize += xHeapStructSize;\r
+\r
+ /* Ensure that blocks are always aligned to the required number of\r
+ * bytes. */\r
+ if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )\r
+ {\r
+ /* Byte alignment required. */\r
+ xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );\r
+ secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+\r
+ if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )\r
+ {\r
+ /* Traverse the list from the start (lowest address) block until\r
+ * one of adequate size is found. */\r
+ pxPreviousBlock = &xStart;\r
+ pxBlock = xStart.pxNextFreeBlock;\r
+ while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )\r
+ {\r
+ pxPreviousBlock = pxBlock;\r
+ pxBlock = pxBlock->pxNextFreeBlock;\r
+ }\r
+\r
+ /* If the end marker was reached then a block of adequate size was\r
+ * not found. */\r
+ if( pxBlock != pxEnd )\r
+ {\r
+ /* Return the memory space pointed to - jumping over the\r
+ * BlockLink_t structure at its start. */\r
+ pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );\r
+\r
+ /* This block is being returned for use so must be taken out\r
+ * of the list of free blocks. */\r
+ pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;\r
+\r
+ /* If the block is larger than required it can be split into\r
+ * two. */\r
+ if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )\r
+ {\r
+ /* This block is to be split into two. Create a new\r
+ * block following the number of bytes requested. The void\r
+ * cast is used to prevent byte alignment warnings from the\r
+ * compiler. */\r
+ pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );\r
+ secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );\r
+\r
+ /* Calculate the sizes of two blocks split from the single\r
+ * block. */\r
+ pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;\r
+ pxBlock->xBlockSize = xWantedSize;\r
+\r
+ /* Insert the new block into the list of free blocks. */\r
+ prvInsertBlockIntoFreeList( pxNewBlockLink );\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+\r
+ xFreeBytesRemaining -= pxBlock->xBlockSize;\r
+\r
+ if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )\r
+ {\r
+ xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+\r
+ /* The block is being returned - it is allocated and owned by\r
+ * the application and has no "next" block. */\r
+ pxBlock->xBlockSize |= xBlockAllocatedBit;\r
+ pxBlock->pxNextFreeBlock = NULL;\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+\r
+ traceMALLOC( pvReturn, xWantedSize );\r
+\r
+ #if( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )\r
+ {\r
+ if( pvReturn == NULL )\r
+ {\r
+ extern void vApplicationMallocFailedHook( void );\r
+ vApplicationMallocFailedHook();\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+ }\r
+ #endif\r
+\r
+ secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );\r
+ return pvReturn;\r
}\r
/*-----------------------------------------------------------*/\r
\r
uint8_t *puc = ( uint8_t * ) pv;\r
BlockLink_t *pxLink;\r
\r
- if( pv != NULL )\r
- {\r
- /* The memory being freed will have an BlockLink_t structure immediately\r
- * before it. */\r
- puc -= xHeapStructSize;\r
-\r
- /* This casting is to keep the compiler from issuing warnings. */\r
- pxLink = ( void * ) puc;\r
-\r
- /* Check the block is actually allocated. */\r
- secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );\r
- secureportASSERT( pxLink->pxNextFreeBlock == NULL );\r
-\r
- if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )\r
- {\r
- if( pxLink->pxNextFreeBlock == NULL )\r
- {\r
- /* The block is being returned to the heap - it is no longer\r
- * allocated. */\r
- pxLink->xBlockSize &= ~xBlockAllocatedBit;\r
-\r
- secureportDISABLE_NON_SECURE_INTERRUPTS();\r
- {\r
- /* Add this block to the list of free blocks. */\r
- xFreeBytesRemaining += pxLink->xBlockSize;\r
- traceFREE( pv, pxLink->xBlockSize );\r
- prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );\r
- }\r
- secureportENABLE_NON_SECURE_INTERRUPTS();\r
- }\r
- else\r
- {\r
- mtCOVERAGE_TEST_MARKER();\r
- }\r
- }\r
- else\r
- {\r
- mtCOVERAGE_TEST_MARKER();\r
- }\r
- }\r
+ if( pv != NULL )\r
+ {\r
+ /* The memory being freed will have an BlockLink_t structure immediately\r
+ * before it. */\r
+ puc -= xHeapStructSize;\r
+\r
+ /* This casting is to keep the compiler from issuing warnings. */\r
+ pxLink = ( void * ) puc;\r
+\r
+ /* Check the block is actually allocated. */\r
+ secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );\r
+ secureportASSERT( pxLink->pxNextFreeBlock == NULL );\r
+\r
+ if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )\r
+ {\r
+ if( pxLink->pxNextFreeBlock == NULL )\r
+ {\r
+ /* The block is being returned to the heap - it is no longer\r
+ * allocated. */\r
+ pxLink->xBlockSize &= ~xBlockAllocatedBit;\r
+\r
+ secureportDISABLE_NON_SECURE_INTERRUPTS();\r
+ {\r
+ /* Add this block to the list of free blocks. */\r
+ xFreeBytesRemaining += pxLink->xBlockSize;\r
+ traceFREE( pv, pxLink->xBlockSize );\r
+ prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );\r
+ }\r
+ secureportENABLE_NON_SECURE_INTERRUPTS();\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
\r
size_t xPortGetFreeHeapSize( void )\r
{\r
- return xFreeBytesRemaining;\r
+ return xFreeBytesRemaining;\r
}\r
/*-----------------------------------------------------------*/\r
\r
size_t xPortGetMinimumEverFreeHeapSize( void )\r
{\r
- return xMinimumEverFreeBytesRemaining;\r
+ return xMinimumEverFreeBytesRemaining;\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vPortInitialiseBlocks( void )\r
{\r
- /* This just exists to keep the linker quiet. */\r
+ /* This just exists to keep the linker quiet. */\r
}\r
/*-----------------------------------------------------------*/\r
/**\r
* @brief Constants required to manipulate the SCB.\r
*/\r
-#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */\r
-#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL )\r
-#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )\r
-#define secureinitSCB_AIRCR_PRIS_POS ( 14UL )\r
-#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS )\r
+#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */\r
+#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL )\r
+#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )\r
+#define secureinitSCB_AIRCR_PRIS_POS ( 14UL )\r
+#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS )\r
\r
/**\r
* @brief Constants required to manipulate the FPU.\r
*/\r
-#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */\r
-#define secureinitFPCCR_LSPENS_POS ( 29UL )\r
-#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS )\r
-#define secureinitFPCCR_TS_POS ( 26UL )\r
-#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS )\r
+#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */\r
+#define secureinitFPCCR_LSPENS_POS ( 29UL )\r
+#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS )\r
+#define secureinitFPCCR_TS_POS ( 26UL )\r
+#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS )\r
\r
-#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */\r
-#define secureinitNSACR_CP10_POS ( 10UL )\r
-#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS )\r
-#define secureinitNSACR_CP11_POS ( 11UL )\r
-#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS )\r
+#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */\r
+#define secureinitNSACR_CP10_POS ( 10UL )\r
+#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS )\r
+#define secureinitNSACR_CP11_POS ( 11UL )\r
+#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS )\r
/*-----------------------------------------------------------*/\r
\r
secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )\r
{\r
- uint32_t ulIPSR;\r
+ uint32_t ulIPSR;\r
\r
- /* Read the Interrupt Program Status Register (IPSR) value. */\r
- secureportREAD_IPSR( ulIPSR );\r
+ /* Read the Interrupt Program Status Register (IPSR) value. */\r
+ secureportREAD_IPSR( ulIPSR );\r
\r
- /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
- * when the processor is running in the Thread Mode. */\r
- if( ulIPSR != 0 )\r
- {\r
- *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |\r
- ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |\r
- ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK );\r
- }\r
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
+ * when the processor is running in the Thread Mode. */\r
+ if( ulIPSR != 0 )\r
+ {\r
+ *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |\r
+ ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |\r
+ ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK );\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
\r
secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )\r
{\r
- uint32_t ulIPSR;\r
+ uint32_t ulIPSR;\r
\r
- /* Read the Interrupt Program Status Register (IPSR) value. */\r
- secureportREAD_IPSR( ulIPSR );\r
+ /* Read the Interrupt Program Status Register (IPSR) value. */\r
+ secureportREAD_IPSR( ulIPSR );\r
\r
- /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
- * when the processor is running in the Thread Mode. */\r
- if( ulIPSR != 0 )\r
- {\r
- /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is\r
- * permitted. CP11 should be programmed to the same value as CP10. */\r
- *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );\r
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
+ * when the processor is running in the Thread Mode. */\r
+ if( ulIPSR != 0 )\r
+ {\r
+ /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is\r
+ * permitted. CP11 should be programmed to the same value as CP10. */\r
+ *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );\r
\r
- /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures\r
- * that we can enable/disable lazy stacking in port.c file. */\r
- *( secureinitFPCCR ) &= ~ ( secureinitFPCCR_LSPENS_MASK );\r
+ /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures\r
+ * that we can enable/disable lazy stacking in port.c file. */\r
+ *( secureinitFPCCR ) &= ~ ( secureinitFPCCR_LSPENS_MASK );\r
\r
- /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP\r
- * registers (S16-S31) are also pushed to stack on exception entry and\r
- * restored on exception return. */\r
- *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );\r
- }\r
+ /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP\r
+ * registers (S16-S31) are also pushed to stack on exception entry and\r
+ * restored on exception return. */\r
+ *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
/**\r
* @brief Byte alignment requirements.\r
*/\r
-#define secureportBYTE_ALIGNMENT 8\r
-#define secureportBYTE_ALIGNMENT_MASK ( 0x0007 )\r
+#define secureportBYTE_ALIGNMENT 8\r
+#define secureportBYTE_ALIGNMENT_MASK ( 0x0007 )\r
\r
/**\r
* @brief Macro to declare a function as non-secure callable.\r
*/\r
#if defined( __IAR_SYSTEMS_ICC__ )\r
- #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry\r
+ #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry\r
#else\r
- #define secureportNON_SECURE_CALLABLE __attribute__((cmse_nonsecure_entry))\r
+ #define secureportNON_SECURE_CALLABLE __attribute__((cmse_nonsecure_entry))\r
#endif\r
\r
/**\r
* @brief Set the secure PRIMASK value.\r
*/\r
#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \\r
- __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )\r
+ __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )\r
\r
/**\r
* @brief Set the non-secure PRIMASK value.\r
*/\r
#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \\r
- __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )\r
+ __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )\r
\r
/**\r
* @brief Read the PSP value in the given variable.\r
*/\r
#define secureportREAD_PSP( pucOutCurrentStackPointer ) \\r
- __asm volatile ( "mrs %0, psp" : "=r" ( pucOutCurrentStackPointer ) )\r
+ __asm volatile ( "mrs %0, psp" : "=r" ( pucOutCurrentStackPointer ) )\r
\r
/**\r
* @brief Set the PSP to the given value.\r
*/\r
#define secureportSET_PSP( pucCurrentStackPointer ) \\r
- __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )\r
+ __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )\r
\r
/**\r
* @brief Set the PSPLIM to the given value.\r
*/\r
#define secureportSET_PSPLIM( pucStackLimit ) \\r
- __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )\r
+ __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )\r
\r
/**\r
* @brief Set the NonSecure MSP to the given value.\r
*/\r
#define secureportSET_MSP_NS( pucMainStackPointer ) \\r
- __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )\r
+ __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )\r
\r
/**\r
* @brief Set the CONTROL register to the given value.\r
*/\r
#define secureportSET_CONTROL( ulControl ) \\r
- __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )\r
+ __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )\r
\r
/**\r
* @brief Read the Interrupt Program Status Register (IPSR) value in the given\r
* variable.\r
*/\r
#define secureportREAD_IPSR( ulIPSR ) \\r
- __asm volatile ( "mrs %0, ipsr" : "=r" ( ulIPSR ) )\r
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulIPSR ) )\r
\r
/**\r
* @brief PRIMASK value to enable interrupts.\r
*/\r
-#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL 0\r
+#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL 0\r
\r
/**\r
* @brief PRIMASK value to disable interrupts.\r
*/\r
-#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL 1\r
+#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL 1\r
\r
/**\r
* @brief Disable secure interrupts.\r
*/\r
-#define secureportDISABLE_SECURE_INTERRUPTS() secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )\r
+#define secureportDISABLE_SECURE_INTERRUPTS() secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )\r
\r
/**\r
* @brief Disable non-secure interrupts.\r
*\r
* This effectively disables context switches.\r
*/\r
-#define secureportDISABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )\r
+#define secureportDISABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )\r
\r
/**\r
* @brief Enable non-secure interrupts.\r
*/\r
-#define secureportENABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )\r
+#define secureportENABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )\r
\r
/**\r
* @brief Assert definition.\r
*/\r
-#define secureportASSERT( x ) \\r
- if( ( x ) == 0 ) \\r
- { \\r
- secureportDISABLE_SECURE_INTERRUPTS(); \\r
- secureportDISABLE_NON_SECURE_INTERRUPTS(); \\r
- for( ;; ); \\r
- }\r
+#define secureportASSERT( x ) \\r
+ if( ( x ) == 0 ) \\r
+ { \\r
+ secureportDISABLE_SECURE_INTERRUPTS(); \\r
+ secureportDISABLE_NON_SECURE_INTERRUPTS(); \\r
+ for( ;; ); \\r
+ }\r
\r
#endif /* __SECURE_PORT_MACROS_H__ */\r
#include "portasm.h"\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
- /* Secure components includes. */\r
- #include "secure_context.h"\r
- #include "secure_init.h"\r
+ /* Secure components includes. */\r
+ #include "secure_context.h"\r
+ #include "secure_init.h"\r
#endif /* configENABLE_TRUSTZONE */\r
\r
#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
+/**\r
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only\r
+ * i.e. the processor boots as secure and never jumps to the non-secure side.\r
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS\r
+ * on the secure side. The following are the valid configuration seetings:\r
+ *\r
+ * 1. Run FreeRTOS on the Secure Side:\r
+ * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0\r
+ *\r
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:\r
+ * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1\r
+ *\r
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:\r
+ * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0\r
+ */\r
+#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )\r
+ #error Trust Zone needs to be disabled in order to run FreeRTOS on the Secure Side.\r
+#endif\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Constants required to manipulate the NVIC.\r
*/\r
-#define portNVIC_SYSTICK_CTRL ( ( volatile uint32_t * ) 0xe000e010 )\r
-#define portNVIC_SYSTICK_LOAD ( ( volatile uint32_t * ) 0xe000e014 )\r
-#define portNVIC_SYSTICK_CURRENT_VALUE ( ( volatile uint32_t * ) 0xe000e018 )\r
-#define portNVIC_INT_CTRL ( ( volatile uint32_t * ) 0xe000ed04 )\r
-#define portNVIC_SYSPRI2 ( ( volatile uint32_t * ) 0xe000ed20 )\r
-#define portNVIC_SYSTICK_CLK ( 0x00000004 )\r
-#define portNVIC_SYSTICK_INT ( 0x00000002 )\r
-#define portNVIC_SYSTICK_ENABLE ( 0x00000001 )\r
-#define portNVIC_PENDSVSET ( 0x10000000 )\r
-#define portMIN_INTERRUPT_PRIORITY ( 255UL )\r
-#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )\r
-#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )\r
+#define portNVIC_SYSTICK_CTRL ( ( volatile uint32_t * ) 0xe000e010 )\r
+#define portNVIC_SYSTICK_LOAD ( ( volatile uint32_t * ) 0xe000e014 )\r
+#define portNVIC_SYSTICK_CURRENT_VALUE ( ( volatile uint32_t * ) 0xe000e018 )\r
+#define portNVIC_INT_CTRL ( ( volatile uint32_t * ) 0xe000ed04 )\r
+#define portNVIC_SYSPRI2 ( ( volatile uint32_t * ) 0xe000ed20 )\r
+#define portNVIC_SYSTICK_CLK ( 0x00000004 )\r
+#define portNVIC_SYSTICK_INT ( 0x00000002 )\r
+#define portNVIC_SYSTICK_ENABLE ( 0x00000001 )\r
+#define portNVIC_PENDSVSET ( 0x10000000 )\r
+#define portMIN_INTERRUPT_PRIORITY ( 255UL )\r
+#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )\r
+#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Constants required to manipulate the SCB.\r
*/\r
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( * ( volatile uint32_t * ) 0xe000ed24 )\r
-#define portSCB_MEM_FAULT_ENABLE ( 1UL << 16UL )\r
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( * ( volatile uint32_t * ) 0xe000ed24 )\r
+#define portSCB_MEM_FAULT_ENABLE ( 1UL << 16UL )\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Constants required to manipulate the FPU.\r
*/\r
-#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */\r
-#define portCPACR_CP10_VALUE ( 3UL )\r
-#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE\r
-#define portCPACR_CP10_POS ( 20UL )\r
-#define portCPACR_CP11_POS ( 22UL )\r
-\r
-#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */\r
-#define portFPCCR_ASPEN_POS ( 31UL )\r
-#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS )\r
-#define portFPCCR_LSPEN_POS ( 30UL )\r
-#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS )\r
+#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */\r
+#define portCPACR_CP10_VALUE ( 3UL )\r
+#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE\r
+#define portCPACR_CP10_POS ( 20UL )\r
+#define portCPACR_CP11_POS ( 22UL )\r
+\r
+#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */\r
+#define portFPCCR_ASPEN_POS ( 31UL )\r
+#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS )\r
+#define portFPCCR_LSPEN_POS ( 30UL )\r
+#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS )\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Constants required to manipulate the MPU.\r
*/\r
-#define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )\r
-#define portMPU_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )\r
-#define portMPU_RNR_REG ( * ( ( volatile uint32_t * ) 0xe000ed98 ) )\r
+#define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )\r
+#define portMPU_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )\r
+#define portMPU_RNR_REG ( * ( ( volatile uint32_t * ) 0xe000ed98 ) )\r
\r
-#define portMPU_RBAR_REG ( * ( ( volatile uint32_t * ) 0xe000ed9c ) )\r
-#define portMPU_RLAR_REG ( * ( ( volatile uint32_t * ) 0xe000eda0 ) )\r
+#define portMPU_RBAR_REG ( * ( ( volatile uint32_t * ) 0xe000ed9c ) )\r
+#define portMPU_RLAR_REG ( * ( ( volatile uint32_t * ) 0xe000eda0 ) )\r
\r
-#define portMPU_RBAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda4 ) )\r
-#define portMPU_RLAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda8 ) )\r
+#define portMPU_RBAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda4 ) )\r
+#define portMPU_RLAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda8 ) )\r
\r
-#define portMPU_RBAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edac ) )\r
-#define portMPU_RLAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edb0 ) )\r
+#define portMPU_RBAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edac ) )\r
+#define portMPU_RLAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edb0 ) )\r
\r
-#define portMPU_RBAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb4 ) )\r
-#define portMPU_RLAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb8 ) )\r
+#define portMPU_RBAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb4 ) )\r
+#define portMPU_RLAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb8 ) )\r
\r
-#define portMPU_MAIR0_REG ( * ( ( volatile uint32_t * ) 0xe000edc0 ) )\r
-#define portMPU_MAIR1_REG ( * ( ( volatile uint32_t * ) 0xe000edc4 ) )\r
+#define portMPU_MAIR0_REG ( * ( ( volatile uint32_t * ) 0xe000edc0 ) )\r
+#define portMPU_MAIR1_REG ( * ( ( volatile uint32_t * ) 0xe000edc4 ) )\r
\r
-#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
-#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
+#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
+#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
\r
-#define portMPU_MAIR_ATTR0_POS ( 0UL )\r
-#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )\r
+#define portMPU_MAIR_ATTR0_POS ( 0UL )\r
+#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )\r
\r
-#define portMPU_MAIR_ATTR1_POS ( 8UL )\r
-#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )\r
+#define portMPU_MAIR_ATTR1_POS ( 8UL )\r
+#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )\r
\r
-#define portMPU_MAIR_ATTR2_POS ( 16UL )\r
-#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )\r
+#define portMPU_MAIR_ATTR2_POS ( 16UL )\r
+#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )\r
\r
-#define portMPU_MAIR_ATTR3_POS ( 24UL )\r
-#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )\r
+#define portMPU_MAIR_ATTR3_POS ( 24UL )\r
+#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )\r
\r
-#define portMPU_MAIR_ATTR4_POS ( 0UL )\r
-#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )\r
+#define portMPU_MAIR_ATTR4_POS ( 0UL )\r
+#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )\r
\r
-#define portMPU_MAIR_ATTR5_POS ( 8UL )\r
-#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )\r
+#define portMPU_MAIR_ATTR5_POS ( 8UL )\r
+#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )\r
\r
-#define portMPU_MAIR_ATTR6_POS ( 16UL )\r
-#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )\r
+#define portMPU_MAIR_ATTR6_POS ( 16UL )\r
+#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )\r
\r
-#define portMPU_MAIR_ATTR7_POS ( 24UL )\r
-#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )\r
+#define portMPU_MAIR_ATTR7_POS ( 24UL )\r
+#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )\r
\r
-#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )\r
-#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )\r
-#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )\r
-#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )\r
-#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )\r
-#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )\r
-#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )\r
-#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )\r
\r
-#define portMPU_RLAR_REGION_ENABLE ( 1UL )\r
+#define portMPU_RLAR_REGION_ENABLE ( 1UL )\r
\r
/* Enable privileged access to unmapped region. */\r
-#define portMPU_PRIV_BACKGROUND_ENABLE ( 1UL << 2UL )\r
+#define portMPU_PRIV_BACKGROUND_ENABLE ( 1UL << 2UL )\r
\r
/* Enable MPU. */\r
-#define portMPU_ENABLE ( 1UL << 0UL )\r
+#define portMPU_ENABLE ( 1UL << 0UL )\r
\r
/* Expected value of the portMPU_TYPE register. */\r
-#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */\r
+#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Constants required to set up the initial stack.\r
*/\r
-#define portINITIAL_XPSR ( 0x01000000 )\r
-\r
-/**\r
- * @brief Initial EXC_RETURN value.\r
- *\r
- * FF FF FF BC\r
- * 1111 1111 1111 1111 1111 1111 1011 1100\r
- *\r
- * Bit[6] - 0 --> The exception was taken from the Non-Secure state.\r
- * Bit[5] - 1 --> Do not skip stacking of additional state context.\r
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\r
- * Bit[3] - 1 --> Return to the Thread mode.\r
- * Bit[2] - 1 --> Restore registers from the process stack.\r
- * Bit[1] - 0 --> Reserved, 0.\r
- * Bit[0] - 0 --> The exception was taken to the Non-Secure state.\r
- */\r
-#define portINITIAL_EXC_RETURN ( 0xffffffbc )\r
+#define portINITIAL_XPSR ( 0x01000000 )\r
+\r
+#if( configRUN_FREERTOS_SECURE_ONLY == 1 )\r
+ /**\r
+ * @brief Initial EXC_RETURN value.\r
+ *\r
+ * FF FF FF FD\r
+ * 1111 1111 1111 1111 1111 1111 1111 1101\r
+ *\r
+ * Bit[6] - 1 --> The exception was taken from the Secure state.\r
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.\r
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\r
+ * Bit[3] - 1 --> Return to the Thread mode.\r
+ * Bit[2] - 1 --> Restore registers from the process stack.\r
+ * Bit[1] - 0 --> Reserved, 0.\r
+ * Bit[0] - 1 --> The exception was taken to the Secure state.\r
+ */\r
+ #define portINITIAL_EXC_RETURN ( 0xfffffffd )\r
+#else\r
+ /**\r
+ * @brief Initial EXC_RETURN value.\r
+ *\r
+ * FF FF FF BC\r
+ * 1111 1111 1111 1111 1111 1111 1011 1100\r
+ *\r
+ * Bit[6] - 0 --> The exception was taken from the Non-Secure state.\r
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.\r
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\r
+ * Bit[3] - 1 --> Return to the Thread mode.\r
+ * Bit[2] - 1 --> Restore registers from the process stack.\r
+ * Bit[1] - 0 --> Reserved, 0.\r
+ * Bit[0] - 0 --> The exception was taken to the Non-Secure state.\r
+ */\r
+ #define portINITIAL_EXC_RETURN ( 0xffffffbc )\r
+#endif /* configRUN_FREERTOS_SECURE_ONLY */\r
\r
/**\r
* @brief CONTROL register privileged bit mask.\r
* Bit[0] = 0 ==> The task is privileged.\r
* Bit[0] = 1 ==> The task is not privileged.\r
*/\r
-#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL )\r
+#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL )\r
\r
/**\r
* @brief Initial CONTROL register values.\r
*/\r
-#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 )\r
-#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 )\r
+#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 )\r
+#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 )\r
\r
/**\r
* @brief Let the user override the pre-loading of the initial LR with the\r
* in the debugger.\r
*/\r
#ifdef configTASK_RETURN_ADDRESS\r
- #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS\r
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS\r
#else\r
- #define portTASK_RETURN_ADDRESS prvTaskExitError\r
+ #define portTASK_RETURN_ADDRESS prvTaskExitError\r
#endif\r
\r
/**\r
* @brief If portPRELOAD_REGISTERS then registers will be given an initial value\r
* when a task is created. This helps in debugging at the cost of code size.\r
*/\r
-#define portPRELOAD_REGISTERS 1\r
+#define portPRELOAD_REGISTERS 1\r
\r
/**\r
* @brief A task is created without a secure context, and must call\r
* portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes\r
* any secure calls.\r
*/\r
-#define portNO_SECURE_CONTEXT 0\r
+#define portNO_SECURE_CONTEXT 0\r
/*-----------------------------------------------------------*/\r
\r
/**\r
static void prvTaskExitError( void );\r
\r
#if( configENABLE_MPU == 1 )\r
- /**\r
- * @brief Setup the Memory Protection Unit (MPU).\r
- */\r
- static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\r
+ /**\r
+ * @brief Setup the Memory Protection Unit (MPU).\r
+ */\r
+ static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\r
#endif /* configENABLE_MPU */\r
\r
#if( configENABLE_FPU == 1 )\r
- /**\r
- * @brief Setup the Floating Point Unit (FPU).\r
- */\r
- static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\r
+ /**\r
+ * @brief Setup the Floating Point Unit (FPU).\r
+ */\r
+ static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\r
#endif /* configENABLE_FPU */\r
\r
/**\r
static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
- /**\r
- * @brief Saved as part of the task context to indicate which context the\r
- * task is using on the secure side.\r
- */\r
- volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\r
+ /**\r
+ * @brief Saved as part of the task context to indicate which context the\r
+ * task is using on the secure side.\r
+ */\r
+ volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\r
#endif /* configENABLE_TRUSTZONE */\r
/*-----------------------------------------------------------*/\r
\r
static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\r
{\r
- /* Stop and reset the SysTick. */\r
- *( portNVIC_SYSTICK_CTRL ) = 0UL;\r
- *( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;\r
+ /* Stop and reset the SysTick. */\r
+ *( portNVIC_SYSTICK_CTRL ) = 0UL;\r
+ *( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;\r
\r
- /* Configure SysTick to interrupt at the requested rate. */\r
- *( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
- *( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
+ /* Configure SysTick to interrupt at the requested rate. */\r
+ *( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
+ *( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
}\r
/*-----------------------------------------------------------*/\r
\r
{\r
volatile uint32_t ulDummy = 0UL;\r
\r
- /* A function that implements a task must not exit or attempt to return to\r
- * its caller as there is nothing to return to. If a task wants to exit it\r
- * should instead call vTaskDelete( NULL ). Artificially force an assert()\r
- * to be triggered if configASSERT() is defined, then stop here so\r
- * application writers can catch the error. */\r
- configASSERT( ulCriticalNesting == ~0UL );\r
- portDISABLE_INTERRUPTS();\r
-\r
- while( ulDummy == 0 )\r
- {\r
- /* This file calls prvTaskExitError() after the scheduler has been\r
- * started to remove a compiler warning about the function being\r
- * defined but never called. ulDummy is used purely to quieten other\r
- * warnings about code appearing after this function is called - making\r
- * ulDummy volatile makes the compiler think the function could return\r
- * and therefore not output an 'unreachable code' warning for code that\r
- * appears after it. */\r
- }\r
+ /* A function that implements a task must not exit or attempt to return to\r
+ * its caller as there is nothing to return to. If a task wants to exit it\r
+ * should instead call vTaskDelete( NULL ). Artificially force an assert()\r
+ * to be triggered if configASSERT() is defined, then stop here so\r
+ * application writers can catch the error. */\r
+ configASSERT( ulCriticalNesting == ~0UL );\r
+ portDISABLE_INTERRUPTS();\r
+\r
+ while( ulDummy == 0 )\r
+ {\r
+ /* This file calls prvTaskExitError() after the scheduler has been\r
+ * started to remove a compiler warning about the function being\r
+ * defined but never called. ulDummy is used purely to quieten other\r
+ * warnings about code appearing after this function is called - making\r
+ * ulDummy volatile makes the compiler think the function could return\r
+ * and therefore not output an 'unreachable code' warning for code that\r
+ * appears after it. */\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
\r
#if( configENABLE_MPU == 1 )\r
- static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */\r
- {\r
- #if defined( __ARMCC_VERSION )\r
- /* Declaration when these variable are defined in code instead of being\r
- * exported from linker scripts. */\r
- extern uint32_t * __privileged_functions_start__;\r
- extern uint32_t * __privileged_functions_end__;\r
- extern uint32_t * __syscalls_flash_start__;\r
- extern uint32_t * __unprivileged_flash_end__;\r
- extern uint32_t * __privileged_sram_start__;\r
- extern uint32_t * __privileged_sram_end__;\r
- #else\r
- /* Declaration when these variable are exported from linker scripts. */\r
- extern uint32_t __privileged_functions_start__[];\r
- extern uint32_t __privileged_functions_end__[];\r
- extern uint32_t __syscalls_flash_start__[];\r
- extern uint32_t __unprivileged_flash_end__[];\r
- extern uint32_t __privileged_sram_start__[];\r
- extern uint32_t __privileged_sram_end__[];\r
- #endif /* defined( __ARMCC_VERSION ) */\r
-\r
- /* Check that the MPU is present. */\r
- if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\r
- {\r
- /* MAIR0 - Index 0. */\r
- portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
- /* MAIR0 - Index 1. */\r
- portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
-\r
- /* Setup privileged flash as Read Only so that privileged tasks can\r
- * read it but not modify. */\r
- portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;\r
- portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
- ( portMPU_REGION_NON_SHAREABLE ) |\r
- ( portMPU_REGION_PRIVILEGED_READ_ONLY );\r
- portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
- ( portMPU_RLAR_ATTR_INDEX0 ) |\r
- ( portMPU_RLAR_REGION_ENABLE );\r
-\r
- /* Setup unprivileged flash and system calls flash as Read Only by\r
- * both privileged and unprivileged tasks. All tasks can read it but\r
- * no-one can modify. */\r
- portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;\r
- portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
- ( portMPU_REGION_NON_SHAREABLE ) |\r
- ( portMPU_REGION_READ_ONLY );\r
- portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
- ( portMPU_RLAR_ATTR_INDEX0 ) |\r
- ( portMPU_RLAR_REGION_ENABLE );\r
-\r
- /* Setup RAM containing kernel data for privileged access only. */\r
- portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;\r
- portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
- ( portMPU_REGION_NON_SHAREABLE ) |\r
- ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
- ( portMPU_REGION_EXECUTE_NEVER );\r
- portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
- ( portMPU_RLAR_ATTR_INDEX0 ) |\r
- ( portMPU_RLAR_REGION_ENABLE );\r
-\r
- /* By default allow everything to access the general peripherals.\r
- * The system peripherals and registers are protected. */\r
- portMPU_RNR_REG = portUNPRIVILEGED_DEVICE_REGION;\r
- portMPU_RBAR_REG = ( ( ( uint32_t ) portDEVICE_REGION_START_ADDRESS ) & portMPU_RBAR_ADDRESS_MASK ) |\r
- ( portMPU_REGION_NON_SHAREABLE ) |\r
- ( portMPU_REGION_READ_WRITE ) |\r
- ( portMPU_REGION_EXECUTE_NEVER );\r
- portMPU_RLAR_REG = ( ( ( uint32_t ) portDEVICE_REGION_END_ADDRESS ) & portMPU_RLAR_ADDRESS_MASK ) |\r
- ( portMPU_RLAR_ATTR_INDEX1 ) |\r
- ( portMPU_RLAR_REGION_ENABLE );\r
-\r
- /* Enable mem fault. */\r
- portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;\r
-\r
- /* Enable MPU with privileged background access i.e. unmapped\r
- * regions have privileged access. */\r
- portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );\r
- }\r
- }\r
+ static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */\r
+ {\r
+ #if defined( __ARMCC_VERSION )\r
+ /* Declaration when these variable are defined in code instead of being\r
+ * exported from linker scripts. */\r
+ extern uint32_t * __privileged_functions_start__;\r
+ extern uint32_t * __privileged_functions_end__;\r
+ extern uint32_t * __syscalls_flash_start__;\r
+ extern uint32_t * __unprivileged_flash_end__;\r
+ extern uint32_t * __privileged_sram_start__;\r
+ extern uint32_t * __privileged_sram_end__;\r
+ #else\r
+ /* Declaration when these variable are exported from linker scripts. */\r
+ extern uint32_t __privileged_functions_start__[];\r
+ extern uint32_t __privileged_functions_end__[];\r
+ extern uint32_t __syscalls_flash_start__[];\r
+ extern uint32_t __unprivileged_flash_end__[];\r
+ extern uint32_t __privileged_sram_start__[];\r
+ extern uint32_t __privileged_sram_end__[];\r
+ #endif /* defined( __ARMCC_VERSION ) */\r
+\r
+ /* Check that the MPU is present. */\r
+ if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\r
+ {\r
+ /* MAIR0 - Index 0. */\r
+ portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
+ /* MAIR0 - Index 1. */\r
+ portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
+\r
+ /* Setup privileged flash as Read Only so that privileged tasks can\r
+ * read it but not modify. */\r
+ portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_PRIVILEGED_READ_ONLY );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Setup unprivileged flash and system calls flash as Read Only by\r
+ * both privileged and unprivileged tasks. All tasks can read it but\r
+ * no-one can modify. */\r
+ portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_ONLY );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Setup RAM containing kernel data for privileged access only. */\r
+ portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
+ ( portMPU_REGION_EXECUTE_NEVER );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* By default allow everything to access the general peripherals.\r
+ * The system peripherals and registers are protected. */\r
+ portMPU_RNR_REG = portUNPRIVILEGED_DEVICE_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) portDEVICE_REGION_START_ADDRESS ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_WRITE ) |\r
+ ( portMPU_REGION_EXECUTE_NEVER );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) portDEVICE_REGION_END_ADDRESS ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX1 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Enable mem fault. */\r
+ portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;\r
+\r
+ /* Enable MPU with privileged background access i.e. unmapped\r
+ * regions have privileged access. */\r
+ portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );\r
+ }\r
+ }\r
#endif /* configENABLE_MPU */\r
/*-----------------------------------------------------------*/\r
\r
#if( configENABLE_FPU == 1 )\r
- static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */\r
- {\r
- #if( configENABLE_TRUSTZONE == 1 )\r
- {\r
- /* Enable non-secure access to the FPU. */\r
- SecureInit_EnableNSFPUAccess();\r
- }\r
- #endif /* configENABLE_TRUSTZONE */\r
-\r
- /* CP10 = 11 ==> Full access to FPU i.e. both privileged and\r
- * unprivileged code should be able to access FPU. CP11 should be\r
- * programmed to the same value as CP10. */\r
- *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |\r
- ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )\r
- );\r
-\r
- /* ASPEN = 1 ==> Hardware should automatically preserve floating point\r
- * context on exception entry and restore on exception return.\r
- * LSPEN = 1 ==> Enable lazy context save of FP state. */\r
- *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );\r
- }\r
+ static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */\r
+ {\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ /* Enable non-secure access to the FPU. */\r
+ SecureInit_EnableNSFPUAccess();\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+\r
+ /* CP10 = 11 ==> Full access to FPU i.e. both privileged and\r
+ * unprivileged code should be able to access FPU. CP11 should be\r
+ * programmed to the same value as CP10. */\r
+ *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |\r
+ ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )\r
+ );\r
+\r
+ /* ASPEN = 1 ==> Hardware should automatically preserve floating point\r
+ * context on exception entry and restore on exception return.\r
+ * LSPEN = 1 ==> Enable lazy context save of FP state. */\r
+ *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );\r
+ }\r
#endif /* configENABLE_FPU */\r
/*-----------------------------------------------------------*/\r
\r
void vPortYield( void ) /* PRIVILEGED_FUNCTION */\r
{\r
- /* Set a PendSV to request a context switch. */\r
- *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
+ /* Set a PendSV to request a context switch. */\r
+ *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
\r
- /* Barriers are normally not required but do ensure the code is\r
- * completely within the specified behaviour for the architecture. */\r
- __asm volatile( "dsb" ::: "memory" );\r
- __asm volatile( "isb" );\r
+ /* Barriers are normally not required but do ensure the code is\r
+ * completely within the specified behaviour for the architecture. */\r
+ __asm volatile( "dsb" ::: "memory" );\r
+ __asm volatile( "isb" );\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */\r
{\r
- portDISABLE_INTERRUPTS();\r
- ulCriticalNesting++;\r
+ portDISABLE_INTERRUPTS();\r
+ ulCriticalNesting++;\r
\r
- /* Barriers are normally not required but do ensure the code is\r
- * completely within the specified behaviour for the architecture. */\r
- __asm volatile( "dsb" ::: "memory" );\r
- __asm volatile( "isb" );\r
+ /* Barriers are normally not required but do ensure the code is\r
+ * completely within the specified behaviour for the architecture. */\r
+ __asm volatile( "dsb" ::: "memory" );\r
+ __asm volatile( "isb" );\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */\r
{\r
- configASSERT( ulCriticalNesting );\r
- ulCriticalNesting--;\r
+ configASSERT( ulCriticalNesting );\r
+ ulCriticalNesting--;\r
\r
- if( ulCriticalNesting == 0 )\r
- {\r
- portENABLE_INTERRUPTS();\r
- }\r
+ if( ulCriticalNesting == 0 )\r
+ {\r
+ portENABLE_INTERRUPTS();\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
\r
{\r
uint32_t ulPreviousMask;\r
\r
- ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();\r
- {\r
- /* Increment the RTOS tick. */\r
- if( xTaskIncrementTick() != pdFALSE )\r
- {\r
- /* Pend a context switch. */\r
- *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
- }\r
- }\r
- portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );\r
+ ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();\r
+ {\r
+ /* Increment the RTOS tick. */\r
+ if( xTaskIncrementTick() != pdFALSE )\r
+ {\r
+ /* Pend a context switch. */\r
+ *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
+ }\r
+ }\r
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION */\r
{\r
#if( configENABLE_MPU == 1 )\r
- #if defined( __ARMCC_VERSION )\r
- /* Declaration when these variable are defined in code instead of being\r
- * exported from linker scripts. */\r
- extern uint32_t * __syscalls_flash_start__;\r
- extern uint32_t * __syscalls_flash_end__;\r
- #else\r
- /* Declaration when these variable are exported from linker scripts. */\r
- extern uint32_t __syscalls_flash_start__[];\r
- extern uint32_t __syscalls_flash_end__[];\r
- #endif /* defined( __ARMCC_VERSION ) */\r
+ #if defined( __ARMCC_VERSION )\r
+ /* Declaration when these variable are defined in code instead of being\r
+ * exported from linker scripts. */\r
+ extern uint32_t * __syscalls_flash_start__;\r
+ extern uint32_t * __syscalls_flash_end__;\r
+ #else\r
+ /* Declaration when these variable are exported from linker scripts. */\r
+ extern uint32_t __syscalls_flash_start__[];\r
+ extern uint32_t __syscalls_flash_end__[];\r
+ #endif /* defined( __ARMCC_VERSION ) */\r
#endif /* configENABLE_MPU */\r
\r
uint32_t ulPC;\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
- uint32_t ulR0;\r
- #if( configENABLE_MPU == 1 )\r
- uint32_t ulControl, ulIsTaskPrivileged;\r
- #endif /* configENABLE_MPU */\r
+ uint32_t ulR0;\r
+ #if( configENABLE_MPU == 1 )\r
+ uint32_t ulControl, ulIsTaskPrivileged;\r
+ #endif /* configENABLE_MPU */\r
#endif /* configENABLE_TRUSTZONE */\r
uint8_t ucSVCNumber;\r
\r
- /* Register are stored on the stack in the following order - R0, R1, R2, R3,\r
- * R12, LR, PC, xPSR. */\r
- ulPC = pulCallerStackAddress[ 6 ];\r
- ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];\r
-\r
- switch( ucSVCNumber )\r
- {\r
- #if( configENABLE_TRUSTZONE == 1 )\r
- case portSVC_ALLOCATE_SECURE_CONTEXT:\r
- {\r
- /* R0 contains the stack size passed as parameter to the\r
- * vPortAllocateSecureContext function. */\r
- ulR0 = pulCallerStackAddress[ 0 ];\r
-\r
- #if( configENABLE_MPU == 1 )\r
- {\r
- /* Read the CONTROL register value. */\r
- __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );\r
-\r
- /* The task that raised the SVC is privileged if Bit[0]\r
- * in the CONTROL register is 0. */\r
- ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );\r
-\r
- /* Allocate and load a context for the secure task. */\r
- xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );\r
- }\r
- #else\r
- {\r
- /* Allocate and load a context for the secure task. */\r
- xSecureContext = SecureContext_AllocateContext( ulR0 );\r
- }\r
- #endif /* configENABLE_MPU */\r
-\r
- configASSERT( xSecureContext != NULL );\r
- SecureContext_LoadContext( xSecureContext );\r
- }\r
- break;\r
-\r
- case portSVC_FREE_SECURE_CONTEXT:\r
- {\r
- /* R0 contains the secure context handle to be freed. */\r
- ulR0 = pulCallerStackAddress[ 0 ];\r
-\r
- /* Free the secure context. */\r
- SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );\r
- }\r
- break;\r
- #endif /* configENABLE_TRUSTZONE */\r
-\r
- case portSVC_START_SCHEDULER:\r
- {\r
- #if( configENABLE_TRUSTZONE == 1 )\r
- {\r
- /* De-prioritize the non-secure exceptions so that the\r
- * non-secure pendSV runs at the lowest priority. */\r
- SecureInit_DePrioritizeNSExceptions();\r
-\r
- /* Initialize the secure context management system. */\r
- SecureContext_Init();\r
- }\r
- #endif /* configENABLE_TRUSTZONE */\r
-\r
- #if( configENABLE_FPU == 1 )\r
- {\r
- /* Setup the Floating Point Unit (FPU). */\r
- prvSetupFPU();\r
- }\r
- #endif /* configENABLE_FPU */\r
-\r
- /* Setup the context of the first task so that the first task starts\r
- * executing. */\r
- vRestoreContextOfFirstTask();\r
- }\r
- break;\r
-\r
- #if( configENABLE_MPU == 1 )\r
- case portSVC_RAISE_PRIVILEGE:\r
- {\r
- /* Only raise the privilege, if the svc was raised from any of\r
- * the system calls. */\r
- if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&\r
- ulPC <= ( uint32_t ) __syscalls_flash_end__ )\r
- {\r
- vRaisePrivilege();\r
- }\r
- }\r
- break;\r
- #endif /* configENABLE_MPU */\r
-\r
- default:\r
- {\r
- /* Incorrect SVC call. */\r
- configASSERT( pdFALSE );\r
- }\r
- }\r
+ /* Register are stored on the stack in the following order - R0, R1, R2, R3,\r
+ * R12, LR, PC, xPSR. */\r
+ ulPC = pulCallerStackAddress[ 6 ];\r
+ ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];\r
+\r
+ switch( ucSVCNumber )\r
+ {\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ case portSVC_ALLOCATE_SECURE_CONTEXT:\r
+ {\r
+ /* R0 contains the stack size passed as parameter to the\r
+ * vPortAllocateSecureContext function. */\r
+ ulR0 = pulCallerStackAddress[ 0 ];\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ /* Read the CONTROL register value. */\r
+ __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );\r
+\r
+ /* The task that raised the SVC is privileged if Bit[0]\r
+ * in the CONTROL register is 0. */\r
+ ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );\r
+\r
+ /* Allocate and load a context for the secure task. */\r
+ xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );\r
+ }\r
+ #else\r
+ {\r
+ /* Allocate and load a context for the secure task. */\r
+ xSecureContext = SecureContext_AllocateContext( ulR0 );\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ configASSERT( xSecureContext != NULL );\r
+ SecureContext_LoadContext( xSecureContext );\r
+ }\r
+ break;\r
+\r
+ case portSVC_FREE_SECURE_CONTEXT:\r
+ {\r
+ /* R0 contains the secure context handle to be freed. */\r
+ ulR0 = pulCallerStackAddress[ 0 ];\r
+\r
+ /* Free the secure context. */\r
+ SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );\r
+ }\r
+ break;\r
+ #endif /* configENABLE_TRUSTZONE */\r
+\r
+ case portSVC_START_SCHEDULER:\r
+ {\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ /* De-prioritize the non-secure exceptions so that the\r
+ * non-secure pendSV runs at the lowest priority. */\r
+ SecureInit_DePrioritizeNSExceptions();\r
+\r
+ /* Initialize the secure context management system. */\r
+ SecureContext_Init();\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+\r
+ #if( configENABLE_FPU == 1 )\r
+ {\r
+ /* Setup the Floating Point Unit (FPU). */\r
+ prvSetupFPU();\r
+ }\r
+ #endif /* configENABLE_FPU */\r
+\r
+ /* Setup the context of the first task so that the first task starts\r
+ * executing. */\r
+ vRestoreContextOfFirstTask();\r
+ }\r
+ break;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ case portSVC_RAISE_PRIVILEGE:\r
+ {\r
+ /* Only raise the privilege, if the svc was raised from any of\r
+ * the system calls. */\r
+ if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&\r
+ ulPC <= ( uint32_t ) __syscalls_flash_end__ )\r
+ {\r
+ vRaisePrivilege();\r
+ }\r
+ }\r
+ break;\r
+ #endif /* configENABLE_MPU */\r
+\r
+ default:\r
+ {\r
+ /* Incorrect SVC call. */\r
+ configASSERT( pdFALSE );\r
+ }\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
\r
#if( configENABLE_MPU == 1 )\r
- StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */\r
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */\r
#else\r
- StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */\r
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */\r
#endif /* configENABLE_MPU */\r
{\r
- /* Simulate the stack frame as it would be created by a context switch\r
- * interrupt. */\r
- #if( portPRELOAD_REGISTERS == 0 )\r
- {\r
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
- *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\r
- pxTopOfStack -= 5; /* R12, R3, R2 and R1. */\r
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
- pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */\r
- *pxTopOfStack = portINITIAL_EXC_RETURN;\r
-\r
- #if( configENABLE_MPU == 1 )\r
- {\r
- pxTopOfStack--;\r
- if( xRunPrivileged == pdTRUE )\r
- {\r
- *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
- }\r
- else\r
- {\r
- *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
- }\r
- }\r
- #endif /* configENABLE_MPU */\r
-\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\r
-\r
- #if( configENABLE_TRUSTZONE == 1 )\r
- {\r
- pxTopOfStack--;\r
- *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\r
- }\r
- #endif /* configENABLE_TRUSTZONE */\r
- }\r
- #else /* portPRELOAD_REGISTERS */\r
- {\r
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
- *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */\r
-\r
- #if( configENABLE_MPU == 1 )\r
- {\r
- pxTopOfStack--;\r
- if( xRunPrivileged == pdTRUE )\r
- {\r
- *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
- }\r
- else\r
- {\r
- *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
- }\r
- }\r
- #endif /* configENABLE_MPU */\r
-\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\r
-\r
- #if( configENABLE_TRUSTZONE == 1 )\r
- {\r
- pxTopOfStack--;\r
- *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\r
- }\r
- #endif /* configENABLE_TRUSTZONE */\r
- }\r
- #endif /* portPRELOAD_REGISTERS */\r
-\r
- return pxTopOfStack;\r
+ /* Simulate the stack frame as it would be created by a context switch\r
+ * interrupt. */\r
+ #if( portPRELOAD_REGISTERS == 0 )\r
+ {\r
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\r
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */\r
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
+ pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */\r
+ *pxTopOfStack = portINITIAL_EXC_RETURN;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ if( xRunPrivileged == pdTRUE )\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ else\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\r
+\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+ }\r
+ #else /* portPRELOAD_REGISTERS */\r
+ {\r
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ if( xRunPrivileged == pdTRUE )\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ else\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\r
+\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+ }\r
+ #endif /* portPRELOAD_REGISTERS */\r
+\r
+ return pxTopOfStack;\r
}\r
/*-----------------------------------------------------------*/\r
\r
BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */\r
{\r
- /* Make PendSV, CallSV and SysTick the same priority as the kernel. */\r
- *( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;\r
- *( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;\r
-\r
- #if( configENABLE_MPU == 1 )\r
- {\r
- /* Setup the Memory Protection Unit (MPU). */\r
- prvSetupMPU();\r
- }\r
- #endif /* configENABLE_MPU */\r
-\r
- /* Start the timer that generates the tick ISR. Interrupts are disabled\r
- * here already. */\r
- prvSetupTimerInterrupt();\r
-\r
- /* Initialize the critical nesting count ready for the first task. */\r
- ulCriticalNesting = 0;\r
-\r
- /* Start the first task. */\r
- vStartFirstTask();\r
-\r
- /* Should never get here as the tasks will now be executing. Call the task\r
- * exit error function to prevent compiler warnings about a static function\r
- * not being called in the case that the application writer overrides this\r
- * functionality by defining configTASK_RETURN_ADDRESS. Call\r
- * vTaskSwitchContext() so link time optimization does not remove the\r
- * symbol. */\r
- vTaskSwitchContext();\r
- prvTaskExitError();\r
-\r
- /* Should not get here. */\r
- return 0;\r
+ /* Make PendSV, CallSV and SysTick the same priority as the kernel. */\r
+ *( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;\r
+ *( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ /* Setup the Memory Protection Unit (MPU). */\r
+ prvSetupMPU();\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ /* Start the timer that generates the tick ISR. Interrupts are disabled\r
+ * here already. */\r
+ prvSetupTimerInterrupt();\r
+\r
+ /* Initialize the critical nesting count ready for the first task. */\r
+ ulCriticalNesting = 0;\r
+\r
+ /* Start the first task. */\r
+ vStartFirstTask();\r
+\r
+ /* Should never get here as the tasks will now be executing. Call the task\r
+ * exit error function to prevent compiler warnings about a static function\r
+ * not being called in the case that the application writer overrides this\r
+ * functionality by defining configTASK_RETURN_ADDRESS. Call\r
+ * vTaskSwitchContext() so link time optimization does not remove the\r
+ * symbol. */\r
+ vTaskSwitchContext();\r
+ prvTaskExitError();\r
+\r
+ /* Should not get here. */\r
+ return 0;\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */\r
{\r
- /* Not implemented in ports where there is nothing to return to.\r
- * Artificially force an assert. */\r
- configASSERT( ulCriticalNesting == 1000UL );\r
+ /* Not implemented in ports where there is nothing to return to.\r
+ * Artificially force an assert. */\r
+ configASSERT( ulCriticalNesting == 1000UL );\r
}\r
/*-----------------------------------------------------------*/\r
\r
#if( configENABLE_MPU == 1 )\r
- void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )\r
- {\r
- uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;\r
- int32_t lIndex = 0;\r
-\r
- /* Setup MAIR0. */\r
- xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
- xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
-\r
- /* This function is called automatically when the task is created - in\r
- * which case the stack region parameters will be valid. At all other\r
- * times the stack parameters will not be valid and it is assumed that\r
- * the stack region has already been configured. */\r
- if( ulStackDepth > 0 )\r
- {\r
- /* Define the region that allows access to the stack. */\r
- ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;\r
- ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;\r
- ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\r
-\r
- xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |\r
- ( portMPU_REGION_NON_SHAREABLE ) |\r
- ( portMPU_REGION_READ_WRITE ) |\r
- ( portMPU_REGION_EXECUTE_NEVER );\r
-\r
- xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |\r
- ( portMPU_RLAR_ATTR_INDEX0 ) |\r
- ( portMPU_RLAR_REGION_ENABLE );\r
- }\r
-\r
- /* User supplied configurable regions. */\r
- for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )\r
- {\r
- /* If xRegions is NULL i.e. the task has not specified any MPU\r
- * region, the else part ensures that all the configurable MPU\r
- * regions are invalidated. */\r
- if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )\r
- {\r
- /* Translate the generic region definition contained in xRegions\r
- * into the ARMv8 specific MPU settings that are then stored in\r
- * xMPUSettings. */\r
- ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;\r
- ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;\r
- ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\r
-\r
- /* Start address. */\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |\r
- ( portMPU_REGION_NON_SHAREABLE );\r
-\r
- /* RO/RW. */\r
- if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )\r
- {\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );\r
- }\r
- else\r
- {\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );\r
- }\r
-\r
- /* XN. */\r
- if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )\r
- {\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );\r
- }\r
-\r
- /* End Address. */\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |\r
- ( portMPU_RLAR_REGION_ENABLE );\r
-\r
- /* Normal memory/ Device memory. */\r
- if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )\r
- {\r
- /* Attr1 in MAIR0 is configured as device memory. */\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;\r
- }\r
- else\r
- {\r
- /* Attr1 in MAIR0 is configured as normal memory. */\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;\r
- }\r
- }\r
- else\r
- {\r
- /* Invalidate the region. */\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;\r
- }\r
-\r
- lIndex++;\r
- }\r
- }\r
+ void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )\r
+ {\r
+ uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;\r
+ int32_t lIndex = 0;\r
+\r
+ /* Setup MAIR0. */\r
+ xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
+ xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
+\r
+ /* This function is called automatically when the task is created - in\r
+ * which case the stack region parameters will be valid. At all other\r
+ * times the stack parameters will not be valid and it is assumed that\r
+ * the stack region has already been configured. */\r
+ if( ulStackDepth > 0 )\r
+ {\r
+ /* Define the region that allows access to the stack. */\r
+ ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;\r
+ ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;\r
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\r
+\r
+ xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_WRITE ) |\r
+ ( portMPU_REGION_EXECUTE_NEVER );\r
+\r
+ xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+ }\r
+\r
+ /* User supplied configurable regions. */\r
+ for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )\r
+ {\r
+ /* If xRegions is NULL i.e. the task has not specified any MPU\r
+ * region, the else part ensures that all the configurable MPU\r
+ * regions are invalidated. */\r
+ if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )\r
+ {\r
+ /* Translate the generic region definition contained in xRegions\r
+ * into the ARMv8 specific MPU settings that are then stored in\r
+ * xMPUSettings. */\r
+ ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;\r
+ ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;\r
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\r
+\r
+ /* Start address. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |\r
+ ( portMPU_REGION_NON_SHAREABLE );\r
+\r
+ /* RO/RW. */\r
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )\r
+ {\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );\r
+ }\r
+ else\r
+ {\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );\r
+ }\r
+\r
+ /* XN. */\r
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )\r
+ {\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );\r
+ }\r
+\r
+ /* End Address. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Normal memory/ Device memory. */\r
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )\r
+ {\r
+ /* Attr1 in MAIR0 is configured as device memory. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;\r
+ }\r
+ else\r
+ {\r
+ /* Attr1 in MAIR0 is configured as normal memory. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Invalidate the region. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;\r
+ }\r
+\r
+ lIndex++;\r
+ }\r
+ }\r
#endif /* configENABLE_MPU */\r
/*-----------------------------------------------------------*/\r
\r
void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
{\r
- __asm volatile\r
- (\r
- " .syntax unified \n"\r
- " \n"\r
- " ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
- " ldr r1, [r2] \n" /* Read pxCurrentTCB. */\r
- " ldr r0, [r1] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
- " \n"\r
- #if( configENABLE_MPU == 1 )\r
- " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
- " ldr r3, [r1] \n" /* r3 = *r1 i.e. r3 = MAIR0. */\r
- " ldr r2, xMAIR0Const2 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
- " str r3, [r2] \n" /* Program MAIR0. */\r
- " ldr r2, xRNRConst2 \n" /* r2 = 0xe000ed98 [Location of RNR]. */\r
- " movs r3, #4 \n" /* r3 = 4. */\r
- " str r3, [r2] \n" /* Program RNR = 4. */\r
- " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
- " ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */\r
- " ldmia r1!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */\r
- " stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
- #endif /* configENABLE_MPU */\r
- " \n"\r
- #if( configENABLE_MPU == 1 )\r
- " ldm r0!, {r1-r3} \n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */\r
- " msr psplim, r1 \n" /* Set this task's PSPLIM value. */\r
- " msr control, r2 \n" /* Set this task's CONTROL value. */\r
- " adds r0, #32 \n" /* Discard everything up to r0. */\r
- " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */\r
- " isb \n"\r
- " bx r3 \n" /* Finally, branch to EXC_RETURN. */\r
- #else /* configENABLE_MPU */\r
- " ldm r0!, {r1-r2} \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */\r
- " msr psplim, r1 \n" /* Set this task's PSPLIM value. */\r
- " movs r1, #2 \n" /* r1 = 2. */\r
- " msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */\r
- " adds r0, #32 \n" /* Discard everything up to r0. */\r
- " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */\r
- " isb \n"\r
- " bx r2 \n" /* Finally, branch to EXC_RETURN. */\r
- #endif /* configENABLE_MPU */\r
- " \n"\r
- " .align 4 \n"\r
- "pxCurrentTCBConst2: .word pxCurrentTCB \n"\r
- #if( configENABLE_MPU == 1 )\r
- "xMAIR0Const2: .word 0xe000edc0 \n"\r
- "xRNRConst2: .word 0xe000ed98 \n"\r
- "xRBARConst2: .word 0xe000ed9c \n"\r
- #endif /* configENABLE_MPU */\r
- );\r
+ __asm volatile\r
+ (\r
+ " .syntax unified \n"\r
+ " \n"\r
+ " ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */\r
+ " ldr r0, [r1] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
+ " ldr r3, [r1] \n" /* r3 = *r1 i.e. r3 = MAIR0. */\r
+ " ldr r2, xMAIR0Const2 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ " str r3, [r2] \n" /* Program MAIR0. */\r
+ " ldr r2, xRNRConst2 \n" /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ " movs r3, #4 \n" /* r3 = 4. */\r
+ " str r3, [r2] \n" /* Program RNR = 4. */\r
+ " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
+ " ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */\r
+ " ldmia r1!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */\r
+ " stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " ldm r0!, {r1-r3} \n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */\r
+ " msr psplim, r1 \n" /* Set this task's PSPLIM value. */\r
+ " msr control, r2 \n" /* Set this task's CONTROL value. */\r
+ " adds r0, #32 \n" /* Discard everything up to r0. */\r
+ " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */\r
+ " isb \n"\r
+ " bx r3 \n" /* Finally, branch to EXC_RETURN. */\r
+ #else /* configENABLE_MPU */\r
+ " ldm r0!, {r1-r2} \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */\r
+ " msr psplim, r1 \n" /* Set this task's PSPLIM value. */\r
+ " movs r1, #2 \n" /* r1 = 2. */\r
+ " msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */\r
+ " adds r0, #32 \n" /* Discard everything up to r0. */\r
+ " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */\r
+ " isb \n"\r
+ " bx r2 \n" /* Finally, branch to EXC_RETURN. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ " .align 4 \n"\r
+ "pxCurrentTCBConst2: .word pxCurrentTCB \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ "xMAIR0Const2: .word 0xe000edc0 \n"\r
+ "xRNRConst2: .word 0xe000ed98 \n"\r
+ "xRBARConst2: .word 0xe000ed9c \n"\r
+ #endif /* configENABLE_MPU */\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
\r
BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */\r
{\r
- __asm volatile\r
- (\r
- " mrs r0, control \n" /* r0 = CONTROL. */\r
- " tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\r
- " ite ne \n"\r
- " movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
- " moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\r
- " bx lr \n" /* Return. */\r
- " \n"\r
- " .align 4 \n"\r
- ::: "r0", "memory"\r
- );\r
+ __asm volatile\r
+ (\r
+ " mrs r0, control \n" /* r0 = CONTROL. */\r
+ " tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\r
+ " ite ne \n"\r
+ " movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
+ " moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\r
+ " bx lr \n" /* Return. */\r
+ " \n"\r
+ " .align 4 \n"\r
+ ::: "r0", "memory"\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
{\r
- __asm volatile\r
- (\r
- " mrs r0, control \n" /* Read the CONTROL register. */\r
- " bic r0, #1 \n" /* Clear the bit 0. */\r
- " msr control, r0 \n" /* Write back the new CONTROL value. */\r
- " bx lr \n" /* Return to the caller. */\r
- ::: "r0", "memory"\r
- );\r
+ __asm volatile\r
+ (\r
+ " mrs r0, control \n" /* Read the CONTROL register. */\r
+ " bic r0, #1 \n" /* Clear the bit 0. */\r
+ " msr control, r0 \n" /* Write back the new CONTROL value. */\r
+ " bx lr \n" /* Return to the caller. */\r
+ ::: "r0", "memory"\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vResetPrivilege( void ) /* __attribute__ (( naked )) */\r
{\r
- __asm volatile\r
- (\r
- " mrs r0, control \n" /* r0 = CONTROL. */\r
- " orr r0, #1 \n" /* r0 = r0 | 1. */\r
- " msr control, r0 \n" /* CONTROL = r0. */\r
- " bx lr \n" /* Return to the caller. */\r
- :::"r0", "memory"\r
- );\r
+ __asm volatile\r
+ (\r
+ " mrs r0, control \n" /* r0 = CONTROL. */\r
+ " orr r0, #1 \n" /* r0 = r0 | 1. */\r
+ " msr control, r0 \n" /* CONTROL = r0. */\r
+ " bx lr \n" /* Return to the caller. */\r
+ :::"r0", "memory"\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
{\r
- __asm volatile\r
- (\r
- " ldr r0, xVTORConst \n" /* Use the NVIC offset register to locate the stack. */\r
- " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */\r
- " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */\r
- " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */\r
- " cpsie i \n" /* Globally enable interrupts. */\r
- " cpsie f \n"\r
- " dsb \n"\r
- " isb \n"\r
- " svc %0 \n" /* System call to start the first task. */\r
- " nop \n"\r
- " \n"\r
- " .align 4 \n"\r
- "xVTORConst: .word 0xe000ed08 \n"\r
- :: "i" ( portSVC_START_SCHEDULER ) : "memory"\r
- );\r
+ __asm volatile\r
+ (\r
+ " ldr r0, xVTORConst \n" /* Use the NVIC offset register to locate the stack. */\r
+ " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */\r
+ " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */\r
+ " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */\r
+ " cpsie i \n" /* Globally enable interrupts. */\r
+ " cpsie f \n"\r
+ " dsb \n"\r
+ " isb \n"\r
+ " svc %0 \n" /* System call to start the first task. */\r
+ " nop \n"\r
+ " \n"\r
+ " .align 4 \n"\r
+ "xVTORConst: .word 0xe000ed08 \n"\r
+ :: "i" ( portSVC_START_SCHEDULER ) : "memory"\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
\r
uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
{\r
- __asm volatile\r
- (\r
- " mrs r0, PRIMASK \n"\r
- " cpsid i \n"\r
- " bx lr \n"\r
- ::: "memory"\r
- );\r
+ __asm volatile\r
+ (\r
+ " mrs r0, PRIMASK \n"\r
+ " cpsid i \n"\r
+ " bx lr \n"\r
+ ::: "memory"\r
+ );\r
\r
#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- /* To avoid compiler warnings. The return statement will never be reached,\r
- * but some compilers warn if it is not included, while others won't compile\r
- * if it is. */\r
- return 0;\r
+ /* To avoid compiler warnings. The return statement will never be reached,\r
+ * but some compilers warn if it is not included, while others won't compile\r
+ * if it is. */\r
+ return 0;\r
#endif\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
{\r
- __asm volatile\r
- (\r
- " msr PRIMASK, r0 \n"\r
- " bx lr \n"\r
- ::: "memory"\r
- );\r
+ __asm volatile\r
+ (\r
+ " msr PRIMASK, r0 \n"\r
+ " bx lr \n"\r
+ ::: "memory"\r
+ );\r
\r
#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- /* Just to avoid compiler warning. ulMask is used from the asm code but\r
- * the compiler can't see that. Some compilers generate warnings without\r
- * the following line, while others generate warnings if the line is\r
- * included. */\r
- ( void ) ulMask;\r
+ /* Just to avoid compiler warning. ulMask is used from the asm code but\r
+ * the compiler can't see that. Some compilers generate warnings without\r
+ * the following line, while others generate warnings if the line is\r
+ * included. */\r
+ ( void ) ulMask;\r
#endif\r
}\r
/*-----------------------------------------------------------*/\r
\r
void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
{\r
- __asm volatile\r
- (\r
- " .syntax unified \n"\r
- " \n"\r
- " mrs r0, psp \n" /* Read PSP in r0. */\r
- #if( configENABLE_FPU == 1 )\r
- " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
- " it eq \n"\r
- " vstmdbeq r0!, {s16-s31} \n" /* Store the FPU registers which are not saved automatically. */\r
- #endif /* configENABLE_FPU */\r
- #if( configENABLE_MPU == 1 )\r
- " mrs r1, psplim \n" /* r1 = PSPLIM. */\r
- " mrs r2, control \n" /* r2 = CONTROL. */\r
- " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */\r
- " stmdb r0!, {r1-r11} \n" /* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */\r
- #else /* configENABLE_MPU */\r
- " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
- " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */\r
- " stmdb r0!, {r2-r11} \n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */\r
- #endif /* configENABLE_MPU */\r
- " \n"\r
- " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
- " ldr r1, [r2] \n" /* Read pxCurrentTCB. */\r
- " str r0, [r1] \n" /* Save the new top of stack in TCB. */\r
- " \n"\r
- " cpsid i \n"\r
- " bl vTaskSwitchContext \n"\r
- " cpsie i \n"\r
- " \n"\r
- " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
- " ldr r1, [r2] \n" /* Read pxCurrentTCB. */\r
- " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */\r
- " \n"\r
- #if( configENABLE_MPU == 1 )\r
- " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
- " ldr r3, [r1] \n" /* r3 = *r1 i.e. r3 = MAIR0. */\r
- " ldr r2, xMAIR0Const \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
- " str r3, [r2] \n" /* Program MAIR0. */\r
- " ldr r2, xRNRConst \n" /* r2 = 0xe000ed98 [Location of RNR]. */\r
- " movs r3, #4 \n" /* r3 = 4. */\r
- " str r3, [r2] \n" /* Program RNR = 4. */\r
- " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
- " ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */\r
- " ldmia r1!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
- " stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
- #endif /* configENABLE_MPU */\r
- " \n"\r
- #if( configENABLE_MPU == 1 )\r
- " ldmia r0!, {r1-r11} \n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */\r
- #else /* configENABLE_MPU */\r
- " ldmia r0!, {r2-r11} \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */\r
- #endif /* configENABLE_MPU */\r
- " \n"\r
- #if( configENABLE_FPU == 1 )\r
- " tst r3, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
- " it eq \n"\r
- " vldmiaeq r0!, {s16-s31} \n" /* Restore the FPU registers which are not restored automatically. */\r
- #endif /* configENABLE_FPU */\r
- " \n"\r
- #if( configENABLE_MPU == 1 )\r
- " msr psplim, r1 \n" /* Restore the PSPLIM register value for the task. */\r
- " msr control, r2 \n" /* Restore the CONTROL register value for the task. */\r
- #else /* configENABLE_MPU */\r
- " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */\r
- #endif /* configENABLE_MPU */\r
- " msr psp, r0 \n" /* Remember the new top of stack for the task. */\r
- " bx r3 \n"\r
- " \n"\r
- " .align 4 \n"\r
- "pxCurrentTCBConst: .word pxCurrentTCB \n"\r
- "xMAIR0Const: .word 0xe000edc0 \n"\r
- "xRNRConst: .word 0xe000ed98 \n"\r
- "xRBARConst: .word 0xe000ed9c \n"\r
- );\r
+ __asm volatile\r
+ (\r
+ " .syntax unified \n"\r
+ " \n"\r
+ " mrs r0, psp \n" /* Read PSP in r0. */\r
+ #if( configENABLE_FPU == 1 )\r
+ " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
+ " it eq \n"\r
+ " vstmdbeq r0!, {s16-s31} \n" /* Store the FPU registers which are not saved automatically. */\r
+ #endif /* configENABLE_FPU */\r
+ #if( configENABLE_MPU == 1 )\r
+ " mrs r1, psplim \n" /* r1 = PSPLIM. */\r
+ " mrs r2, control \n" /* r2 = CONTROL. */\r
+ " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */\r
+ " stmdb r0!, {r1-r11} \n" /* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */\r
+ #else /* configENABLE_MPU */\r
+ " mrs r2, psplim \n" /* r2 = PSPLIM. */\r
+ " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */\r
+ " stmdb r0!, {r2-r11} \n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */\r
+ " str r0, [r1] \n" /* Save the new top of stack in TCB. */\r
+ " \n"\r
+ " cpsid i \n"\r
+ " bl vTaskSwitchContext \n"\r
+ " cpsie i \n"\r
+ " \n"\r
+ " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */\r
+ " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
+ " ldr r3, [r1] \n" /* r3 = *r1 i.e. r3 = MAIR0. */\r
+ " ldr r2, xMAIR0Const \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ " str r3, [r2] \n" /* Program MAIR0. */\r
+ " ldr r2, xRNRConst \n" /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ " movs r3, #4 \n" /* r3 = 4. */\r
+ " str r3, [r2] \n" /* Program RNR = 4. */\r
+ " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
+ " ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */\r
+ " ldmia r1!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
+ " stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " ldmia r0!, {r1-r11} \n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */\r
+ #else /* configENABLE_MPU */\r
+ " ldmia r0!, {r2-r11} \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */\r
+ #endif /* configENABLE_MPU */\r
+ " \n"\r
+ #if( configENABLE_FPU == 1 )\r
+ " tst r3, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
+ " it eq \n"\r
+ " vldmiaeq r0!, {s16-s31} \n" /* Restore the FPU registers which are not restored automatically. */\r
+ #endif /* configENABLE_FPU */\r
+ " \n"\r
+ #if( configENABLE_MPU == 1 )\r
+ " msr psplim, r1 \n" /* Restore the PSPLIM register value for the task. */\r
+ " msr control, r2 \n" /* Restore the CONTROL register value for the task. */\r
+ #else /* configENABLE_MPU */\r
+ " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */\r
+ #endif /* configENABLE_MPU */\r
+ " msr psp, r0 \n" /* Remember the new top of stack for the task. */\r
+ " bx r3 \n"\r
+ " \n"\r
+ " .align 4 \n"\r
+ "pxCurrentTCBConst: .word pxCurrentTCB \n"\r
+ "xMAIR0Const: .word 0xe000edc0 \n"\r
+ "xRNRConst: .word 0xe000ed98 \n"\r
+ "xRBARConst: .word 0xe000ed9c \n"\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
\r
void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
{\r
- __asm volatile\r
- (\r
- " tst lr, #4 \n"\r
- " ite eq \n"\r
- " mrseq r0, msp \n"\r
- " mrsne r0, psp \n"\r
- " ldr r1, svchandler_address_const \n"\r
- " bx r1 \n"\r
- " \n"\r
- " .align 4 \n"\r
- "svchandler_address_const: .word vPortSVCHandler_C \n"\r
- );\r
+ __asm volatile\r
+ (\r
+ " tst lr, #4 \n"\r
+ " ite eq \n"\r
+ " mrseq r0, msp \n"\r
+ " mrsne r0, psp \n"\r
+ " ldr r1, svchandler_address_const \n"\r
+ " bx r1 \n"\r
+ " \n"\r
+ " .align 4 \n"\r
+ "svchandler_address_const: .word vPortSVCHandler_C \n"\r
+ );\r
}\r
/*-----------------------------------------------------------*/\r
*------------------------------------------------------------------------------\r
*/\r
\r
+#ifndef configENABLE_FPU\r
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h.\r
+#endif /* configENABLE_FPU */\r
+\r
+#ifndef configENABLE_MPU\r
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h.\r
+#endif /* configENABLE_MPU */\r
+\r
+#ifndef configENABLE_TRUSTZONE\r
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.\r
+#endif /* configENABLE_TRUSTZONE */\r
+/*-----------------------------------------------------------*/\r
+\r
/**\r
* @brief Type definitions.\r
*/\r
-#define portCHAR char\r
-#define portFLOAT float\r
-#define portDOUBLE double\r
-#define portLONG long\r
-#define portSHORT short\r
-#define portSTACK_TYPE uint32_t\r
-#define portBASE_TYPE long\r
-\r
-typedef portSTACK_TYPE StackType_t;\r
-typedef long BaseType_t;\r
-typedef unsigned long UBaseType_t;\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT short\r
+#define portSTACK_TYPE uint32_t\r
+#define portBASE_TYPE long\r
+\r
+typedef portSTACK_TYPE StackType_t;\r
+typedef long BaseType_t;\r
+typedef unsigned long UBaseType_t;\r
\r
#if( configUSE_16_BIT_TICKS == 1 )\r
- typedef uint16_t TickType_t;\r
- #define portMAX_DELAY ( TickType_t ) 0xffff\r
+ typedef uint16_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffff\r
#else\r
- typedef uint32_t TickType_t;\r
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL\r
+ typedef uint32_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL\r
\r
- /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\r
- * not need to be guarded with a critical section. */\r
- #define portTICK_TYPE_IS_ATOMIC 1\r
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\r
+ * not need to be guarded with a critical section. */\r
+ #define portTICK_TYPE_IS_ATOMIC 1\r
#endif\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* Architecture specifics.\r
*/\r
-#define portSTACK_GROWTH ( -1 )\r
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
-#define portBYTE_ALIGNMENT 8\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
+#define portBYTE_ALIGNMENT 8\r
#define portNOP()\r
-#define portINLINE __inline\r
+#define portINLINE __inline\r
#ifndef portFORCE_INLINE\r
- #define portFORCE_INLINE inline __attribute__(( always_inline ))\r
+ #define portFORCE_INLINE inline __attribute__(( always_inline ))\r
#endif\r
-#define portHAS_STACK_OVERFLOW_CHECKING 1\r
+#define portHAS_STACK_OVERFLOW_CHECKING 1\r
/*-----------------------------------------------------------*/\r
\r
/**\r
extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );\r
- extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* PRIVILEGED_FUNCTION */;\r
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );\r
+ extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* PRIVILEGED_FUNCTION */;\r
#endif /* configENABLE_TRUSTZONE */\r
\r
#if( configENABLE_MPU == 1 )\r
- extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;\r
- extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;\r
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;\r
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;\r
#endif /* configENABLE_MPU */\r
/*-----------------------------------------------------------*/\r
\r
* @brief MPU specific constants.\r
*/\r
#if( configENABLE_MPU == 1 )\r
- #define portUSING_MPU_WRAPPERS 1\r
- #define portPRIVILEGE_BIT ( 0x80000000UL )\r
+ #define portUSING_MPU_WRAPPERS 1\r
+ #define portPRIVILEGE_BIT ( 0x80000000UL )\r
#else\r
- #define portPRIVILEGE_BIT ( 0x0UL )\r
+ #define portPRIVILEGE_BIT ( 0x0UL )\r
#endif /* configENABLE_MPU */\r
\r
\r
/* MPU regions. */\r
-#define portPRIVILEGED_FLASH_REGION ( 0UL )\r
-#define portUNPRIVILEGED_FLASH_REGION ( 1UL )\r
-#define portPRIVILEGED_RAM_REGION ( 2UL )\r
-#define portUNPRIVILEGED_DEVICE_REGION ( 3UL )\r
-#define portSTACK_REGION ( 4UL )\r
-#define portFIRST_CONFIGURABLE_REGION ( 5UL )\r
-#define portLAST_CONFIGURABLE_REGION ( 7UL )\r
-#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\r
-#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */\r
+#define portPRIVILEGED_FLASH_REGION ( 0UL )\r
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )\r
+#define portPRIVILEGED_RAM_REGION ( 2UL )\r
+#define portUNPRIVILEGED_DEVICE_REGION ( 3UL )\r
+#define portSTACK_REGION ( 4UL )\r
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )\r
+#define portLAST_CONFIGURABLE_REGION ( 7UL )\r
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\r
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */\r
\r
/* Devices Region. */\r
-#define portDEVICE_REGION_START_ADDRESS ( 0x50000000 )\r
-#define portDEVICE_REGION_END_ADDRESS ( 0x5FFFFFFF )\r
+#define portDEVICE_REGION_START_ADDRESS ( 0x50000000 )\r
+#define portDEVICE_REGION_END_ADDRESS ( 0x5FFFFFFF )\r
\r
/* Device memory attributes used in MPU_MAIR registers.\r
*\r
* 8-bit values encoded as follows:\r
* Bit[7:4] - 0000 - Device Memory\r
* Bit[3:2] - 00 --> Device-nGnRnE\r
- * 01 --> Device-nGnRE\r
- * 10 --> Device-nGRE\r
- * 11 --> Device-GRE\r
+ * 01 --> Device-nGnRE\r
+ * 10 --> Device-nGRE\r
+ * 11 --> Device-GRE\r
* Bit[1:0] - 00, Reserved.\r
*/\r
-#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */\r
-#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */\r
-#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */\r
-#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */\r
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */\r
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */\r
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */\r
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */\r
\r
/* Normal memory attributes used in MPU_MAIR registers. */\r
-#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */\r
-#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */\r
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */\r
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */\r
\r
/* Attributes used in MPU_RBAR registers. */\r
-#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )\r
-#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )\r
-#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )\r
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )\r
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )\r
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )\r
\r
-#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )\r
-#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )\r
-#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )\r
-#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )\r
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )\r
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )\r
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )\r
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )\r
\r
-#define portMPU_REGION_EXECUTE_NEVER ( 1UL )\r
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )\r
/*-----------------------------------------------------------*/\r
\r
/**\r
*/\r
typedef struct MPURegionSettings\r
{\r
- uint32_t ulRBAR; /**< RBAR for the region. */\r
- uint32_t ulRLAR; /**< RLAR for the region. */\r
+ uint32_t ulRBAR; /**< RBAR for the region. */\r
+ uint32_t ulRLAR; /**< RLAR for the region. */\r
} MPURegionSettings_t;\r
\r
/**\r
*/\r
typedef struct MPU_SETTINGS\r
{\r
- uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */\r
- MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */\r
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */\r
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */\r
} xMPU_SETTINGS;\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief SVC numbers.\r
*/\r
-#define portSVC_ALLOCATE_SECURE_CONTEXT 0\r
-#define portSVC_FREE_SECURE_CONTEXT 1\r
-#define portSVC_START_SCHEDULER 2\r
-#define portSVC_RAISE_PRIVILEGE 3\r
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0\r
+#define portSVC_FREE_SECURE_CONTEXT 1\r
+#define portSVC_START_SCHEDULER 2\r
+#define portSVC_RAISE_PRIVILEGE 3\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Scheduler utilities.\r
*/\r
-#define portYIELD() vPortYield()\r
-#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )\r
-#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )\r
-#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT\r
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
+#define portYIELD() vPortYield()\r
+#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )\r
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )\r
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT\r
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Critical section management.\r
*/\r
-#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()\r
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )\r
-#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )\r
-#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )\r
-#define portENTER_CRITICAL() vPortEnterCritical()\r
-#define portEXIT_CRITICAL() vPortExitCritical()\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )\r
+#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )\r
+#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )\r
+#define portENTER_CRITICAL() vPortEnterCritical()\r
+#define portEXIT_CRITICAL() vPortExitCritical()\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Task function macros as described on the FreeRTOS.org WEB site.\r
*/\r
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
/*-----------------------------------------------------------*/\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
- /**\r
- * @brief Allocate a secure context for the task.\r
- *\r
- * Tasks are not created with a secure context. Any task that is going to call\r
- * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a\r
- * secure context before it calls any secure function.\r
- *\r
- * @param[in] ulSecureStackSize The size of the secure stack to be allocated.\r
- */\r
- #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )\r
-\r
- /**\r
- * @brief Called when a task is deleted to delete the task's secure context,\r
- * if it has one.\r
- *\r
- * @param[in] pxTCB The TCB of the task being deleted.\r
- */\r
- #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )\r
+ /**\r
+ * @brief Allocate a secure context for the task.\r
+ *\r
+ * Tasks are not created with a secure context. Any task that is going to call\r
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a\r
+ * secure context before it calls any secure function.\r
+ *\r
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.\r
+ */\r
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )\r
+\r
+ /**\r
+ * @brief Called when a task is deleted to delete the task's secure context,\r
+ * if it has one.\r
+ *\r
+ * @param[in] pxTCB The TCB of the task being deleted.\r
+ */\r
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )\r
#else\r
- #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )\r
- #define portCLEAN_UP_TCB( pxTCB )\r
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )\r
+ #define portCLEAN_UP_TCB( pxTCB )\r
#endif /* configENABLE_TRUSTZONE */\r
/*-----------------------------------------------------------*/\r
\r
#if( configENABLE_MPU == 1 )\r
- /**\r
- * @brief Checks whether or not the processor is privileged.\r
- *\r
- * @return 1 if the processor is already privileged, 0 otherwise.\r
- */\r
- #define portIS_PRIVILEGED() xIsPrivileged()\r
-\r
- /**\r
- * @brief Raise an SVC request to raise privilege.\r
- *\r
- * The SVC handler checks that the SVC was raised from a system call and only\r
- * then it raises the privilege. If this is called from any other place,\r
- * the privilege is not raised.\r
- */\r
- #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );\r
-\r
- /**\r
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\r
- * register.\r
- */\r
- #define portRESET_PRIVILEGE() vResetPrivilege()\r
+ /**\r
+ * @brief Checks whether or not the processor is privileged.\r
+ *\r
+ * @return 1 if the processor is already privileged, 0 otherwise.\r
+ */\r
+ #define portIS_PRIVILEGED() xIsPrivileged()\r
+\r
+ /**\r
+ * @brief Raise an SVC request to raise privilege.\r
+ *\r
+ * The SVC handler checks that the SVC was raised from a system call and only\r
+ * then it raises the privilege. If this is called from any other place,\r
+ * the privilege is not raised.\r
+ */\r
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );\r
+\r
+ /**\r
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\r
+ * register.\r
+ */\r
+ #define portRESET_PRIVILEGE() vResetPrivilege()\r
#else\r
- #define portIS_PRIVILEGED()\r
- #define portRAISE_PRIVILEGE()\r
- #define portRESET_PRIVILEGE()\r
+ #define portIS_PRIVILEGED()\r
+ #define portRAISE_PRIVILEGE()\r
+ #define portRESET_PRIVILEGE()\r
#endif /* configENABLE_MPU */\r
/*-----------------------------------------------------------*/\r
\r
#include "portasm.h"\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
- /* Secure components includes. */\r
- #include "secure_context.h"\r
- #include "secure_init.h"\r
+ /* Secure components includes. */\r
+ #include "secure_context.h"\r
+ #include "secure_init.h"\r
#endif /* configENABLE_TRUSTZONE */\r
\r
#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
+/**\r
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only\r
+ * i.e. the processor boots as secure and never jumps to the non-secure side.\r
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS\r
+ * on the secure side. The following are the valid configuration seetings:\r
+ *\r
+ * 1. Run FreeRTOS on the Secure Side:\r
+ * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0\r
+ *\r
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:\r
+ * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1\r
+ *\r
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:\r
+ * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0\r
+ */\r
+#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )\r
+ #error Trust Zone needs to be disabled in order to run FreeRTOS on the Secure Side.\r
+#endif\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Constants required to manipulate the NVIC.\r
*/\r
-#define portNVIC_SYSTICK_CTRL ( ( volatile uint32_t * ) 0xe000e010 )\r
-#define portNVIC_SYSTICK_LOAD ( ( volatile uint32_t * ) 0xe000e014 )\r
-#define portNVIC_SYSTICK_CURRENT_VALUE ( ( volatile uint32_t * ) 0xe000e018 )\r
-#define portNVIC_INT_CTRL ( ( volatile uint32_t * ) 0xe000ed04 )\r
-#define portNVIC_SYSPRI2 ( ( volatile uint32_t * ) 0xe000ed20 )\r
-#define portNVIC_SYSTICK_CLK ( 0x00000004 )\r
-#define portNVIC_SYSTICK_INT ( 0x00000002 )\r
-#define portNVIC_SYSTICK_ENABLE ( 0x00000001 )\r
-#define portNVIC_PENDSVSET ( 0x10000000 )\r
-#define portMIN_INTERRUPT_PRIORITY ( 255UL )\r
-#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )\r
-#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )\r
+#define portNVIC_SYSTICK_CTRL ( ( volatile uint32_t * ) 0xe000e010 )\r
+#define portNVIC_SYSTICK_LOAD ( ( volatile uint32_t * ) 0xe000e014 )\r
+#define portNVIC_SYSTICK_CURRENT_VALUE ( ( volatile uint32_t * ) 0xe000e018 )\r
+#define portNVIC_INT_CTRL ( ( volatile uint32_t * ) 0xe000ed04 )\r
+#define portNVIC_SYSPRI2 ( ( volatile uint32_t * ) 0xe000ed20 )\r
+#define portNVIC_SYSTICK_CLK ( 0x00000004 )\r
+#define portNVIC_SYSTICK_INT ( 0x00000002 )\r
+#define portNVIC_SYSTICK_ENABLE ( 0x00000001 )\r
+#define portNVIC_PENDSVSET ( 0x10000000 )\r
+#define portMIN_INTERRUPT_PRIORITY ( 255UL )\r
+#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )\r
+#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Constants required to manipulate the SCB.\r
*/\r
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( * ( volatile uint32_t * ) 0xe000ed24 )\r
-#define portSCB_MEM_FAULT_ENABLE ( 1UL << 16UL )\r
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( * ( volatile uint32_t * ) 0xe000ed24 )\r
+#define portSCB_MEM_FAULT_ENABLE ( 1UL << 16UL )\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Constants required to manipulate the FPU.\r
*/\r
-#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */\r
-#define portCPACR_CP10_VALUE ( 3UL )\r
-#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE\r
-#define portCPACR_CP10_POS ( 20UL )\r
-#define portCPACR_CP11_POS ( 22UL )\r
-\r
-#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */\r
-#define portFPCCR_ASPEN_POS ( 31UL )\r
-#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS )\r
-#define portFPCCR_LSPEN_POS ( 30UL )\r
-#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS )\r
+#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */\r
+#define portCPACR_CP10_VALUE ( 3UL )\r
+#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE\r
+#define portCPACR_CP10_POS ( 20UL )\r
+#define portCPACR_CP11_POS ( 22UL )\r
+\r
+#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */\r
+#define portFPCCR_ASPEN_POS ( 31UL )\r
+#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS )\r
+#define portFPCCR_LSPEN_POS ( 30UL )\r
+#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS )\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Constants required to manipulate the MPU.\r
*/\r
-#define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )\r
-#define portMPU_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )\r
-#define portMPU_RNR_REG ( * ( ( volatile uint32_t * ) 0xe000ed98 ) )\r
+#define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )\r
+#define portMPU_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )\r
+#define portMPU_RNR_REG ( * ( ( volatile uint32_t * ) 0xe000ed98 ) )\r
\r
-#define portMPU_RBAR_REG ( * ( ( volatile uint32_t * ) 0xe000ed9c ) )\r
-#define portMPU_RLAR_REG ( * ( ( volatile uint32_t * ) 0xe000eda0 ) )\r
+#define portMPU_RBAR_REG ( * ( ( volatile uint32_t * ) 0xe000ed9c ) )\r
+#define portMPU_RLAR_REG ( * ( ( volatile uint32_t * ) 0xe000eda0 ) )\r
\r
-#define portMPU_RBAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda4 ) )\r
-#define portMPU_RLAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda8 ) )\r
+#define portMPU_RBAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda4 ) )\r
+#define portMPU_RLAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda8 ) )\r
\r
-#define portMPU_RBAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edac ) )\r
-#define portMPU_RLAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edb0 ) )\r
+#define portMPU_RBAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edac ) )\r
+#define portMPU_RLAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edb0 ) )\r
\r
-#define portMPU_RBAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb4 ) )\r
-#define portMPU_RLAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb8 ) )\r
+#define portMPU_RBAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb4 ) )\r
+#define portMPU_RLAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb8 ) )\r
\r
-#define portMPU_MAIR0_REG ( * ( ( volatile uint32_t * ) 0xe000edc0 ) )\r
-#define portMPU_MAIR1_REG ( * ( ( volatile uint32_t * ) 0xe000edc4 ) )\r
+#define portMPU_MAIR0_REG ( * ( ( volatile uint32_t * ) 0xe000edc0 ) )\r
+#define portMPU_MAIR1_REG ( * ( ( volatile uint32_t * ) 0xe000edc4 ) )\r
\r
-#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
-#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
+#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
+#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
\r
-#define portMPU_MAIR_ATTR0_POS ( 0UL )\r
-#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )\r
+#define portMPU_MAIR_ATTR0_POS ( 0UL )\r
+#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )\r
\r
-#define portMPU_MAIR_ATTR1_POS ( 8UL )\r
-#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )\r
+#define portMPU_MAIR_ATTR1_POS ( 8UL )\r
+#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )\r
\r
-#define portMPU_MAIR_ATTR2_POS ( 16UL )\r
-#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )\r
+#define portMPU_MAIR_ATTR2_POS ( 16UL )\r
+#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )\r
\r
-#define portMPU_MAIR_ATTR3_POS ( 24UL )\r
-#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )\r
+#define portMPU_MAIR_ATTR3_POS ( 24UL )\r
+#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )\r
\r
-#define portMPU_MAIR_ATTR4_POS ( 0UL )\r
-#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )\r
+#define portMPU_MAIR_ATTR4_POS ( 0UL )\r
+#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )\r
\r
-#define portMPU_MAIR_ATTR5_POS ( 8UL )\r
-#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )\r
+#define portMPU_MAIR_ATTR5_POS ( 8UL )\r
+#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )\r
\r
-#define portMPU_MAIR_ATTR6_POS ( 16UL )\r
-#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )\r
+#define portMPU_MAIR_ATTR6_POS ( 16UL )\r
+#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )\r
\r
-#define portMPU_MAIR_ATTR7_POS ( 24UL )\r
-#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )\r
+#define portMPU_MAIR_ATTR7_POS ( 24UL )\r
+#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )\r
\r
-#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )\r
-#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )\r
-#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )\r
-#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )\r
-#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )\r
-#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )\r
-#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )\r
-#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )\r
\r
-#define portMPU_RLAR_REGION_ENABLE ( 1UL )\r
+#define portMPU_RLAR_REGION_ENABLE ( 1UL )\r
\r
/* Enable privileged access to unmapped region. */\r
-#define portMPU_PRIV_BACKGROUND_ENABLE ( 1UL << 2UL )\r
+#define portMPU_PRIV_BACKGROUND_ENABLE ( 1UL << 2UL )\r
\r
/* Enable MPU. */\r
-#define portMPU_ENABLE ( 1UL << 0UL )\r
+#define portMPU_ENABLE ( 1UL << 0UL )\r
\r
/* Expected value of the portMPU_TYPE register. */\r
-#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */\r
+#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Constants required to set up the initial stack.\r
*/\r
-#define portINITIAL_XPSR ( 0x01000000 )\r
-\r
-/**\r
- * @brief Initial EXC_RETURN value.\r
- *\r
- * FF FF FF BC\r
- * 1111 1111 1111 1111 1111 1111 1011 1100\r
- *\r
- * Bit[6] - 0 --> The exception was taken from the Non-Secure state.\r
- * Bit[5] - 1 --> Do not skip stacking of additional state context.\r
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\r
- * Bit[3] - 1 --> Return to the Thread mode.\r
- * Bit[2] - 1 --> Restore registers from the process stack.\r
- * Bit[1] - 0 --> Reserved, 0.\r
- * Bit[0] - 0 --> The exception was taken to the Non-Secure state.\r
- */\r
-#define portINITIAL_EXC_RETURN ( 0xffffffbc )\r
+#define portINITIAL_XPSR ( 0x01000000 )\r
+\r
+#if( configRUN_FREERTOS_SECURE_ONLY == 1 )\r
+ /**\r
+ * @brief Initial EXC_RETURN value.\r
+ *\r
+ * FF FF FF FD\r
+ * 1111 1111 1111 1111 1111 1111 1111 1101\r
+ *\r
+ * Bit[6] - 1 --> The exception was taken from the Secure state.\r
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.\r
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\r
+ * Bit[3] - 1 --> Return to the Thread mode.\r
+ * Bit[2] - 1 --> Restore registers from the process stack.\r
+ * Bit[1] - 0 --> Reserved, 0.\r
+ * Bit[0] - 1 --> The exception was taken to the Secure state.\r
+ */\r
+ #define portINITIAL_EXC_RETURN ( 0xfffffffd )\r
+#else\r
+ /**\r
+ * @brief Initial EXC_RETURN value.\r
+ *\r
+ * FF FF FF BC\r
+ * 1111 1111 1111 1111 1111 1111 1011 1100\r
+ *\r
+ * Bit[6] - 0 --> The exception was taken from the Non-Secure state.\r
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.\r
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\r
+ * Bit[3] - 1 --> Return to the Thread mode.\r
+ * Bit[2] - 1 --> Restore registers from the process stack.\r
+ * Bit[1] - 0 --> Reserved, 0.\r
+ * Bit[0] - 0 --> The exception was taken to the Non-Secure state.\r
+ */\r
+ #define portINITIAL_EXC_RETURN ( 0xffffffbc )\r
+#endif /* configRUN_FREERTOS_SECURE_ONLY */\r
\r
/**\r
* @brief CONTROL register privileged bit mask.\r
* Bit[0] = 0 ==> The task is privileged.\r
* Bit[0] = 1 ==> The task is not privileged.\r
*/\r
-#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL )\r
+#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL )\r
\r
/**\r
* @brief Initial CONTROL register values.\r
*/\r
-#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 )\r
-#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 )\r
+#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 )\r
+#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 )\r
\r
/**\r
* @brief Let the user override the pre-loading of the initial LR with the\r
* in the debugger.\r
*/\r
#ifdef configTASK_RETURN_ADDRESS\r
- #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS\r
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS\r
#else\r
- #define portTASK_RETURN_ADDRESS prvTaskExitError\r
+ #define portTASK_RETURN_ADDRESS prvTaskExitError\r
#endif\r
\r
/**\r
* @brief If portPRELOAD_REGISTERS then registers will be given an initial value\r
* when a task is created. This helps in debugging at the cost of code size.\r
*/\r
-#define portPRELOAD_REGISTERS 1\r
+#define portPRELOAD_REGISTERS 1\r
\r
/**\r
* @brief A task is created without a secure context, and must call\r
* portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes\r
* any secure calls.\r
*/\r
-#define portNO_SECURE_CONTEXT 0\r
+#define portNO_SECURE_CONTEXT 0\r
/*-----------------------------------------------------------*/\r
\r
/**\r
static void prvTaskExitError( void );\r
\r
#if( configENABLE_MPU == 1 )\r
- /**\r
- * @brief Setup the Memory Protection Unit (MPU).\r
- */\r
- static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\r
+ /**\r
+ * @brief Setup the Memory Protection Unit (MPU).\r
+ */\r
+ static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\r
#endif /* configENABLE_MPU */\r
\r
#if( configENABLE_FPU == 1 )\r
- /**\r
- * @brief Setup the Floating Point Unit (FPU).\r
- */\r
- static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\r
+ /**\r
+ * @brief Setup the Floating Point Unit (FPU).\r
+ */\r
+ static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\r
#endif /* configENABLE_FPU */\r
\r
/**\r
static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
- /**\r
- * @brief Saved as part of the task context to indicate which context the\r
- * task is using on the secure side.\r
- */\r
- volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\r
+ /**\r
+ * @brief Saved as part of the task context to indicate which context the\r
+ * task is using on the secure side.\r
+ */\r
+ volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\r
#endif /* configENABLE_TRUSTZONE */\r
/*-----------------------------------------------------------*/\r
\r
static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\r
{\r
- /* Stop and reset the SysTick. */\r
- *( portNVIC_SYSTICK_CTRL ) = 0UL;\r
- *( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;\r
+ /* Stop and reset the SysTick. */\r
+ *( portNVIC_SYSTICK_CTRL ) = 0UL;\r
+ *( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;\r
\r
- /* Configure SysTick to interrupt at the requested rate. */\r
- *( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
- *( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
+ /* Configure SysTick to interrupt at the requested rate. */\r
+ *( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
+ *( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
}\r
/*-----------------------------------------------------------*/\r
\r
{\r
volatile uint32_t ulDummy = 0UL;\r
\r
- /* A function that implements a task must not exit or attempt to return to\r
- * its caller as there is nothing to return to. If a task wants to exit it\r
- * should instead call vTaskDelete( NULL ). Artificially force an assert()\r
- * to be triggered if configASSERT() is defined, then stop here so\r
- * application writers can catch the error. */\r
- configASSERT( ulCriticalNesting == ~0UL );\r
- portDISABLE_INTERRUPTS();\r
-\r
- while( ulDummy == 0 )\r
- {\r
- /* This file calls prvTaskExitError() after the scheduler has been\r
- * started to remove a compiler warning about the function being\r
- * defined but never called. ulDummy is used purely to quieten other\r
- * warnings about code appearing after this function is called - making\r
- * ulDummy volatile makes the compiler think the function could return\r
- * and therefore not output an 'unreachable code' warning for code that\r
- * appears after it. */\r
- }\r
+ /* A function that implements a task must not exit or attempt to return to\r
+ * its caller as there is nothing to return to. If a task wants to exit it\r
+ * should instead call vTaskDelete( NULL ). Artificially force an assert()\r
+ * to be triggered if configASSERT() is defined, then stop here so\r
+ * application writers can catch the error. */\r
+ configASSERT( ulCriticalNesting == ~0UL );\r
+ portDISABLE_INTERRUPTS();\r
+\r
+ while( ulDummy == 0 )\r
+ {\r
+ /* This file calls prvTaskExitError() after the scheduler has been\r
+ * started to remove a compiler warning about the function being\r
+ * defined but never called. ulDummy is used purely to quieten other\r
+ * warnings about code appearing after this function is called - making\r
+ * ulDummy volatile makes the compiler think the function could return\r
+ * and therefore not output an 'unreachable code' warning for code that\r
+ * appears after it. */\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
\r
#if( configENABLE_MPU == 1 )\r
- static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */\r
- {\r
- #if defined( __ARMCC_VERSION )\r
- /* Declaration when these variable are defined in code instead of being\r
- * exported from linker scripts. */\r
- extern uint32_t * __privileged_functions_start__;\r
- extern uint32_t * __privileged_functions_end__;\r
- extern uint32_t * __syscalls_flash_start__;\r
- extern uint32_t * __unprivileged_flash_end__;\r
- extern uint32_t * __privileged_sram_start__;\r
- extern uint32_t * __privileged_sram_end__;\r
- #else\r
- /* Declaration when these variable are exported from linker scripts. */\r
- extern uint32_t __privileged_functions_start__[];\r
- extern uint32_t __privileged_functions_end__[];\r
- extern uint32_t __syscalls_flash_start__[];\r
- extern uint32_t __unprivileged_flash_end__[];\r
- extern uint32_t __privileged_sram_start__[];\r
- extern uint32_t __privileged_sram_end__[];\r
- #endif /* defined( __ARMCC_VERSION ) */\r
-\r
- /* Check that the MPU is present. */\r
- if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\r
- {\r
- /* MAIR0 - Index 0. */\r
- portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
- /* MAIR0 - Index 1. */\r
- portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
-\r
- /* Setup privileged flash as Read Only so that privileged tasks can\r
- * read it but not modify. */\r
- portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;\r
- portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
- ( portMPU_REGION_NON_SHAREABLE ) |\r
- ( portMPU_REGION_PRIVILEGED_READ_ONLY );\r
- portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
- ( portMPU_RLAR_ATTR_INDEX0 ) |\r
- ( portMPU_RLAR_REGION_ENABLE );\r
-\r
- /* Setup unprivileged flash and system calls flash as Read Only by\r
- * both privileged and unprivileged tasks. All tasks can read it but\r
- * no-one can modify. */\r
- portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;\r
- portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
- ( portMPU_REGION_NON_SHAREABLE ) |\r
- ( portMPU_REGION_READ_ONLY );\r
- portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
- ( portMPU_RLAR_ATTR_INDEX0 ) |\r
- ( portMPU_RLAR_REGION_ENABLE );\r
-\r
- /* Setup RAM containing kernel data for privileged access only. */\r
- portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;\r
- portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
- ( portMPU_REGION_NON_SHAREABLE ) |\r
- ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
- ( portMPU_REGION_EXECUTE_NEVER );\r
- portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
- ( portMPU_RLAR_ATTR_INDEX0 ) |\r
- ( portMPU_RLAR_REGION_ENABLE );\r
-\r
- /* By default allow everything to access the general peripherals.\r
- * The system peripherals and registers are protected. */\r
- portMPU_RNR_REG = portUNPRIVILEGED_DEVICE_REGION;\r
- portMPU_RBAR_REG = ( ( ( uint32_t ) portDEVICE_REGION_START_ADDRESS ) & portMPU_RBAR_ADDRESS_MASK ) |\r
- ( portMPU_REGION_NON_SHAREABLE ) |\r
- ( portMPU_REGION_READ_WRITE ) |\r
- ( portMPU_REGION_EXECUTE_NEVER );\r
- portMPU_RLAR_REG = ( ( ( uint32_t ) portDEVICE_REGION_END_ADDRESS ) & portMPU_RLAR_ADDRESS_MASK ) |\r
- ( portMPU_RLAR_ATTR_INDEX1 ) |\r
- ( portMPU_RLAR_REGION_ENABLE );\r
-\r
- /* Enable mem fault. */\r
- portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;\r
-\r
- /* Enable MPU with privileged background access i.e. unmapped\r
- * regions have privileged access. */\r
- portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );\r
- }\r
- }\r
+ static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */\r
+ {\r
+ #if defined( __ARMCC_VERSION )\r
+ /* Declaration when these variable are defined in code instead of being\r
+ * exported from linker scripts. */\r
+ extern uint32_t * __privileged_functions_start__;\r
+ extern uint32_t * __privileged_functions_end__;\r
+ extern uint32_t * __syscalls_flash_start__;\r
+ extern uint32_t * __unprivileged_flash_end__;\r
+ extern uint32_t * __privileged_sram_start__;\r
+ extern uint32_t * __privileged_sram_end__;\r
+ #else\r
+ /* Declaration when these variable are exported from linker scripts. */\r
+ extern uint32_t __privileged_functions_start__[];\r
+ extern uint32_t __privileged_functions_end__[];\r
+ extern uint32_t __syscalls_flash_start__[];\r
+ extern uint32_t __unprivileged_flash_end__[];\r
+ extern uint32_t __privileged_sram_start__[];\r
+ extern uint32_t __privileged_sram_end__[];\r
+ #endif /* defined( __ARMCC_VERSION ) */\r
+\r
+ /* Check that the MPU is present. */\r
+ if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\r
+ {\r
+ /* MAIR0 - Index 0. */\r
+ portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
+ /* MAIR0 - Index 1. */\r
+ portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
+\r
+ /* Setup privileged flash as Read Only so that privileged tasks can\r
+ * read it but not modify. */\r
+ portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_PRIVILEGED_READ_ONLY );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Setup unprivileged flash and system calls flash as Read Only by\r
+ * both privileged and unprivileged tasks. All tasks can read it but\r
+ * no-one can modify. */\r
+ portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_ONLY );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Setup RAM containing kernel data for privileged access only. */\r
+ portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
+ ( portMPU_REGION_EXECUTE_NEVER );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* By default allow everything to access the general peripherals.\r
+ * The system peripherals and registers are protected. */\r
+ portMPU_RNR_REG = portUNPRIVILEGED_DEVICE_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) portDEVICE_REGION_START_ADDRESS ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_WRITE ) |\r
+ ( portMPU_REGION_EXECUTE_NEVER );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) portDEVICE_REGION_END_ADDRESS ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX1 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Enable mem fault. */\r
+ portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;\r
+\r
+ /* Enable MPU with privileged background access i.e. unmapped\r
+ * regions have privileged access. */\r
+ portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );\r
+ }\r
+ }\r
#endif /* configENABLE_MPU */\r
/*-----------------------------------------------------------*/\r
\r
#if( configENABLE_FPU == 1 )\r
- static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */\r
- {\r
- #if( configENABLE_TRUSTZONE == 1 )\r
- {\r
- /* Enable non-secure access to the FPU. */\r
- SecureInit_EnableNSFPUAccess();\r
- }\r
- #endif /* configENABLE_TRUSTZONE */\r
-\r
- /* CP10 = 11 ==> Full access to FPU i.e. both privileged and\r
- * unprivileged code should be able to access FPU. CP11 should be\r
- * programmed to the same value as CP10. */\r
- *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |\r
- ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )\r
- );\r
-\r
- /* ASPEN = 1 ==> Hardware should automatically preserve floating point\r
- * context on exception entry and restore on exception return.\r
- * LSPEN = 1 ==> Enable lazy context save of FP state. */\r
- *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );\r
- }\r
+ static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */\r
+ {\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ /* Enable non-secure access to the FPU. */\r
+ SecureInit_EnableNSFPUAccess();\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+\r
+ /* CP10 = 11 ==> Full access to FPU i.e. both privileged and\r
+ * unprivileged code should be able to access FPU. CP11 should be\r
+ * programmed to the same value as CP10. */\r
+ *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |\r
+ ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )\r
+ );\r
+\r
+ /* ASPEN = 1 ==> Hardware should automatically preserve floating point\r
+ * context on exception entry and restore on exception return.\r
+ * LSPEN = 1 ==> Enable lazy context save of FP state. */\r
+ *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );\r
+ }\r
#endif /* configENABLE_FPU */\r
/*-----------------------------------------------------------*/\r
\r
void vPortYield( void ) /* PRIVILEGED_FUNCTION */\r
{\r
- /* Set a PendSV to request a context switch. */\r
- *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
+ /* Set a PendSV to request a context switch. */\r
+ *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
\r
- /* Barriers are normally not required but do ensure the code is\r
- * completely within the specified behaviour for the architecture. */\r
- __asm volatile( "dsb" ::: "memory" );\r
- __asm volatile( "isb" );\r
+ /* Barriers are normally not required but do ensure the code is\r
+ * completely within the specified behaviour for the architecture. */\r
+ __asm volatile( "dsb" ::: "memory" );\r
+ __asm volatile( "isb" );\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */\r
{\r
- portDISABLE_INTERRUPTS();\r
- ulCriticalNesting++;\r
+ portDISABLE_INTERRUPTS();\r
+ ulCriticalNesting++;\r
\r
- /* Barriers are normally not required but do ensure the code is\r
- * completely within the specified behaviour for the architecture. */\r
- __asm volatile( "dsb" ::: "memory" );\r
- __asm volatile( "isb" );\r
+ /* Barriers are normally not required but do ensure the code is\r
+ * completely within the specified behaviour for the architecture. */\r
+ __asm volatile( "dsb" ::: "memory" );\r
+ __asm volatile( "isb" );\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */\r
{\r
- configASSERT( ulCriticalNesting );\r
- ulCriticalNesting--;\r
+ configASSERT( ulCriticalNesting );\r
+ ulCriticalNesting--;\r
\r
- if( ulCriticalNesting == 0 )\r
- {\r
- portENABLE_INTERRUPTS();\r
- }\r
+ if( ulCriticalNesting == 0 )\r
+ {\r
+ portENABLE_INTERRUPTS();\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
\r
{\r
uint32_t ulPreviousMask;\r
\r
- ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();\r
- {\r
- /* Increment the RTOS tick. */\r
- if( xTaskIncrementTick() != pdFALSE )\r
- {\r
- /* Pend a context switch. */\r
- *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
- }\r
- }\r
- portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );\r
+ ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();\r
+ {\r
+ /* Increment the RTOS tick. */\r
+ if( xTaskIncrementTick() != pdFALSE )\r
+ {\r
+ /* Pend a context switch. */\r
+ *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
+ }\r
+ }\r
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION */\r
{\r
#if( configENABLE_MPU == 1 )\r
- #if defined( __ARMCC_VERSION )\r
- /* Declaration when these variable are defined in code instead of being\r
- * exported from linker scripts. */\r
- extern uint32_t * __syscalls_flash_start__;\r
- extern uint32_t * __syscalls_flash_end__;\r
- #else\r
- /* Declaration when these variable are exported from linker scripts. */\r
- extern uint32_t __syscalls_flash_start__[];\r
- extern uint32_t __syscalls_flash_end__[];\r
- #endif /* defined( __ARMCC_VERSION ) */\r
+ #if defined( __ARMCC_VERSION )\r
+ /* Declaration when these variable are defined in code instead of being\r
+ * exported from linker scripts. */\r
+ extern uint32_t * __syscalls_flash_start__;\r
+ extern uint32_t * __syscalls_flash_end__;\r
+ #else\r
+ /* Declaration when these variable are exported from linker scripts. */\r
+ extern uint32_t __syscalls_flash_start__[];\r
+ extern uint32_t __syscalls_flash_end__[];\r
+ #endif /* defined( __ARMCC_VERSION ) */\r
#endif /* configENABLE_MPU */\r
\r
uint32_t ulPC;\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
- uint32_t ulR0;\r
- #if( configENABLE_MPU == 1 )\r
- uint32_t ulControl, ulIsTaskPrivileged;\r
- #endif /* configENABLE_MPU */\r
+ uint32_t ulR0;\r
+ #if( configENABLE_MPU == 1 )\r
+ uint32_t ulControl, ulIsTaskPrivileged;\r
+ #endif /* configENABLE_MPU */\r
#endif /* configENABLE_TRUSTZONE */\r
uint8_t ucSVCNumber;\r
\r
- /* Register are stored on the stack in the following order - R0, R1, R2, R3,\r
- * R12, LR, PC, xPSR. */\r
- ulPC = pulCallerStackAddress[ 6 ];\r
- ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];\r
-\r
- switch( ucSVCNumber )\r
- {\r
- #if( configENABLE_TRUSTZONE == 1 )\r
- case portSVC_ALLOCATE_SECURE_CONTEXT:\r
- {\r
- /* R0 contains the stack size passed as parameter to the\r
- * vPortAllocateSecureContext function. */\r
- ulR0 = pulCallerStackAddress[ 0 ];\r
-\r
- #if( configENABLE_MPU == 1 )\r
- {\r
- /* Read the CONTROL register value. */\r
- __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );\r
-\r
- /* The task that raised the SVC is privileged if Bit[0]\r
- * in the CONTROL register is 0. */\r
- ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );\r
-\r
- /* Allocate and load a context for the secure task. */\r
- xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );\r
- }\r
- #else\r
- {\r
- /* Allocate and load a context for the secure task. */\r
- xSecureContext = SecureContext_AllocateContext( ulR0 );\r
- }\r
- #endif /* configENABLE_MPU */\r
-\r
- configASSERT( xSecureContext != NULL );\r
- SecureContext_LoadContext( xSecureContext );\r
- }\r
- break;\r
-\r
- case portSVC_FREE_SECURE_CONTEXT:\r
- {\r
- /* R0 contains the secure context handle to be freed. */\r
- ulR0 = pulCallerStackAddress[ 0 ];\r
-\r
- /* Free the secure context. */\r
- SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );\r
- }\r
- break;\r
- #endif /* configENABLE_TRUSTZONE */\r
-\r
- case portSVC_START_SCHEDULER:\r
- {\r
- #if( configENABLE_TRUSTZONE == 1 )\r
- {\r
- /* De-prioritize the non-secure exceptions so that the\r
- * non-secure pendSV runs at the lowest priority. */\r
- SecureInit_DePrioritizeNSExceptions();\r
-\r
- /* Initialize the secure context management system. */\r
- SecureContext_Init();\r
- }\r
- #endif /* configENABLE_TRUSTZONE */\r
-\r
- #if( configENABLE_FPU == 1 )\r
- {\r
- /* Setup the Floating Point Unit (FPU). */\r
- prvSetupFPU();\r
- }\r
- #endif /* configENABLE_FPU */\r
-\r
- /* Setup the context of the first task so that the first task starts\r
- * executing. */\r
- vRestoreContextOfFirstTask();\r
- }\r
- break;\r
-\r
- #if( configENABLE_MPU == 1 )\r
- case portSVC_RAISE_PRIVILEGE:\r
- {\r
- /* Only raise the privilege, if the svc was raised from any of\r
- * the system calls. */\r
- if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&\r
- ulPC <= ( uint32_t ) __syscalls_flash_end__ )\r
- {\r
- vRaisePrivilege();\r
- }\r
- }\r
- break;\r
- #endif /* configENABLE_MPU */\r
-\r
- default:\r
- {\r
- /* Incorrect SVC call. */\r
- configASSERT( pdFALSE );\r
- }\r
- }\r
+ /* Register are stored on the stack in the following order - R0, R1, R2, R3,\r
+ * R12, LR, PC, xPSR. */\r
+ ulPC = pulCallerStackAddress[ 6 ];\r
+ ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];\r
+\r
+ switch( ucSVCNumber )\r
+ {\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ case portSVC_ALLOCATE_SECURE_CONTEXT:\r
+ {\r
+ /* R0 contains the stack size passed as parameter to the\r
+ * vPortAllocateSecureContext function. */\r
+ ulR0 = pulCallerStackAddress[ 0 ];\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ /* Read the CONTROL register value. */\r
+ __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );\r
+\r
+ /* The task that raised the SVC is privileged if Bit[0]\r
+ * in the CONTROL register is 0. */\r
+ ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );\r
+\r
+ /* Allocate and load a context for the secure task. */\r
+ xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );\r
+ }\r
+ #else\r
+ {\r
+ /* Allocate and load a context for the secure task. */\r
+ xSecureContext = SecureContext_AllocateContext( ulR0 );\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ configASSERT( xSecureContext != NULL );\r
+ SecureContext_LoadContext( xSecureContext );\r
+ }\r
+ break;\r
+\r
+ case portSVC_FREE_SECURE_CONTEXT:\r
+ {\r
+ /* R0 contains the secure context handle to be freed. */\r
+ ulR0 = pulCallerStackAddress[ 0 ];\r
+\r
+ /* Free the secure context. */\r
+ SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );\r
+ }\r
+ break;\r
+ #endif /* configENABLE_TRUSTZONE */\r
+\r
+ case portSVC_START_SCHEDULER:\r
+ {\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ /* De-prioritize the non-secure exceptions so that the\r
+ * non-secure pendSV runs at the lowest priority. */\r
+ SecureInit_DePrioritizeNSExceptions();\r
+\r
+ /* Initialize the secure context management system. */\r
+ SecureContext_Init();\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+\r
+ #if( configENABLE_FPU == 1 )\r
+ {\r
+ /* Setup the Floating Point Unit (FPU). */\r
+ prvSetupFPU();\r
+ }\r
+ #endif /* configENABLE_FPU */\r
+\r
+ /* Setup the context of the first task so that the first task starts\r
+ * executing. */\r
+ vRestoreContextOfFirstTask();\r
+ }\r
+ break;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ case portSVC_RAISE_PRIVILEGE:\r
+ {\r
+ /* Only raise the privilege, if the svc was raised from any of\r
+ * the system calls. */\r
+ if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&\r
+ ulPC <= ( uint32_t ) __syscalls_flash_end__ )\r
+ {\r
+ vRaisePrivilege();\r
+ }\r
+ }\r
+ break;\r
+ #endif /* configENABLE_MPU */\r
+\r
+ default:\r
+ {\r
+ /* Incorrect SVC call. */\r
+ configASSERT( pdFALSE );\r
+ }\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
\r
#if( configENABLE_MPU == 1 )\r
- StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */\r
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */\r
#else\r
- StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */\r
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */\r
#endif /* configENABLE_MPU */\r
{\r
- /* Simulate the stack frame as it would be created by a context switch\r
- * interrupt. */\r
- #if( portPRELOAD_REGISTERS == 0 )\r
- {\r
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
- *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\r
- pxTopOfStack -= 5; /* R12, R3, R2 and R1. */\r
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
- pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */\r
- *pxTopOfStack = portINITIAL_EXC_RETURN;\r
-\r
- #if( configENABLE_MPU == 1 )\r
- {\r
- pxTopOfStack--;\r
- if( xRunPrivileged == pdTRUE )\r
- {\r
- *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
- }\r
- else\r
- {\r
- *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
- }\r
- }\r
- #endif /* configENABLE_MPU */\r
-\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\r
-\r
- #if( configENABLE_TRUSTZONE == 1 )\r
- {\r
- pxTopOfStack--;\r
- *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\r
- }\r
- #endif /* configENABLE_TRUSTZONE */\r
- }\r
- #else /* portPRELOAD_REGISTERS */\r
- {\r
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
- *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */\r
-\r
- #if( configENABLE_MPU == 1 )\r
- {\r
- pxTopOfStack--;\r
- if( xRunPrivileged == pdTRUE )\r
- {\r
- *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
- }\r
- else\r
- {\r
- *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
- }\r
- }\r
- #endif /* configENABLE_MPU */\r
-\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\r
-\r
- #if( configENABLE_TRUSTZONE == 1 )\r
- {\r
- pxTopOfStack--;\r
- *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\r
- }\r
- #endif /* configENABLE_TRUSTZONE */\r
- }\r
- #endif /* portPRELOAD_REGISTERS */\r
-\r
- return pxTopOfStack;\r
+ /* Simulate the stack frame as it would be created by a context switch\r
+ * interrupt. */\r
+ #if( portPRELOAD_REGISTERS == 0 )\r
+ {\r
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\r
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */\r
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
+ pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */\r
+ *pxTopOfStack = portINITIAL_EXC_RETURN;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ if( xRunPrivileged == pdTRUE )\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ else\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\r
+\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+ }\r
+ #else /* portPRELOAD_REGISTERS */\r
+ {\r
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ if( xRunPrivileged == pdTRUE )\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ else\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\r
+\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+ }\r
+ #endif /* portPRELOAD_REGISTERS */\r
+\r
+ return pxTopOfStack;\r
}\r
/*-----------------------------------------------------------*/\r
\r
BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */\r
{\r
- /* Make PendSV, CallSV and SysTick the same priority as the kernel. */\r
- *( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;\r
- *( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;\r
-\r
- #if( configENABLE_MPU == 1 )\r
- {\r
- /* Setup the Memory Protection Unit (MPU). */\r
- prvSetupMPU();\r
- }\r
- #endif /* configENABLE_MPU */\r
-\r
- /* Start the timer that generates the tick ISR. Interrupts are disabled\r
- * here already. */\r
- prvSetupTimerInterrupt();\r
-\r
- /* Initialize the critical nesting count ready for the first task. */\r
- ulCriticalNesting = 0;\r
-\r
- /* Start the first task. */\r
- vStartFirstTask();\r
-\r
- /* Should never get here as the tasks will now be executing. Call the task\r
- * exit error function to prevent compiler warnings about a static function\r
- * not being called in the case that the application writer overrides this\r
- * functionality by defining configTASK_RETURN_ADDRESS. Call\r
- * vTaskSwitchContext() so link time optimization does not remove the\r
- * symbol. */\r
- vTaskSwitchContext();\r
- prvTaskExitError();\r
-\r
- /* Should not get here. */\r
- return 0;\r
+ /* Make PendSV, CallSV and SysTick the same priority as the kernel. */\r
+ *( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;\r
+ *( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ /* Setup the Memory Protection Unit (MPU). */\r
+ prvSetupMPU();\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ /* Start the timer that generates the tick ISR. Interrupts are disabled\r
+ * here already. */\r
+ prvSetupTimerInterrupt();\r
+\r
+ /* Initialize the critical nesting count ready for the first task. */\r
+ ulCriticalNesting = 0;\r
+\r
+ /* Start the first task. */\r
+ vStartFirstTask();\r
+\r
+ /* Should never get here as the tasks will now be executing. Call the task\r
+ * exit error function to prevent compiler warnings about a static function\r
+ * not being called in the case that the application writer overrides this\r
+ * functionality by defining configTASK_RETURN_ADDRESS. Call\r
+ * vTaskSwitchContext() so link time optimization does not remove the\r
+ * symbol. */\r
+ vTaskSwitchContext();\r
+ prvTaskExitError();\r
+\r
+ /* Should not get here. */\r
+ return 0;\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */\r
{\r
- /* Not implemented in ports where there is nothing to return to.\r
- * Artificially force an assert. */\r
- configASSERT( ulCriticalNesting == 1000UL );\r
+ /* Not implemented in ports where there is nothing to return to.\r
+ * Artificially force an assert. */\r
+ configASSERT( ulCriticalNesting == 1000UL );\r
}\r
/*-----------------------------------------------------------*/\r
\r
#if( configENABLE_MPU == 1 )\r
- void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )\r
- {\r
- uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;\r
- int32_t lIndex = 0;\r
-\r
- /* Setup MAIR0. */\r
- xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
- xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
-\r
- /* This function is called automatically when the task is created - in\r
- * which case the stack region parameters will be valid. At all other\r
- * times the stack parameters will not be valid and it is assumed that\r
- * the stack region has already been configured. */\r
- if( ulStackDepth > 0 )\r
- {\r
- /* Define the region that allows access to the stack. */\r
- ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;\r
- ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;\r
- ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\r
-\r
- xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |\r
- ( portMPU_REGION_NON_SHAREABLE ) |\r
- ( portMPU_REGION_READ_WRITE ) |\r
- ( portMPU_REGION_EXECUTE_NEVER );\r
-\r
- xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |\r
- ( portMPU_RLAR_ATTR_INDEX0 ) |\r
- ( portMPU_RLAR_REGION_ENABLE );\r
- }\r
-\r
- /* User supplied configurable regions. */\r
- for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )\r
- {\r
- /* If xRegions is NULL i.e. the task has not specified any MPU\r
- * region, the else part ensures that all the configurable MPU\r
- * regions are invalidated. */\r
- if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )\r
- {\r
- /* Translate the generic region definition contained in xRegions\r
- * into the ARMv8 specific MPU settings that are then stored in\r
- * xMPUSettings. */\r
- ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;\r
- ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;\r
- ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\r
-\r
- /* Start address. */\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |\r
- ( portMPU_REGION_NON_SHAREABLE );\r
-\r
- /* RO/RW. */\r
- if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )\r
- {\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );\r
- }\r
- else\r
- {\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );\r
- }\r
-\r
- /* XN. */\r
- if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )\r
- {\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );\r
- }\r
-\r
- /* End Address. */\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |\r
- ( portMPU_RLAR_REGION_ENABLE );\r
-\r
- /* Normal memory/ Device memory. */\r
- if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )\r
- {\r
- /* Attr1 in MAIR0 is configured as device memory. */\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;\r
- }\r
- else\r
- {\r
- /* Attr1 in MAIR0 is configured as normal memory. */\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;\r
- }\r
- }\r
- else\r
- {\r
- /* Invalidate the region. */\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;\r
- }\r
-\r
- lIndex++;\r
- }\r
- }\r
+ void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )\r
+ {\r
+ uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;\r
+ int32_t lIndex = 0;\r
+\r
+ /* Setup MAIR0. */\r
+ xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
+ xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
+\r
+ /* This function is called automatically when the task is created - in\r
+ * which case the stack region parameters will be valid. At all other\r
+ * times the stack parameters will not be valid and it is assumed that\r
+ * the stack region has already been configured. */\r
+ if( ulStackDepth > 0 )\r
+ {\r
+ /* Define the region that allows access to the stack. */\r
+ ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;\r
+ ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;\r
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\r
+\r
+ xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_WRITE ) |\r
+ ( portMPU_REGION_EXECUTE_NEVER );\r
+\r
+ xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+ }\r
+\r
+ /* User supplied configurable regions. */\r
+ for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )\r
+ {\r
+ /* If xRegions is NULL i.e. the task has not specified any MPU\r
+ * region, the else part ensures that all the configurable MPU\r
+ * regions are invalidated. */\r
+ if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )\r
+ {\r
+ /* Translate the generic region definition contained in xRegions\r
+ * into the ARMv8 specific MPU settings that are then stored in\r
+ * xMPUSettings. */\r
+ ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;\r
+ ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;\r
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\r
+\r
+ /* Start address. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |\r
+ ( portMPU_REGION_NON_SHAREABLE );\r
+\r
+ /* RO/RW. */\r
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )\r
+ {\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );\r
+ }\r
+ else\r
+ {\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );\r
+ }\r
+\r
+ /* XN. */\r
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )\r
+ {\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );\r
+ }\r
+\r
+ /* End Address. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Normal memory/ Device memory. */\r
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )\r
+ {\r
+ /* Attr1 in MAIR0 is configured as device memory. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;\r
+ }\r
+ else\r
+ {\r
+ /* Attr1 in MAIR0 is configured as normal memory. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Invalidate the region. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;\r
+ }\r
+\r
+ lIndex++;\r
+ }\r
+ }\r
#endif /* configENABLE_MPU */\r
/*-----------------------------------------------------------*/\r
* 1 tab == 4 spaces!\r
*/\r
\r
- EXTERN pxCurrentTCB\r
- EXTERN xSecureContext\r
- EXTERN vTaskSwitchContext\r
- EXTERN vPortSVCHandler_C\r
- EXTERN SecureContext_SaveContext\r
- EXTERN SecureContext_LoadContext\r
+ EXTERN pxCurrentTCB\r
+ EXTERN xSecureContext\r
+ EXTERN vTaskSwitchContext\r
+ EXTERN vPortSVCHandler_C\r
+ EXTERN SecureContext_SaveContext\r
+ EXTERN SecureContext_LoadContext\r
\r
- PUBLIC xIsPrivileged\r
- PUBLIC vResetPrivilege\r
- PUBLIC vPortAllocateSecureContext\r
- PUBLIC vRestoreContextOfFirstTask\r
- PUBLIC vRaisePrivilege\r
- PUBLIC vStartFirstTask\r
- PUBLIC ulSetInterruptMaskFromISR\r
- PUBLIC vClearInterruptMaskFromISR\r
- PUBLIC PendSV_Handler\r
- PUBLIC SVC_Handler\r
- PUBLIC vPortFreeSecureContext\r
+ PUBLIC xIsPrivileged\r
+ PUBLIC vResetPrivilege\r
+ PUBLIC vPortAllocateSecureContext\r
+ PUBLIC vRestoreContextOfFirstTask\r
+ PUBLIC vRaisePrivilege\r
+ PUBLIC vStartFirstTask\r
+ PUBLIC ulSetInterruptMaskFromISR\r
+ PUBLIC vClearInterruptMaskFromISR\r
+ PUBLIC PendSV_Handler\r
+ PUBLIC SVC_Handler\r
+ PUBLIC vPortFreeSecureContext\r
/*-----------------------------------------------------------*/\r
\r
/*---------------- Unprivileged Functions -------------------*/\r
\r
/*-----------------------------------------------------------*/\r
\r
- SECTION .text:CODE:NOROOT(2)\r
- THUMB\r
+ SECTION .text:CODE:NOROOT(2)\r
+ THUMB\r
/*-----------------------------------------------------------*/\r
\r
xIsPrivileged:\r
- mrs r0, control /* r0 = CONTROL. */\r
- tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\r
- ite ne\r
- movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
- moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */\r
- bx lr /* Return. */\r
+ mrs r0, control /* r0 = CONTROL. */\r
+ tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\r
+ ite ne\r
+ movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
+ moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */\r
+ bx lr /* Return. */\r
/*-----------------------------------------------------------*/\r
\r
vResetPrivilege:\r
- mrs r0, control /* r0 = CONTROL. */\r
- orr r0, r0, #1 /* r0 = r0 | 1. */\r
- msr control, r0 /* CONTROL = r0. */\r
- bx lr /* Return to the caller. */\r
+ mrs r0, control /* r0 = CONTROL. */\r
+ orr r0, r0, #1 /* r0 = r0 | 1. */\r
+ msr control, r0 /* CONTROL = r0. */\r
+ bx lr /* Return to the caller. */\r
/*-----------------------------------------------------------*/\r
\r
vPortAllocateSecureContext:\r
- svc 0 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */\r
- bx lr /* Return. */\r
+ svc 0 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */\r
+ bx lr /* Return. */\r
/*-----------------------------------------------------------*/\r
\r
/*----------------- Privileged Functions --------------------*/\r
\r
/*-----------------------------------------------------------*/\r
\r
- SECTION privileged_functions:CODE:NOROOT(2)\r
- THUMB\r
+ SECTION privileged_functions:CODE:NOROOT(2)\r
+ THUMB\r
/*-----------------------------------------------------------*/\r
\r
vRestoreContextOfFirstTask:\r
- ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
- ldr r3, [r2] /* Read pxCurrentTCB. */\r
- ldr r0, [r3] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ ldr r3, [r2] /* Read pxCurrentTCB. */\r
+ ldr r0, [r3] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
\r
#if ( configENABLE_MPU == 1 )\r
- adds r3, #4 /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
- ldr r4, [r3] /* r4 = *r3 i.e. r4 = MAIR0. */\r
- ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
- str r4, [r2] /* Program MAIR0. */\r
- ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */\r
- movs r4, #4 /* r4 = 4. */\r
- str r4, [r2] /* Program RNR = 4. */\r
- adds r3, #4 /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\r
- ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */\r
- ldmia r3!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */\r
- stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+ adds r3, #4 /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
+ ldr r4, [r3] /* r4 = *r3 i.e. r4 = MAIR0. */\r
+ ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ str r4, [r2] /* Program MAIR0. */\r
+ ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ movs r4, #4 /* r4 = 4. */\r
+ str r4, [r2] /* Program RNR = 4. */\r
+ adds r3, #4 /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\r
+ ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */\r
+ ldmia r3!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */\r
+ stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
#endif /* configENABLE_MPU */\r
\r
#if ( configENABLE_MPU == 1 )\r
- ldm r0!, {r1-r4} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */\r
- ldr r5, =xSecureContext\r
- str r1, [r5] /* Set xSecureContext to this task's value for the same. */\r
- msr psplim, r2 /* Set this task's PSPLIM value. */\r
- msr control, r3 /* Set this task's CONTROL value. */\r
- adds r0, #32 /* Discard everything up to r0. */\r
- msr psp, r0 /* This is now the new top of stack to use in the task. */\r
- isb\r
- bx r4 /* Finally, branch to EXC_RETURN. */\r
+ ldm r0!, {r1-r4} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */\r
+ ldr r5, =xSecureContext\r
+ str r1, [r5] /* Set xSecureContext to this task's value for the same. */\r
+ msr psplim, r2 /* Set this task's PSPLIM value. */\r
+ msr control, r3 /* Set this task's CONTROL value. */\r
+ adds r0, #32 /* Discard everything up to r0. */\r
+ msr psp, r0 /* This is now the new top of stack to use in the task. */\r
+ isb\r
+ bx r4 /* Finally, branch to EXC_RETURN. */\r
#else /* configENABLE_MPU */\r
- ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */\r
- ldr r4, =xSecureContext\r
- str r1, [r4] /* Set xSecureContext to this task's value for the same. */\r
- msr psplim, r2 /* Set this task's PSPLIM value. */\r
- movs r1, #2 /* r1 = 2. */\r
- msr CONTROL, r1 /* Switch to use PSP in the thread mode. */\r
- adds r0, #32 /* Discard everything up to r0. */\r
- msr psp, r0 /* This is now the new top of stack to use in the task. */\r
- isb\r
- bx r3 /* Finally, branch to EXC_RETURN. */\r
+ ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */\r
+ ldr r4, =xSecureContext\r
+ str r1, [r4] /* Set xSecureContext to this task's value for the same. */\r
+ msr psplim, r2 /* Set this task's PSPLIM value. */\r
+ movs r1, #2 /* r1 = 2. */\r
+ msr CONTROL, r1 /* Switch to use PSP in the thread mode. */\r
+ adds r0, #32 /* Discard everything up to r0. */\r
+ msr psp, r0 /* This is now the new top of stack to use in the task. */\r
+ isb\r
+ bx r3 /* Finally, branch to EXC_RETURN. */\r
#endif /* configENABLE_MPU */\r
/*-----------------------------------------------------------*/\r
\r
vRaisePrivilege:\r
- mrs r0, control /* Read the CONTROL register. */\r
- bic r0, r0, #1 /* Clear the bit 0. */\r
- msr control, r0 /* Write back the new CONTROL value. */\r
- bx lr /* Return to the caller. */\r
+ mrs r0, control /* Read the CONTROL register. */\r
+ bic r0, r0, #1 /* Clear the bit 0. */\r
+ msr control, r0 /* Write back the new CONTROL value. */\r
+ bx lr /* Return to the caller. */\r
/*-----------------------------------------------------------*/\r
\r
vStartFirstTask:\r
- ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */\r
- ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */\r
- ldr r0, [r0] /* The first entry in vector table is stack pointer. */\r
- msr msp, r0 /* Set the MSP back to the start of the stack. */\r
- cpsie i /* Globally enable interrupts. */\r
- cpsie f\r
- dsb\r
- isb\r
- svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */\r
+ ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */\r
+ ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */\r
+ ldr r0, [r0] /* The first entry in vector table is stack pointer. */\r
+ msr msp, r0 /* Set the MSP back to the start of the stack. */\r
+ cpsie i /* Globally enable interrupts. */\r
+ cpsie f\r
+ dsb\r
+ isb\r
+ svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */\r
/*-----------------------------------------------------------*/\r
\r
ulSetInterruptMaskFromISR:\r
- mrs r0, PRIMASK\r
- cpsid i\r
- bx lr\r
+ mrs r0, PRIMASK\r
+ cpsid i\r
+ bx lr\r
/*-----------------------------------------------------------*/\r
\r
vClearInterruptMaskFromISR:\r
- msr PRIMASK, r0\r
- bx lr\r
+ msr PRIMASK, r0\r
+ bx lr\r
/*-----------------------------------------------------------*/\r
\r
PendSV_Handler:\r
- mrs r1, psp /* Read PSP in r1. */\r
- ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
- ldr r0, [r2] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */\r
+ mrs r1, psp /* Read PSP in r1. */\r
+ ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
+ ldr r0, [r2] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */\r
\r
- cbz r0, save_ns_context /* No secure context to save. */\r
- push {r0-r2, r14}\r
- bl SecureContext_SaveContext\r
- pop {r0-r3} /* LR is now in r3. */\r
- mov lr, r3 /* LR = r3. */\r
- lsls r2, r3, #25 /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
- bpl save_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
- ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
- ldr r2, [r3] /* Read pxCurrentTCB. */\r
+ cbz r0, save_ns_context /* No secure context to save. */\r
+ push {r0-r2, r14}\r
+ bl SecureContext_SaveContext\r
+ pop {r0-r3} /* LR is now in r3. */\r
+ mov lr, r3 /* LR = r3. */\r
+ lsls r2, r3, #25 /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
+ bpl save_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
+ ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ ldr r2, [r3] /* Read pxCurrentTCB. */\r
#if ( configENABLE_MPU == 1 )\r
- subs r1, r1, #16 /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
- str r1, [r2] /* Save the new top of stack in TCB. */\r
- mrs r2, psplim /* r2 = PSPLIM. */\r
- mrs r3, control /* r3 = CONTROL. */\r
- mov r4, lr /* r4 = LR/EXC_RETURN. */\r
- stmia r1!, {r0, r2-r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
+ subs r1, r1, #16 /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
+ str r1, [r2] /* Save the new top of stack in TCB. */\r
+ mrs r2, psplim /* r2 = PSPLIM. */\r
+ mrs r3, control /* r3 = CONTROL. */\r
+ mov r4, lr /* r4 = LR/EXC_RETURN. */\r
+ stmia r1!, {r0, r2-r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
#else /* configENABLE_MPU */\r
- subs r1, r1, #12 /* Make space for xSecureContext, PSPLIM and LR on the stack. */\r
- str r1, [r2] /* Save the new top of stack in TCB. */\r
- mrs r2, psplim /* r2 = PSPLIM. */\r
- mov r3, lr /* r3 = LR/EXC_RETURN. */\r
- stmia r1!, {r0, r2-r3} /* Store xSecureContext, PSPLIM and LR on the stack. */\r
+ subs r1, r1, #12 /* Make space for xSecureContext, PSPLIM and LR on the stack. */\r
+ str r1, [r2] /* Save the new top of stack in TCB. */\r
+ mrs r2, psplim /* r2 = PSPLIM. */\r
+ mov r3, lr /* r3 = LR/EXC_RETURN. */\r
+ stmia r1!, {r0, r2-r3} /* Store xSecureContext, PSPLIM and LR on the stack. */\r
#endif /* configENABLE_MPU */\r
- b select_next_task\r
+ b select_next_task\r
\r
- save_ns_context:\r
- ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
- ldr r2, [r3] /* Read pxCurrentTCB. */\r
- #if ( configENABLE_FPU == 1 )\r
- tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
- it eq\r
- vstmdbeq r1!, {s16-s31} /* Store the FPU registers which are not saved automatically. */\r
- #endif /* configENABLE_FPU */\r
- #if ( configENABLE_MPU == 1 )\r
- subs r1, r1, #48 /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */\r
- str r1, [r2] /* Save the new top of stack in TCB. */\r
- adds r1, r1, #16 /* r1 = r1 + 16. */\r
- stm r1, {r4-r11} /* Store the registers that are not saved automatically. */\r
- mrs r2, psplim /* r2 = PSPLIM. */\r
- mrs r3, control /* r3 = CONTROL. */\r
- mov r4, lr /* r4 = LR/EXC_RETURN. */\r
- subs r1, r1, #16 /* r1 = r1 - 16. */\r
- stm r1, {r0, r2-r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
- #else /* configENABLE_MPU */\r
- subs r1, r1, #44 /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */\r
- str r1, [r2] /* Save the new top of stack in TCB. */\r
- adds r1, r1, #12 /* r1 = r1 + 12. */\r
- stm r1, {r4-r11} /* Store the registers that are not saved automatically. */\r
- mrs r2, psplim /* r2 = PSPLIM. */\r
- mov r3, lr /* r3 = LR/EXC_RETURN. */\r
- subs r1, r1, #12 /* r1 = r1 - 12. */\r
- stmia r1!, {r0, r2-r3} /* Store xSecureContext, PSPLIM and LR on the stack. */\r
- #endif /* configENABLE_MPU */\r
+ save_ns_context:\r
+ ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ ldr r2, [r3] /* Read pxCurrentTCB. */\r
+ #if ( configENABLE_FPU == 1 )\r
+ tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
+ it eq\r
+ vstmdbeq r1!, {s16-s31} /* Store the FPU registers which are not saved automatically. */\r
+ #endif /* configENABLE_FPU */\r
+ #if ( configENABLE_MPU == 1 )\r
+ subs r1, r1, #48 /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */\r
+ str r1, [r2] /* Save the new top of stack in TCB. */\r
+ adds r1, r1, #16 /* r1 = r1 + 16. */\r
+ stm r1, {r4-r11} /* Store the registers that are not saved automatically. */\r
+ mrs r2, psplim /* r2 = PSPLIM. */\r
+ mrs r3, control /* r3 = CONTROL. */\r
+ mov r4, lr /* r4 = LR/EXC_RETURN. */\r
+ subs r1, r1, #16 /* r1 = r1 - 16. */\r
+ stm r1, {r0, r2-r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
+ #else /* configENABLE_MPU */\r
+ subs r1, r1, #44 /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */\r
+ str r1, [r2] /* Save the new top of stack in TCB. */\r
+ adds r1, r1, #12 /* r1 = r1 + 12. */\r
+ stm r1, {r4-r11} /* Store the registers that are not saved automatically. */\r
+ mrs r2, psplim /* r2 = PSPLIM. */\r
+ mov r3, lr /* r3 = LR/EXC_RETURN. */\r
+ subs r1, r1, #12 /* r1 = r1 - 12. */\r
+ stmia r1!, {r0, r2-r3} /* Store xSecureContext, PSPLIM and LR on the stack. */\r
+ #endif /* configENABLE_MPU */\r
\r
- select_next_task:\r
- cpsid i\r
- bl vTaskSwitchContext\r
- cpsie i\r
+ select_next_task:\r
+ cpsid i\r
+ bl vTaskSwitchContext\r
+ cpsie i\r
\r
- ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
- ldr r3, [r2] /* Read pxCurrentTCB. */\r
- ldr r1, [r3] /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */\r
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ ldr r3, [r2] /* Read pxCurrentTCB. */\r
+ ldr r1, [r3] /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */\r
\r
- #if ( configENABLE_MPU == 1 )\r
- adds r3, #4 /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
- ldr r4, [r3] /* r4 = *r3 i.e. r4 = MAIR0. */\r
- ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
- str r4, [r2] /* Program MAIR0. */\r
- ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */\r
- movs r4, #4 /* r4 = 4. */\r
- str r4, [r2] /* Program RNR = 4. */\r
- adds r3, #4 /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\r
- ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */\r
- ldmia r3!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
- stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
- #endif /* configENABLE_MPU */\r
+ #if ( configENABLE_MPU == 1 )\r
+ adds r3, #4 /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
+ ldr r4, [r3] /* r4 = *r3 i.e. r4 = MAIR0. */\r
+ ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ str r4, [r2] /* Program MAIR0. */\r
+ ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ movs r4, #4 /* r4 = 4. */\r
+ str r4, [r2] /* Program RNR = 4. */\r
+ adds r3, #4 /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\r
+ ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */\r
+ ldmia r3!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
+ stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+ #endif /* configENABLE_MPU */\r
\r
- #if ( configENABLE_MPU == 1 )\r
- ldmia r1!, {r0, r2-r4} /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */\r
- msr psplim, r2 /* Restore the PSPLIM register value for the task. */\r
- msr control, r3 /* Restore the CONTROL register value for the task. */\r
- mov lr, r4 /* LR = r4. */\r
- ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
- str r0, [r2] /* Restore the task's xSecureContext. */\r
- cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */\r
- push {r1,r4}\r
- bl SecureContext_LoadContext /* Restore the secure context. */\r
- pop {r1,r4}\r
- mov lr, r4 /* LR = r4. */\r
- lsls r2, r4, #25 /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
- bpl restore_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
- msr psp, r1 /* Remember the new top of stack for the task. */\r
- bx lr\r
- #else /* configENABLE_MPU */\r
- ldmia r1!, {r0, r2-r3} /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */\r
- msr psplim, r2 /* Restore the PSPLIM register value for the task. */\r
- mov lr, r3 /* LR = r3. */\r
- ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
- str r0, [r2] /* Restore the task's xSecureContext. */\r
- cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */\r
- push {r1,r3}\r
- bl SecureContext_LoadContext /* Restore the secure context. */\r
- pop {r1,r3}\r
- mov lr, r3 /* LR = r3. */\r
- lsls r2, r3, #25 /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
- bpl restore_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
- msr psp, r1 /* Remember the new top of stack for the task. */\r
- bx lr\r
- #endif /* configENABLE_MPU */\r
+ #if ( configENABLE_MPU == 1 )\r
+ ldmia r1!, {r0, r2-r4} /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */\r
+ msr psplim, r2 /* Restore the PSPLIM register value for the task. */\r
+ msr control, r3 /* Restore the CONTROL register value for the task. */\r
+ mov lr, r4 /* LR = r4. */\r
+ ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
+ str r0, [r2] /* Restore the task's xSecureContext. */\r
+ cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */\r
+ push {r1,r4}\r
+ bl SecureContext_LoadContext /* Restore the secure context. */\r
+ pop {r1,r4}\r
+ mov lr, r4 /* LR = r4. */\r
+ lsls r2, r4, #25 /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
+ bpl restore_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
+ msr psp, r1 /* Remember the new top of stack for the task. */\r
+ bx lr\r
+ #else /* configENABLE_MPU */\r
+ ldmia r1!, {r0, r2-r3} /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */\r
+ msr psplim, r2 /* Restore the PSPLIM register value for the task. */\r
+ mov lr, r3 /* LR = r3. */\r
+ ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
+ str r0, [r2] /* Restore the task's xSecureContext. */\r
+ cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */\r
+ push {r1,r3}\r
+ bl SecureContext_LoadContext /* Restore the secure context. */\r
+ pop {r1,r3}\r
+ mov lr, r3 /* LR = r3. */\r
+ lsls r2, r3, #25 /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
+ bpl restore_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
+ msr psp, r1 /* Remember the new top of stack for the task. */\r
+ bx lr\r
+ #endif /* configENABLE_MPU */\r
\r
- restore_ns_context:\r
- ldmia r1!, {r4-r11} /* Restore the registers that are not automatically restored. */\r
- #if ( configENABLE_FPU == 1 )\r
- tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
- it eq\r
- vldmiaeq r1!, {s16-s31} /* Restore the FPU registers which are not restored automatically. */\r
- #endif /* configENABLE_FPU */\r
- msr psp, r1 /* Remember the new top of stack for the task. */\r
- bx lr\r
+ restore_ns_context:\r
+ ldmia r1!, {r4-r11} /* Restore the registers that are not automatically restored. */\r
+ #if ( configENABLE_FPU == 1 )\r
+ tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
+ it eq\r
+ vldmiaeq r1!, {s16-s31} /* Restore the FPU registers which are not restored automatically. */\r
+ #endif /* configENABLE_FPU */\r
+ msr psp, r1 /* Remember the new top of stack for the task. */\r
+ bx lr\r
/*-----------------------------------------------------------*/\r
\r
SVC_Handler:\r
- tst lr, #4\r
- ite eq\r
- mrseq r0, msp\r
- mrsne r0, psp\r
- b vPortSVCHandler_C\r
+ tst lr, #4\r
+ ite eq\r
+ mrseq r0, msp\r
+ mrsne r0, psp\r
+ b vPortSVCHandler_C\r
/*-----------------------------------------------------------*/\r
\r
vPortFreeSecureContext:\r
- /* r0 = uint32_t *pulTCB. */\r
- ldr r1, [r0] /* The first item in the TCB is the top of the stack. */\r
- ldr r0, [r1] /* The first item on the stack is the task's xSecureContext. */\r
- cmp r0, #0 /* Raise svc if task's xSecureContext is not NULL. */\r
- it ne\r
- svcne 1 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */\r
- bx lr /* Return. */\r
+ /* r0 = uint32_t *pulTCB. */\r
+ ldr r1, [r0] /* The first item in the TCB is the top of the stack. */\r
+ ldr r0, [r1] /* The first item on the stack is the task's xSecureContext. */\r
+ cmp r0, #0 /* Raise svc if task's xSecureContext is not NULL. */\r
+ it ne\r
+ svcne 1 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */\r
+ bx lr /* Return. */\r
/*-----------------------------------------------------------*/\r
\r
- END\r
+ END\r
*------------------------------------------------------------------------------\r
*/\r
\r
+#ifndef configENABLE_FPU\r
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h.\r
+#endif /* configENABLE_FPU */\r
+\r
+#ifndef configENABLE_MPU\r
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h.\r
+#endif /* configENABLE_MPU */\r
+\r
+#ifndef configENABLE_TRUSTZONE\r
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.\r
+#endif /* configENABLE_TRUSTZONE */\r
+/*-----------------------------------------------------------*/\r
+\r
/**\r
* @brief Type definitions.\r
*/\r
-#define portCHAR char\r
-#define portFLOAT float\r
-#define portDOUBLE double\r
-#define portLONG long\r
-#define portSHORT short\r
-#define portSTACK_TYPE uint32_t\r
-#define portBASE_TYPE long\r
-\r
-typedef portSTACK_TYPE StackType_t;\r
-typedef long BaseType_t;\r
-typedef unsigned long UBaseType_t;\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT short\r
+#define portSTACK_TYPE uint32_t\r
+#define portBASE_TYPE long\r
+\r
+typedef portSTACK_TYPE StackType_t;\r
+typedef long BaseType_t;\r
+typedef unsigned long UBaseType_t;\r
\r
#if( configUSE_16_BIT_TICKS == 1 )\r
- typedef uint16_t TickType_t;\r
- #define portMAX_DELAY ( TickType_t ) 0xffff\r
+ typedef uint16_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffff\r
#else\r
- typedef uint32_t TickType_t;\r
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL\r
+ typedef uint32_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL\r
\r
- /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\r
- * not need to be guarded with a critical section. */\r
- #define portTICK_TYPE_IS_ATOMIC 1\r
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\r
+ * not need to be guarded with a critical section. */\r
+ #define portTICK_TYPE_IS_ATOMIC 1\r
#endif\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* Architecture specifics.\r
*/\r
-#define portSTACK_GROWTH ( -1 )\r
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
-#define portBYTE_ALIGNMENT 8\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
+#define portBYTE_ALIGNMENT 8\r
#define portNOP()\r
-#define portINLINE __inline\r
+#define portINLINE __inline\r
#ifndef portFORCE_INLINE\r
- #define portFORCE_INLINE inline __attribute__(( always_inline ))\r
+ #define portFORCE_INLINE inline __attribute__(( always_inline ))\r
#endif\r
-#define portHAS_STACK_OVERFLOW_CHECKING 1\r
+#define portHAS_STACK_OVERFLOW_CHECKING 1\r
/*-----------------------------------------------------------*/\r
\r
/**\r
extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );\r
- extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* PRIVILEGED_FUNCTION */;\r
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );\r
+ extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* PRIVILEGED_FUNCTION */;\r
#endif /* configENABLE_TRUSTZONE */\r
\r
#if( configENABLE_MPU == 1 )\r
- extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;\r
- extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;\r
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;\r
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;\r
#endif /* configENABLE_MPU */\r
/*-----------------------------------------------------------*/\r
\r
* @brief MPU specific constants.\r
*/\r
#if( configENABLE_MPU == 1 )\r
- #define portUSING_MPU_WRAPPERS 1\r
- #define portPRIVILEGE_BIT ( 0x80000000UL )\r
+ #define portUSING_MPU_WRAPPERS 1\r
+ #define portPRIVILEGE_BIT ( 0x80000000UL )\r
#else\r
- #define portPRIVILEGE_BIT ( 0x0UL )\r
+ #define portPRIVILEGE_BIT ( 0x0UL )\r
#endif /* configENABLE_MPU */\r
\r
\r
/* MPU regions. */\r
-#define portPRIVILEGED_FLASH_REGION ( 0UL )\r
-#define portUNPRIVILEGED_FLASH_REGION ( 1UL )\r
-#define portPRIVILEGED_RAM_REGION ( 2UL )\r
-#define portUNPRIVILEGED_DEVICE_REGION ( 3UL )\r
-#define portSTACK_REGION ( 4UL )\r
-#define portFIRST_CONFIGURABLE_REGION ( 5UL )\r
-#define portLAST_CONFIGURABLE_REGION ( 7UL )\r
-#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\r
-#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */\r
+#define portPRIVILEGED_FLASH_REGION ( 0UL )\r
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )\r
+#define portPRIVILEGED_RAM_REGION ( 2UL )\r
+#define portUNPRIVILEGED_DEVICE_REGION ( 3UL )\r
+#define portSTACK_REGION ( 4UL )\r
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )\r
+#define portLAST_CONFIGURABLE_REGION ( 7UL )\r
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\r
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */\r
\r
/* Devices Region. */\r
-#define portDEVICE_REGION_START_ADDRESS ( 0x50000000 )\r
-#define portDEVICE_REGION_END_ADDRESS ( 0x5FFFFFFF )\r
+#define portDEVICE_REGION_START_ADDRESS ( 0x50000000 )\r
+#define portDEVICE_REGION_END_ADDRESS ( 0x5FFFFFFF )\r
\r
/* Device memory attributes used in MPU_MAIR registers.\r
*\r
* 8-bit values encoded as follows:\r
* Bit[7:4] - 0000 - Device Memory\r
* Bit[3:2] - 00 --> Device-nGnRnE\r
- * 01 --> Device-nGnRE\r
- * 10 --> Device-nGRE\r
- * 11 --> Device-GRE\r
+ * 01 --> Device-nGnRE\r
+ * 10 --> Device-nGRE\r
+ * 11 --> Device-GRE\r
* Bit[1:0] - 00, Reserved.\r
*/\r
-#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */\r
-#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */\r
-#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */\r
-#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */\r
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */\r
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */\r
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */\r
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */\r
\r
/* Normal memory attributes used in MPU_MAIR registers. */\r
-#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */\r
-#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */\r
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */\r
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */\r
\r
/* Attributes used in MPU_RBAR registers. */\r
-#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )\r
-#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )\r
-#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )\r
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )\r
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )\r
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )\r
\r
-#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )\r
-#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )\r
-#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )\r
-#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )\r
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )\r
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )\r
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )\r
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )\r
\r
-#define portMPU_REGION_EXECUTE_NEVER ( 1UL )\r
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )\r
/*-----------------------------------------------------------*/\r
\r
/**\r
*/\r
typedef struct MPURegionSettings\r
{\r
- uint32_t ulRBAR; /**< RBAR for the region. */\r
- uint32_t ulRLAR; /**< RLAR for the region. */\r
+ uint32_t ulRBAR; /**< RBAR for the region. */\r
+ uint32_t ulRLAR; /**< RLAR for the region. */\r
} MPURegionSettings_t;\r
\r
/**\r
*/\r
typedef struct MPU_SETTINGS\r
{\r
- uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */\r
- MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */\r
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */\r
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */\r
} xMPU_SETTINGS;\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief SVC numbers.\r
*/\r
-#define portSVC_ALLOCATE_SECURE_CONTEXT 0\r
-#define portSVC_FREE_SECURE_CONTEXT 1\r
-#define portSVC_START_SCHEDULER 2\r
-#define portSVC_RAISE_PRIVILEGE 3\r
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0\r
+#define portSVC_FREE_SECURE_CONTEXT 1\r
+#define portSVC_START_SCHEDULER 2\r
+#define portSVC_RAISE_PRIVILEGE 3\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Scheduler utilities.\r
*/\r
-#define portYIELD() vPortYield()\r
-#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )\r
-#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )\r
-#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT\r
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
+#define portYIELD() vPortYield()\r
+#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )\r
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )\r
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT\r
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Critical section management.\r
*/\r
-#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()\r
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )\r
-#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )\r
-#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )\r
-#define portENTER_CRITICAL() vPortEnterCritical()\r
-#define portEXIT_CRITICAL() vPortExitCritical()\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )\r
+#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )\r
+#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )\r
+#define portENTER_CRITICAL() vPortEnterCritical()\r
+#define portEXIT_CRITICAL() vPortExitCritical()\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Task function macros as described on the FreeRTOS.org WEB site.\r
*/\r
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
/*-----------------------------------------------------------*/\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
- /**\r
- * @brief Allocate a secure context for the task.\r
- *\r
- * Tasks are not created with a secure context. Any task that is going to call\r
- * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a\r
- * secure context before it calls any secure function.\r
- *\r
- * @param[in] ulSecureStackSize The size of the secure stack to be allocated.\r
- */\r
- #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )\r
-\r
- /**\r
- * @brief Called when a task is deleted to delete the task's secure context,\r
- * if it has one.\r
- *\r
- * @param[in] pxTCB The TCB of the task being deleted.\r
- */\r
- #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )\r
+ /**\r
+ * @brief Allocate a secure context for the task.\r
+ *\r
+ * Tasks are not created with a secure context. Any task that is going to call\r
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a\r
+ * secure context before it calls any secure function.\r
+ *\r
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.\r
+ */\r
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )\r
+\r
+ /**\r
+ * @brief Called when a task is deleted to delete the task's secure context,\r
+ * if it has one.\r
+ *\r
+ * @param[in] pxTCB The TCB of the task being deleted.\r
+ */\r
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )\r
#else\r
- #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )\r
- #define portCLEAN_UP_TCB( pxTCB )\r
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )\r
+ #define portCLEAN_UP_TCB( pxTCB )\r
#endif /* configENABLE_TRUSTZONE */\r
/*-----------------------------------------------------------*/\r
\r
#if( configENABLE_MPU == 1 )\r
- /**\r
- * @brief Checks whether or not the processor is privileged.\r
- *\r
- * @return 1 if the processor is already privileged, 0 otherwise.\r
- */\r
- #define portIS_PRIVILEGED() xIsPrivileged()\r
-\r
- /**\r
- * @brief Raise an SVC request to raise privilege.\r
- *\r
- * The SVC handler checks that the SVC was raised from a system call and only\r
- * then it raises the privilege. If this is called from any other place,\r
- * the privilege is not raised.\r
- */\r
- #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );\r
-\r
- /**\r
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\r
- * register.\r
- */\r
- #define portRESET_PRIVILEGE() vResetPrivilege()\r
+ /**\r
+ * @brief Checks whether or not the processor is privileged.\r
+ *\r
+ * @return 1 if the processor is already privileged, 0 otherwise.\r
+ */\r
+ #define portIS_PRIVILEGED() xIsPrivileged()\r
+\r
+ /**\r
+ * @brief Raise an SVC request to raise privilege.\r
+ *\r
+ * The SVC handler checks that the SVC was raised from a system call and only\r
+ * then it raises the privilege. If this is called from any other place,\r
+ * the privilege is not raised.\r
+ */\r
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );\r
+\r
+ /**\r
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\r
+ * register.\r
+ */\r
+ #define portRESET_PRIVILEGE() vResetPrivilege()\r
#else\r
- #define portIS_PRIVILEGED()\r
- #define portRAISE_PRIVILEGE()\r
- #define portRESET_PRIVILEGE()\r
+ #define portIS_PRIVILEGED()\r
+ #define portRAISE_PRIVILEGE()\r
+ #define portRESET_PRIVILEGE()\r
#endif /* configENABLE_MPU */\r
/*-----------------------------------------------------------*/\r
\r
* Bit[0] - 0 --> Thread mode is privileged.\r
* Bit[1] - 1 --> Thread mode uses PSP.\r
*/\r
-#define securecontextCONTROL_VALUE_PRIVILEGED 0x02\r
+#define securecontextCONTROL_VALUE_PRIVILEGED 0x02\r
\r
/**\r
* @brief CONTROL value for un-privileged tasks.\r
* Bit[0] - 1 --> Thread mode is un-privileged.\r
* Bit[1] - 1 --> Thread mode uses PSP.\r
*/\r
-#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03\r
+#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03\r
/*-----------------------------------------------------------*/\r
\r
/**\r
*/\r
typedef struct SecureContext\r
{\r
- uint8_t *pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */\r
- uint8_t *pucStackLimit; /**< Last location of the stack memory (PSPLIM). */\r
- uint8_t *pucStackStart; /**< First location of the stack memory. */\r
+ uint8_t *pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */\r
+ uint8_t *pucStackLimit; /**< Last location of the stack memory (PSPLIM). */\r
+ uint8_t *pucStackStart; /**< First location of the stack memory. */\r
} SecureContext_t;\r
/*-----------------------------------------------------------*/\r
\r
secureportNON_SECURE_CALLABLE void SecureContext_Init( void )\r
{\r
- uint32_t ulIPSR;\r
-\r
- /* Read the Interrupt Program Status Register (IPSR) value. */\r
- secureportREAD_IPSR( ulIPSR );\r
-\r
- /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
- * when the processor is running in the Thread Mode. */\r
- if( ulIPSR != 0 )\r
- {\r
- /* No stack for thread mode until a task's context is loaded. */\r
- secureportSET_PSPLIM( securecontextNO_STACK );\r
- secureportSET_PSP( securecontextNO_STACK );\r
-\r
- #if( configENABLE_MPU == 1 )\r
- {\r
- /* Configure thread mode to use PSP and to be unprivileged. */\r
- secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );\r
- }\r
- #else /* configENABLE_MPU */\r
- {\r
- /* Configure thread mode to use PSP and to be privileged.. */\r
- secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );\r
- }\r
- #endif /* configENABLE_MPU */\r
- }\r
+ uint32_t ulIPSR;\r
+\r
+ /* Read the Interrupt Program Status Register (IPSR) value. */\r
+ secureportREAD_IPSR( ulIPSR );\r
+\r
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
+ * when the processor is running in the Thread Mode. */\r
+ if( ulIPSR != 0 )\r
+ {\r
+ /* No stack for thread mode until a task's context is loaded. */\r
+ secureportSET_PSPLIM( securecontextNO_STACK );\r
+ secureportSET_PSP( securecontextNO_STACK );\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ /* Configure thread mode to use PSP and to be unprivileged. */\r
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );\r
+ }\r
+ #else /* configENABLE_MPU */\r
+ {\r
+ /* Configure thread mode to use PSP and to be privileged.. */\r
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
\r
#if( configENABLE_MPU == 1 )\r
- secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged )\r
+ secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged )\r
#else /* configENABLE_MPU */\r
- secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize )\r
+ secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize )\r
#endif /* configENABLE_MPU */\r
{\r
- uint8_t *pucStackMemory = NULL;\r
- uint32_t ulIPSR;\r
- SecureContextHandle_t xSecureContextHandle = NULL;\r
- #if( configENABLE_MPU == 1 )\r
- uint32_t *pulCurrentStackPointer = NULL;\r
- #endif /* configENABLE_MPU */\r
-\r
- /* Read the Interrupt Program Status Register (IPSR) value. */\r
- secureportREAD_IPSR( ulIPSR );\r
-\r
- /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
- * when the processor is running in the Thread Mode. */\r
- if( ulIPSR != 0 )\r
- {\r
- /* Allocate the context structure. */\r
- xSecureContextHandle = ( SecureContextHandle_t ) pvPortMalloc( sizeof( SecureContext_t ) );\r
-\r
- if( xSecureContextHandle != NULL )\r
- {\r
- /* Allocate the stack space. */\r
- pucStackMemory = pvPortMalloc( ulSecureStackSize );\r
-\r
- if( pucStackMemory != NULL )\r
- {\r
- /* Since stack grows down, the starting point will be the last\r
- * location. Note that this location is next to the last\r
- * allocated byte because the hardware decrements the stack\r
- * pointer before writing i.e. if stack pointer is 0x2, a push\r
- * operation will decrement the stack pointer to 0x1 and then\r
- * write at 0x1. */\r
- xSecureContextHandle->pucStackStart = pucStackMemory + ulSecureStackSize;\r
-\r
- /* The stack cannot go beyond this location. This value is\r
- * programmed in the PSPLIM register on context switch.*/\r
- xSecureContextHandle->pucStackLimit = pucStackMemory;\r
-\r
- #if( configENABLE_MPU == 1 )\r
- {\r
- /* Store the correct CONTROL value for the task on the stack.\r
- * This value is programmed in the CONTROL register on\r
- * context switch. */\r
- pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;\r
- pulCurrentStackPointer--;\r
- if( ulIsTaskPrivileged )\r
- {\r
- *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;\r
- }\r
- else\r
- {\r
- *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;\r
- }\r
-\r
- /* Store the current stack pointer. This value is programmed in\r
- * the PSP register on context switch. */\r
- xSecureContextHandle->pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;\r
- }\r
- #else /* configENABLE_MPU */\r
- {\r
- /* Current SP is set to the starting of the stack. This\r
- * value programmed in the PSP register on context switch. */\r
- xSecureContextHandle->pucCurrentStackPointer = xSecureContextHandle->pucStackStart;\r
-\r
- }\r
- #endif /* configENABLE_MPU */\r
- }\r
- else\r
- {\r
- /* Free the context to avoid memory leak and make sure to return\r
- * NULL to indicate failure. */\r
- vPortFree( xSecureContextHandle );\r
- xSecureContextHandle = NULL;\r
- }\r
- }\r
- }\r
-\r
- return xSecureContextHandle;\r
+ uint8_t *pucStackMemory = NULL;\r
+ uint32_t ulIPSR;\r
+ SecureContextHandle_t xSecureContextHandle = NULL;\r
+ #if( configENABLE_MPU == 1 )\r
+ uint32_t *pulCurrentStackPointer = NULL;\r
+ #endif /* configENABLE_MPU */\r
+\r
+ /* Read the Interrupt Program Status Register (IPSR) value. */\r
+ secureportREAD_IPSR( ulIPSR );\r
+\r
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
+ * when the processor is running in the Thread Mode. */\r
+ if( ulIPSR != 0 )\r
+ {\r
+ /* Allocate the context structure. */\r
+ xSecureContextHandle = ( SecureContextHandle_t ) pvPortMalloc( sizeof( SecureContext_t ) );\r
+\r
+ if( xSecureContextHandle != NULL )\r
+ {\r
+ /* Allocate the stack space. */\r
+ pucStackMemory = pvPortMalloc( ulSecureStackSize );\r
+\r
+ if( pucStackMemory != NULL )\r
+ {\r
+ /* Since stack grows down, the starting point will be the last\r
+ * location. Note that this location is next to the last\r
+ * allocated byte because the hardware decrements the stack\r
+ * pointer before writing i.e. if stack pointer is 0x2, a push\r
+ * operation will decrement the stack pointer to 0x1 and then\r
+ * write at 0x1. */\r
+ xSecureContextHandle->pucStackStart = pucStackMemory + ulSecureStackSize;\r
+\r
+ /* The stack cannot go beyond this location. This value is\r
+ * programmed in the PSPLIM register on context switch.*/\r
+ xSecureContextHandle->pucStackLimit = pucStackMemory;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ /* Store the correct CONTROL value for the task on the stack.\r
+ * This value is programmed in the CONTROL register on\r
+ * context switch. */\r
+ pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;\r
+ pulCurrentStackPointer--;\r
+ if( ulIsTaskPrivileged )\r
+ {\r
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;\r
+ }\r
+ else\r
+ {\r
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;\r
+ }\r
+\r
+ /* Store the current stack pointer. This value is programmed in\r
+ * the PSP register on context switch. */\r
+ xSecureContextHandle->pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;\r
+ }\r
+ #else /* configENABLE_MPU */\r
+ {\r
+ /* Current SP is set to the starting of the stack. This\r
+ * value programmed in the PSP register on context switch. */\r
+ xSecureContextHandle->pucCurrentStackPointer = xSecureContextHandle->pucStackStart;\r
+\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+ }\r
+ else\r
+ {\r
+ /* Free the context to avoid memory leak and make sure to return\r
+ * NULL to indicate failure. */\r
+ vPortFree( xSecureContextHandle );\r
+ xSecureContextHandle = NULL;\r
+ }\r
+ }\r
+ }\r
+\r
+ return xSecureContextHandle;\r
}\r
/*-----------------------------------------------------------*/\r
\r
secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle )\r
{\r
- uint32_t ulIPSR;\r
+ uint32_t ulIPSR;\r
\r
- /* Read the Interrupt Program Status Register (IPSR) value. */\r
- secureportREAD_IPSR( ulIPSR );\r
+ /* Read the Interrupt Program Status Register (IPSR) value. */\r
+ secureportREAD_IPSR( ulIPSR );\r
\r
- /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
- * when the processor is running in the Thread Mode. */\r
- if( ulIPSR != 0 )\r
- {\r
- /* Ensure that valid parameters are passed. */\r
- secureportASSERT( xSecureContextHandle != NULL );\r
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
+ * when the processor is running in the Thread Mode. */\r
+ if( ulIPSR != 0 )\r
+ {\r
+ /* Ensure that valid parameters are passed. */\r
+ secureportASSERT( xSecureContextHandle != NULL );\r
\r
- /* Free the stack space. */\r
- vPortFree( xSecureContextHandle->pucStackLimit );\r
+ /* Free the stack space. */\r
+ vPortFree( xSecureContextHandle->pucStackLimit );\r
\r
- /* Free the context itself. */\r
- vPortFree( xSecureContextHandle );\r
- }\r
+ /* Free the context itself. */\r
+ vPortFree( xSecureContextHandle );\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
/**\r
* @brief PSP value when no task's context is loaded.\r
*/\r
-#define securecontextNO_STACK 0x0\r
+#define securecontextNO_STACK 0x0\r
\r
/**\r
* @brief Opaque handle.\r
*/\r
struct SecureContext;\r
-typedef struct SecureContext* SecureContextHandle_t;\r
+typedef struct SecureContext* SecureContextHandle_t;\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* otherwise.\r
*/\r
#if( configENABLE_MPU == 1 )\r
- SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged );\r
+ SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged );\r
#else /* configENABLE_MPU */\r
- SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize );\r
+ SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize );\r
#endif /* configENABLE_MPU */\r
\r
/**\r
\r
secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )\r
{\r
- SecureContext_LoadContextAsm( xSecureContextHandle );\r
+ SecureContext_LoadContextAsm( xSecureContextHandle );\r
}\r
/*-----------------------------------------------------------*/\r
\r
secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )\r
{\r
- SecureContext_SaveContextAsm( xSecureContextHandle );\r
+ SecureContext_SaveContextAsm( xSecureContextHandle );\r
}\r
/*-----------------------------------------------------------*/\r
* 1 tab == 4 spaces!\r
*/\r
\r
- SECTION .text:CODE:NOROOT(2)\r
- THUMB\r
+ SECTION .text:CODE:NOROOT(2)\r
+ THUMB\r
\r
- PUBLIC SecureContext_LoadContextAsm\r
- PUBLIC SecureContext_SaveContextAsm\r
+ PUBLIC SecureContext_LoadContextAsm\r
+ PUBLIC SecureContext_SaveContextAsm\r
/*-----------------------------------------------------------*/\r
\r
SecureContext_LoadContextAsm:\r
- /* xSecureContextHandle value is in r0. */\r
- mrs r1, ipsr /* r1 = IPSR. */\r
- cbz r1, load_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */\r
- ldmia r0!, {r1, r2} /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */\r
+ /* xSecureContextHandle value is in r0. */\r
+ mrs r1, ipsr /* r1 = IPSR. */\r
+ cbz r1, load_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */\r
+ ldmia r0!, {r1, r2} /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */\r
#if ( configENABLE_MPU == 1 )\r
- ldmia r1!, {r3} /* Read CONTROL register value from task's stack. r3 = CONTROL. */\r
- msr control, r3 /* CONTROL = r3. */\r
+ ldmia r1!, {r3} /* Read CONTROL register value from task's stack. r3 = CONTROL. */\r
+ msr control, r3 /* CONTROL = r3. */\r
#endif /* configENABLE_MPU */\r
- msr psplim, r2 /* PSPLIM = r2. */\r
- msr psp, r1 /* PSP = r1. */\r
+ msr psplim, r2 /* PSPLIM = r2. */\r
+ msr psp, r1 /* PSP = r1. */\r
\r
- load_ctx_therad_mode:\r
- bx lr\r
+ load_ctx_therad_mode:\r
+ bx lr\r
/*-----------------------------------------------------------*/\r
\r
SecureContext_SaveContextAsm:\r
- /* xSecureContextHandle value is in r0. */\r
- mrs r1, ipsr /* r1 = IPSR. */\r
- cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */\r
- mrs r1, psp /* r1 = PSP. */\r
+ /* xSecureContextHandle value is in r0. */\r
+ mrs r1, ipsr /* r1 = IPSR. */\r
+ cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */\r
+ mrs r1, psp /* r1 = PSP. */\r
#if ( configENABLE_FPU == 1 )\r
- vstmdb r1!, {s0} /* Trigger the defferred stacking of FPU registers. */\r
- vldmia r1!, {s0} /* Nullify the effect of the pervious statement. */\r
+ vstmdb r1!, {s0} /* Trigger the defferred stacking of FPU registers. */\r
+ vldmia r1!, {s0} /* Nullify the effect of the pervious statement. */\r
#endif /* configENABLE_FPU */\r
#if ( configENABLE_MPU == 1 )\r
- mrs r2, control /* r2 = CONTROL. */\r
- stmdb r1!, {r2} /* Store CONTROL value on the stack. */\r
+ mrs r2, control /* r2 = CONTROL. */\r
+ stmdb r1!, {r2} /* Store CONTROL value on the stack. */\r
#endif /* configENABLE_MPU */\r
- str r1, [r0] /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */\r
- movs r1, #0 /* r1 = securecontextNO_STACK. */\r
- msr psplim, r1 /* PSPLIM = securecontextNO_STACK. */\r
- msr psp, r1 /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */\r
+ str r1, [r0] /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */\r
+ movs r1, #0 /* r1 = securecontextNO_STACK. */\r
+ msr psplim, r1 /* PSPLIM = securecontextNO_STACK. */\r
+ msr psp, r1 /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */\r
\r
- save_ctx_therad_mode:\r
- bx lr\r
+ save_ctx_therad_mode:\r
+ bx lr\r
/*-----------------------------------------------------------*/\r
\r
- END\r
+ END\r
/**\r
* @brief Total heap size.\r
*/\r
-#define secureconfigTOTAL_HEAP_SIZE ( ( ( size_t ) ( 10 * 1024 ) ) )\r
+#define secureconfigTOTAL_HEAP_SIZE ( ( ( size_t ) ( 10 * 1024 ) ) )\r
\r
/* No test marker by default. */\r
#ifndef mtCOVERAGE_TEST_MARKER\r
- #define mtCOVERAGE_TEST_MARKER()\r
+ #define mtCOVERAGE_TEST_MARKER()\r
#endif\r
\r
/* No tracing by default. */\r
#ifndef traceMALLOC\r
- #define traceMALLOC( pvReturn, xWantedSize )\r
+ #define traceMALLOC( pvReturn, xWantedSize )\r
#endif\r
\r
/* No tracing by default. */\r
#ifndef traceFREE\r
- #define traceFREE( pv, xBlockSize )\r
+ #define traceFREE( pv, xBlockSize )\r
#endif\r
\r
/* Block sizes must not get too small. */\r
-#define secureheapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) )\r
+#define secureheapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) )\r
\r
/* Assumes 8bit bytes! */\r
-#define secureheapBITS_PER_BYTE ( ( size_t ) 8 )\r
+#define secureheapBITS_PER_BYTE ( ( size_t ) 8 )\r
/*-----------------------------------------------------------*/\r
\r
/* Allocate the memory for the heap. */\r
#if( configAPPLICATION_ALLOCATED_HEAP == 1 )\r
- /* The application writer has already defined the array used for the RTOS\r
- * heap - probably so it can be placed in a special segment or address. */\r
- extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];\r
+ /* The application writer has already defined the array used for the RTOS\r
+ * heap - probably so it can be placed in a special segment or address. */\r
+ extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];\r
#else /* configAPPLICATION_ALLOCATED_HEAP */\r
- static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];\r
+ static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];\r
#endif /* configAPPLICATION_ALLOCATED_HEAP */\r
\r
/**\r
*/\r
typedef struct A_BLOCK_LINK\r
{\r
- struct A_BLOCK_LINK *pxNextFreeBlock; /**< The next free block in the list. */\r
- size_t xBlockSize; /**< The size of the free block. */\r
+ struct A_BLOCK_LINK *pxNextFreeBlock; /**< The next free block in the list. */\r
+ size_t xBlockSize; /**< The size of the free block. */\r
} BlockLink_t;\r
/*-----------------------------------------------------------*/\r
\r
size_t uxAddress;\r
size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;\r
\r
- /* Ensure the heap starts on a correctly aligned boundary. */\r
- uxAddress = ( size_t ) ucHeap;\r
-\r
- if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )\r
- {\r
- uxAddress += ( secureportBYTE_ALIGNMENT - 1 );\r
- uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\r
- xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;\r
- }\r
-\r
- pucAlignedHeap = ( uint8_t * ) uxAddress;\r
-\r
- /* xStart is used to hold a pointer to the first item in the list of free\r
- * blocks. The void cast is used to prevent compiler warnings. */\r
- xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;\r
- xStart.xBlockSize = ( size_t ) 0;\r
-\r
- /* pxEnd is used to mark the end of the list of free blocks and is inserted\r
- * at the end of the heap space. */\r
- uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;\r
- uxAddress -= xHeapStructSize;\r
- uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\r
- pxEnd = ( void * ) uxAddress;\r
- pxEnd->xBlockSize = 0;\r
- pxEnd->pxNextFreeBlock = NULL;\r
-\r
- /* To start with there is a single free block that is sized to take up the\r
- * entire heap space, minus the space taken by pxEnd. */\r
- pxFirstFreeBlock = ( void * ) pucAlignedHeap;\r
- pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;\r
- pxFirstFreeBlock->pxNextFreeBlock = pxEnd;\r
-\r
- /* Only one block exists - and it covers the entire usable heap space. */\r
- xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;\r
- xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;\r
-\r
- /* Work out the position of the top bit in a size_t variable. */\r
- xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );\r
+ /* Ensure the heap starts on a correctly aligned boundary. */\r
+ uxAddress = ( size_t ) ucHeap;\r
+\r
+ if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )\r
+ {\r
+ uxAddress += ( secureportBYTE_ALIGNMENT - 1 );\r
+ uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\r
+ xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;\r
+ }\r
+\r
+ pucAlignedHeap = ( uint8_t * ) uxAddress;\r
+\r
+ /* xStart is used to hold a pointer to the first item in the list of free\r
+ * blocks. The void cast is used to prevent compiler warnings. */\r
+ xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;\r
+ xStart.xBlockSize = ( size_t ) 0;\r
+\r
+ /* pxEnd is used to mark the end of the list of free blocks and is inserted\r
+ * at the end of the heap space. */\r
+ uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;\r
+ uxAddress -= xHeapStructSize;\r
+ uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );\r
+ pxEnd = ( void * ) uxAddress;\r
+ pxEnd->xBlockSize = 0;\r
+ pxEnd->pxNextFreeBlock = NULL;\r
+\r
+ /* To start with there is a single free block that is sized to take up the\r
+ * entire heap space, minus the space taken by pxEnd. */\r
+ pxFirstFreeBlock = ( void * ) pucAlignedHeap;\r
+ pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;\r
+ pxFirstFreeBlock->pxNextFreeBlock = pxEnd;\r
+\r
+ /* Only one block exists - and it covers the entire usable heap space. */\r
+ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;\r
+ xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;\r
+\r
+ /* Work out the position of the top bit in a size_t variable. */\r
+ xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );\r
}\r
/*-----------------------------------------------------------*/\r
\r
BlockLink_t *pxIterator;\r
uint8_t *puc;\r
\r
- /* Iterate through the list until a block is found that has a higher address\r
- * than the block being inserted. */\r
- for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )\r
- {\r
- /* Nothing to do here, just iterate to the right position. */\r
- }\r
-\r
- /* Do the block being inserted, and the block it is being inserted after\r
- * make a contiguous block of memory? */\r
- puc = ( uint8_t * ) pxIterator;\r
- if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )\r
- {\r
- pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;\r
- pxBlockToInsert = pxIterator;\r
- }\r
- else\r
- {\r
- mtCOVERAGE_TEST_MARKER();\r
- }\r
-\r
- /* Do the block being inserted, and the block it is being inserted before\r
- * make a contiguous block of memory? */\r
- puc = ( uint8_t * ) pxBlockToInsert;\r
- if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )\r
- {\r
- if( pxIterator->pxNextFreeBlock != pxEnd )\r
- {\r
- /* Form one big block from the two blocks. */\r
- pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;\r
- pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;\r
- }\r
- else\r
- {\r
- pxBlockToInsert->pxNextFreeBlock = pxEnd;\r
- }\r
- }\r
- else\r
- {\r
- pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;\r
- }\r
-\r
- /* If the block being inserted plugged a gab, so was merged with the block\r
- * before and the block after, then it's pxNextFreeBlock pointer will have\r
- * already been set, and should not be set here as that would make it point\r
- * to itself. */\r
- if( pxIterator != pxBlockToInsert )\r
- {\r
- pxIterator->pxNextFreeBlock = pxBlockToInsert;\r
- }\r
- else\r
- {\r
- mtCOVERAGE_TEST_MARKER();\r
- }\r
+ /* Iterate through the list until a block is found that has a higher address\r
+ * than the block being inserted. */\r
+ for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )\r
+ {\r
+ /* Nothing to do here, just iterate to the right position. */\r
+ }\r
+\r
+ /* Do the block being inserted, and the block it is being inserted after\r
+ * make a contiguous block of memory? */\r
+ puc = ( uint8_t * ) pxIterator;\r
+ if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )\r
+ {\r
+ pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;\r
+ pxBlockToInsert = pxIterator;\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+\r
+ /* Do the block being inserted, and the block it is being inserted before\r
+ * make a contiguous block of memory? */\r
+ puc = ( uint8_t * ) pxBlockToInsert;\r
+ if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )\r
+ {\r
+ if( pxIterator->pxNextFreeBlock != pxEnd )\r
+ {\r
+ /* Form one big block from the two blocks. */\r
+ pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;\r
+ pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;\r
+ }\r
+ else\r
+ {\r
+ pxBlockToInsert->pxNextFreeBlock = pxEnd;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;\r
+ }\r
+\r
+ /* If the block being inserted plugged a gab, so was merged with the block\r
+ * before and the block after, then it's pxNextFreeBlock pointer will have\r
+ * already been set, and should not be set here as that would make it point\r
+ * to itself. */\r
+ if( pxIterator != pxBlockToInsert )\r
+ {\r
+ pxIterator->pxNextFreeBlock = pxBlockToInsert;\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
\r
BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;\r
void *pvReturn = NULL;\r
\r
- /* If this is the first call to malloc then the heap will require\r
- * initialisation to setup the list of free blocks. */\r
- if( pxEnd == NULL )\r
- {\r
- prvHeapInit();\r
- }\r
- else\r
- {\r
- mtCOVERAGE_TEST_MARKER();\r
- }\r
-\r
- /* Check the requested block size is not so large that the top bit is set.\r
- * The top bit of the block size member of the BlockLink_t structure is used\r
- * to determine who owns the block - the application or the kernel, so it\r
- * must be free. */\r
- if( ( xWantedSize & xBlockAllocatedBit ) == 0 )\r
- {\r
- /* The wanted size is increased so it can contain a BlockLink_t\r
- * structure in addition to the requested amount of bytes. */\r
- if( xWantedSize > 0 )\r
- {\r
- xWantedSize += xHeapStructSize;\r
-\r
- /* Ensure that blocks are always aligned to the required number of\r
- * bytes. */\r
- if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )\r
- {\r
- /* Byte alignment required. */\r
- xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );\r
- secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );\r
- }\r
- else\r
- {\r
- mtCOVERAGE_TEST_MARKER();\r
- }\r
- }\r
- else\r
- {\r
- mtCOVERAGE_TEST_MARKER();\r
- }\r
-\r
- if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )\r
- {\r
- /* Traverse the list from the start (lowest address) block until\r
- * one of adequate size is found. */\r
- pxPreviousBlock = &xStart;\r
- pxBlock = xStart.pxNextFreeBlock;\r
- while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )\r
- {\r
- pxPreviousBlock = pxBlock;\r
- pxBlock = pxBlock->pxNextFreeBlock;\r
- }\r
-\r
- /* If the end marker was reached then a block of adequate size was\r
- * not found. */\r
- if( pxBlock != pxEnd )\r
- {\r
- /* Return the memory space pointed to - jumping over the\r
- * BlockLink_t structure at its start. */\r
- pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );\r
-\r
- /* This block is being returned for use so must be taken out\r
- * of the list of free blocks. */\r
- pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;\r
-\r
- /* If the block is larger than required it can be split into\r
- * two. */\r
- if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )\r
- {\r
- /* This block is to be split into two. Create a new\r
- * block following the number of bytes requested. The void\r
- * cast is used to prevent byte alignment warnings from the\r
- * compiler. */\r
- pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );\r
- secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );\r
-\r
- /* Calculate the sizes of two blocks split from the single\r
- * block. */\r
- pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;\r
- pxBlock->xBlockSize = xWantedSize;\r
-\r
- /* Insert the new block into the list of free blocks. */\r
- prvInsertBlockIntoFreeList( pxNewBlockLink );\r
- }\r
- else\r
- {\r
- mtCOVERAGE_TEST_MARKER();\r
- }\r
-\r
- xFreeBytesRemaining -= pxBlock->xBlockSize;\r
-\r
- if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )\r
- {\r
- xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;\r
- }\r
- else\r
- {\r
- mtCOVERAGE_TEST_MARKER();\r
- }\r
-\r
- /* The block is being returned - it is allocated and owned by\r
- * the application and has no "next" block. */\r
- pxBlock->xBlockSize |= xBlockAllocatedBit;\r
- pxBlock->pxNextFreeBlock = NULL;\r
- }\r
- else\r
- {\r
- mtCOVERAGE_TEST_MARKER();\r
- }\r
- }\r
- else\r
- {\r
- mtCOVERAGE_TEST_MARKER();\r
- }\r
- }\r
- else\r
- {\r
- mtCOVERAGE_TEST_MARKER();\r
- }\r
-\r
- traceMALLOC( pvReturn, xWantedSize );\r
-\r
- #if( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )\r
- {\r
- if( pvReturn == NULL )\r
- {\r
- extern void vApplicationMallocFailedHook( void );\r
- vApplicationMallocFailedHook();\r
- }\r
- else\r
- {\r
- mtCOVERAGE_TEST_MARKER();\r
- }\r
- }\r
- #endif\r
-\r
- secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );\r
- return pvReturn;\r
+ /* If this is the first call to malloc then the heap will require\r
+ * initialisation to setup the list of free blocks. */\r
+ if( pxEnd == NULL )\r
+ {\r
+ prvHeapInit();\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+\r
+ /* Check the requested block size is not so large that the top bit is set.\r
+ * The top bit of the block size member of the BlockLink_t structure is used\r
+ * to determine who owns the block - the application or the kernel, so it\r
+ * must be free. */\r
+ if( ( xWantedSize & xBlockAllocatedBit ) == 0 )\r
+ {\r
+ /* The wanted size is increased so it can contain a BlockLink_t\r
+ * structure in addition to the requested amount of bytes. */\r
+ if( xWantedSize > 0 )\r
+ {\r
+ xWantedSize += xHeapStructSize;\r
+\r
+ /* Ensure that blocks are always aligned to the required number of\r
+ * bytes. */\r
+ if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )\r
+ {\r
+ /* Byte alignment required. */\r
+ xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );\r
+ secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+\r
+ if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )\r
+ {\r
+ /* Traverse the list from the start (lowest address) block until\r
+ * one of adequate size is found. */\r
+ pxPreviousBlock = &xStart;\r
+ pxBlock = xStart.pxNextFreeBlock;\r
+ while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )\r
+ {\r
+ pxPreviousBlock = pxBlock;\r
+ pxBlock = pxBlock->pxNextFreeBlock;\r
+ }\r
+\r
+ /* If the end marker was reached then a block of adequate size was\r
+ * not found. */\r
+ if( pxBlock != pxEnd )\r
+ {\r
+ /* Return the memory space pointed to - jumping over the\r
+ * BlockLink_t structure at its start. */\r
+ pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );\r
+\r
+ /* This block is being returned for use so must be taken out\r
+ * of the list of free blocks. */\r
+ pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;\r
+\r
+ /* If the block is larger than required it can be split into\r
+ * two. */\r
+ if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )\r
+ {\r
+ /* This block is to be split into two. Create a new\r
+ * block following the number of bytes requested. The void\r
+ * cast is used to prevent byte alignment warnings from the\r
+ * compiler. */\r
+ pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );\r
+ secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );\r
+\r
+ /* Calculate the sizes of two blocks split from the single\r
+ * block. */\r
+ pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;\r
+ pxBlock->xBlockSize = xWantedSize;\r
+\r
+ /* Insert the new block into the list of free blocks. */\r
+ prvInsertBlockIntoFreeList( pxNewBlockLink );\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+\r
+ xFreeBytesRemaining -= pxBlock->xBlockSize;\r
+\r
+ if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )\r
+ {\r
+ xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+\r
+ /* The block is being returned - it is allocated and owned by\r
+ * the application and has no "next" block. */\r
+ pxBlock->xBlockSize |= xBlockAllocatedBit;\r
+ pxBlock->pxNextFreeBlock = NULL;\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+\r
+ traceMALLOC( pvReturn, xWantedSize );\r
+\r
+ #if( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )\r
+ {\r
+ if( pvReturn == NULL )\r
+ {\r
+ extern void vApplicationMallocFailedHook( void );\r
+ vApplicationMallocFailedHook();\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+ }\r
+ #endif\r
+\r
+ secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );\r
+ return pvReturn;\r
}\r
/*-----------------------------------------------------------*/\r
\r
uint8_t *puc = ( uint8_t * ) pv;\r
BlockLink_t *pxLink;\r
\r
- if( pv != NULL )\r
- {\r
- /* The memory being freed will have an BlockLink_t structure immediately\r
- * before it. */\r
- puc -= xHeapStructSize;\r
-\r
- /* This casting is to keep the compiler from issuing warnings. */\r
- pxLink = ( void * ) puc;\r
-\r
- /* Check the block is actually allocated. */\r
- secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );\r
- secureportASSERT( pxLink->pxNextFreeBlock == NULL );\r
-\r
- if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )\r
- {\r
- if( pxLink->pxNextFreeBlock == NULL )\r
- {\r
- /* The block is being returned to the heap - it is no longer\r
- * allocated. */\r
- pxLink->xBlockSize &= ~xBlockAllocatedBit;\r
-\r
- secureportDISABLE_NON_SECURE_INTERRUPTS();\r
- {\r
- /* Add this block to the list of free blocks. */\r
- xFreeBytesRemaining += pxLink->xBlockSize;\r
- traceFREE( pv, pxLink->xBlockSize );\r
- prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );\r
- }\r
- secureportENABLE_NON_SECURE_INTERRUPTS();\r
- }\r
- else\r
- {\r
- mtCOVERAGE_TEST_MARKER();\r
- }\r
- }\r
- else\r
- {\r
- mtCOVERAGE_TEST_MARKER();\r
- }\r
- }\r
+ if( pv != NULL )\r
+ {\r
+ /* The memory being freed will have an BlockLink_t structure immediately\r
+ * before it. */\r
+ puc -= xHeapStructSize;\r
+\r
+ /* This casting is to keep the compiler from issuing warnings. */\r
+ pxLink = ( void * ) puc;\r
+\r
+ /* Check the block is actually allocated. */\r
+ secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );\r
+ secureportASSERT( pxLink->pxNextFreeBlock == NULL );\r
+\r
+ if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )\r
+ {\r
+ if( pxLink->pxNextFreeBlock == NULL )\r
+ {\r
+ /* The block is being returned to the heap - it is no longer\r
+ * allocated. */\r
+ pxLink->xBlockSize &= ~xBlockAllocatedBit;\r
+\r
+ secureportDISABLE_NON_SECURE_INTERRUPTS();\r
+ {\r
+ /* Add this block to the list of free blocks. */\r
+ xFreeBytesRemaining += pxLink->xBlockSize;\r
+ traceFREE( pv, pxLink->xBlockSize );\r
+ prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );\r
+ }\r
+ secureportENABLE_NON_SECURE_INTERRUPTS();\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ mtCOVERAGE_TEST_MARKER();\r
+ }\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
\r
size_t xPortGetFreeHeapSize( void )\r
{\r
- return xFreeBytesRemaining;\r
+ return xFreeBytesRemaining;\r
}\r
/*-----------------------------------------------------------*/\r
\r
size_t xPortGetMinimumEverFreeHeapSize( void )\r
{\r
- return xMinimumEverFreeBytesRemaining;\r
+ return xMinimumEverFreeBytesRemaining;\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vPortInitialiseBlocks( void )\r
{\r
- /* This just exists to keep the linker quiet. */\r
+ /* This just exists to keep the linker quiet. */\r
}\r
/*-----------------------------------------------------------*/\r
/**\r
* @brief Constants required to manipulate the SCB.\r
*/\r
-#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */\r
-#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL )\r
-#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )\r
-#define secureinitSCB_AIRCR_PRIS_POS ( 14UL )\r
-#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS )\r
+#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */\r
+#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL )\r
+#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )\r
+#define secureinitSCB_AIRCR_PRIS_POS ( 14UL )\r
+#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS )\r
\r
/**\r
* @brief Constants required to manipulate the FPU.\r
*/\r
-#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */\r
-#define secureinitFPCCR_LSPENS_POS ( 29UL )\r
-#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS )\r
-#define secureinitFPCCR_TS_POS ( 26UL )\r
-#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS )\r
+#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */\r
+#define secureinitFPCCR_LSPENS_POS ( 29UL )\r
+#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS )\r
+#define secureinitFPCCR_TS_POS ( 26UL )\r
+#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS )\r
\r
-#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */\r
-#define secureinitNSACR_CP10_POS ( 10UL )\r
-#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS )\r
-#define secureinitNSACR_CP11_POS ( 11UL )\r
-#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS )\r
+#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */\r
+#define secureinitNSACR_CP10_POS ( 10UL )\r
+#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS )\r
+#define secureinitNSACR_CP11_POS ( 11UL )\r
+#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS )\r
/*-----------------------------------------------------------*/\r
\r
secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )\r
{\r
- uint32_t ulIPSR;\r
+ uint32_t ulIPSR;\r
\r
- /* Read the Interrupt Program Status Register (IPSR) value. */\r
- secureportREAD_IPSR( ulIPSR );\r
+ /* Read the Interrupt Program Status Register (IPSR) value. */\r
+ secureportREAD_IPSR( ulIPSR );\r
\r
- /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
- * when the processor is running in the Thread Mode. */\r
- if( ulIPSR != 0 )\r
- {\r
- *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |\r
- ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |\r
- ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK );\r
- }\r
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
+ * when the processor is running in the Thread Mode. */\r
+ if( ulIPSR != 0 )\r
+ {\r
+ *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |\r
+ ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |\r
+ ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK );\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
\r
secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )\r
{\r
- uint32_t ulIPSR;\r
+ uint32_t ulIPSR;\r
\r
- /* Read the Interrupt Program Status Register (IPSR) value. */\r
- secureportREAD_IPSR( ulIPSR );\r
+ /* Read the Interrupt Program Status Register (IPSR) value. */\r
+ secureportREAD_IPSR( ulIPSR );\r
\r
- /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
- * when the processor is running in the Thread Mode. */\r
- if( ulIPSR != 0 )\r
- {\r
- /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is\r
- * permitted. CP11 should be programmed to the same value as CP10. */\r
- *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );\r
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero\r
+ * when the processor is running in the Thread Mode. */\r
+ if( ulIPSR != 0 )\r
+ {\r
+ /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is\r
+ * permitted. CP11 should be programmed to the same value as CP10. */\r
+ *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );\r
\r
- /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures\r
- * that we can enable/disable lazy stacking in port.c file. */\r
- *( secureinitFPCCR ) &= ~ ( secureinitFPCCR_LSPENS_MASK );\r
+ /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures\r
+ * that we can enable/disable lazy stacking in port.c file. */\r
+ *( secureinitFPCCR ) &= ~ ( secureinitFPCCR_LSPENS_MASK );\r
\r
- /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP\r
- * registers (S16-S31) are also pushed to stack on exception entry and\r
- * restored on exception return. */\r
- *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );\r
- }\r
+ /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP\r
+ * registers (S16-S31) are also pushed to stack on exception entry and\r
+ * restored on exception return. */\r
+ *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
/**\r
* @brief Byte alignment requirements.\r
*/\r
-#define secureportBYTE_ALIGNMENT 8\r
-#define secureportBYTE_ALIGNMENT_MASK ( 0x0007 )\r
+#define secureportBYTE_ALIGNMENT 8\r
+#define secureportBYTE_ALIGNMENT_MASK ( 0x0007 )\r
\r
/**\r
* @brief Macro to declare a function as non-secure callable.\r
*/\r
#if defined( __IAR_SYSTEMS_ICC__ )\r
- #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry\r
+ #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry\r
#else\r
- #define secureportNON_SECURE_CALLABLE __attribute__((cmse_nonsecure_entry))\r
+ #define secureportNON_SECURE_CALLABLE __attribute__((cmse_nonsecure_entry))\r
#endif\r
\r
/**\r
* @brief Set the secure PRIMASK value.\r
*/\r
#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \\r
- __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )\r
+ __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )\r
\r
/**\r
* @brief Set the non-secure PRIMASK value.\r
*/\r
#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \\r
- __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )\r
+ __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )\r
\r
/**\r
* @brief Read the PSP value in the given variable.\r
*/\r
#define secureportREAD_PSP( pucOutCurrentStackPointer ) \\r
- __asm volatile ( "mrs %0, psp" : "=r" ( pucOutCurrentStackPointer ) )\r
+ __asm volatile ( "mrs %0, psp" : "=r" ( pucOutCurrentStackPointer ) )\r
\r
/**\r
* @brief Set the PSP to the given value.\r
*/\r
#define secureportSET_PSP( pucCurrentStackPointer ) \\r
- __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )\r
+ __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )\r
\r
/**\r
* @brief Set the PSPLIM to the given value.\r
*/\r
#define secureportSET_PSPLIM( pucStackLimit ) \\r
- __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )\r
+ __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )\r
\r
/**\r
* @brief Set the NonSecure MSP to the given value.\r
*/\r
#define secureportSET_MSP_NS( pucMainStackPointer ) \\r
- __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )\r
+ __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )\r
\r
/**\r
* @brief Set the CONTROL register to the given value.\r
*/\r
#define secureportSET_CONTROL( ulControl ) \\r
- __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )\r
+ __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )\r
\r
/**\r
* @brief Read the Interrupt Program Status Register (IPSR) value in the given\r
* variable.\r
*/\r
#define secureportREAD_IPSR( ulIPSR ) \\r
- __asm volatile ( "mrs %0, ipsr" : "=r" ( ulIPSR ) )\r
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulIPSR ) )\r
\r
/**\r
* @brief PRIMASK value to enable interrupts.\r
*/\r
-#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL 0\r
+#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL 0\r
\r
/**\r
* @brief PRIMASK value to disable interrupts.\r
*/\r
-#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL 1\r
+#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL 1\r
\r
/**\r
* @brief Disable secure interrupts.\r
*/\r
-#define secureportDISABLE_SECURE_INTERRUPTS() secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )\r
+#define secureportDISABLE_SECURE_INTERRUPTS() secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )\r
\r
/**\r
* @brief Disable non-secure interrupts.\r
*\r
* This effectively disables context switches.\r
*/\r
-#define secureportDISABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )\r
+#define secureportDISABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )\r
\r
/**\r
* @brief Enable non-secure interrupts.\r
*/\r
-#define secureportENABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )\r
+#define secureportENABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )\r
\r
/**\r
* @brief Assert definition.\r
*/\r
-#define secureportASSERT( x ) \\r
- if( ( x ) == 0 ) \\r
- { \\r
- secureportDISABLE_SECURE_INTERRUPTS(); \\r
- secureportDISABLE_NON_SECURE_INTERRUPTS(); \\r
- for( ;; ); \\r
- }\r
+#define secureportASSERT( x ) \\r
+ if( ( x ) == 0 ) \\r
+ { \\r
+ secureportDISABLE_SECURE_INTERRUPTS(); \\r
+ secureportDISABLE_NON_SECURE_INTERRUPTS(); \\r
+ for( ;; ); \\r
+ }\r
\r
#endif /* __SECURE_PORT_MACROS_H__ */\r
#include "portasm.h"\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
- /* Secure components includes. */\r
- #include "secure_context.h"\r
- #include "secure_init.h"\r
+ /* Secure components includes. */\r
+ #include "secure_context.h"\r
+ #include "secure_init.h"\r
#endif /* configENABLE_TRUSTZONE */\r
\r
#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
+/**\r
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only\r
+ * i.e. the processor boots as secure and never jumps to the non-secure side.\r
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS\r
+ * on the secure side. The following are the valid configuration seetings:\r
+ *\r
+ * 1. Run FreeRTOS on the Secure Side:\r
+ * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0\r
+ *\r
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:\r
+ * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1\r
+ *\r
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:\r
+ * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0\r
+ */\r
+#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )\r
+ #error Trust Zone needs to be disabled in order to run FreeRTOS on the Secure Side.\r
+#endif\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Constants required to manipulate the NVIC.\r
*/\r
-#define portNVIC_SYSTICK_CTRL ( ( volatile uint32_t * ) 0xe000e010 )\r
-#define portNVIC_SYSTICK_LOAD ( ( volatile uint32_t * ) 0xe000e014 )\r
-#define portNVIC_SYSTICK_CURRENT_VALUE ( ( volatile uint32_t * ) 0xe000e018 )\r
-#define portNVIC_INT_CTRL ( ( volatile uint32_t * ) 0xe000ed04 )\r
-#define portNVIC_SYSPRI2 ( ( volatile uint32_t * ) 0xe000ed20 )\r
-#define portNVIC_SYSTICK_CLK ( 0x00000004 )\r
-#define portNVIC_SYSTICK_INT ( 0x00000002 )\r
-#define portNVIC_SYSTICK_ENABLE ( 0x00000001 )\r
-#define portNVIC_PENDSVSET ( 0x10000000 )\r
-#define portMIN_INTERRUPT_PRIORITY ( 255UL )\r
-#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )\r
-#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )\r
+#define portNVIC_SYSTICK_CTRL ( ( volatile uint32_t * ) 0xe000e010 )\r
+#define portNVIC_SYSTICK_LOAD ( ( volatile uint32_t * ) 0xe000e014 )\r
+#define portNVIC_SYSTICK_CURRENT_VALUE ( ( volatile uint32_t * ) 0xe000e018 )\r
+#define portNVIC_INT_CTRL ( ( volatile uint32_t * ) 0xe000ed04 )\r
+#define portNVIC_SYSPRI2 ( ( volatile uint32_t * ) 0xe000ed20 )\r
+#define portNVIC_SYSTICK_CLK ( 0x00000004 )\r
+#define portNVIC_SYSTICK_INT ( 0x00000002 )\r
+#define portNVIC_SYSTICK_ENABLE ( 0x00000001 )\r
+#define portNVIC_PENDSVSET ( 0x10000000 )\r
+#define portMIN_INTERRUPT_PRIORITY ( 255UL )\r
+#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )\r
+#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Constants required to manipulate the SCB.\r
*/\r
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( * ( volatile uint32_t * ) 0xe000ed24 )\r
-#define portSCB_MEM_FAULT_ENABLE ( 1UL << 16UL )\r
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( * ( volatile uint32_t * ) 0xe000ed24 )\r
+#define portSCB_MEM_FAULT_ENABLE ( 1UL << 16UL )\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Constants required to manipulate the FPU.\r
*/\r
-#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */\r
-#define portCPACR_CP10_VALUE ( 3UL )\r
-#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE\r
-#define portCPACR_CP10_POS ( 20UL )\r
-#define portCPACR_CP11_POS ( 22UL )\r
-\r
-#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */\r
-#define portFPCCR_ASPEN_POS ( 31UL )\r
-#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS )\r
-#define portFPCCR_LSPEN_POS ( 30UL )\r
-#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS )\r
+#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */\r
+#define portCPACR_CP10_VALUE ( 3UL )\r
+#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE\r
+#define portCPACR_CP10_POS ( 20UL )\r
+#define portCPACR_CP11_POS ( 22UL )\r
+\r
+#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */\r
+#define portFPCCR_ASPEN_POS ( 31UL )\r
+#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS )\r
+#define portFPCCR_LSPEN_POS ( 30UL )\r
+#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS )\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Constants required to manipulate the MPU.\r
*/\r
-#define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )\r
-#define portMPU_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )\r
-#define portMPU_RNR_REG ( * ( ( volatile uint32_t * ) 0xe000ed98 ) )\r
+#define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )\r
+#define portMPU_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )\r
+#define portMPU_RNR_REG ( * ( ( volatile uint32_t * ) 0xe000ed98 ) )\r
\r
-#define portMPU_RBAR_REG ( * ( ( volatile uint32_t * ) 0xe000ed9c ) )\r
-#define portMPU_RLAR_REG ( * ( ( volatile uint32_t * ) 0xe000eda0 ) )\r
+#define portMPU_RBAR_REG ( * ( ( volatile uint32_t * ) 0xe000ed9c ) )\r
+#define portMPU_RLAR_REG ( * ( ( volatile uint32_t * ) 0xe000eda0 ) )\r
\r
-#define portMPU_RBAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda4 ) )\r
-#define portMPU_RLAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda8 ) )\r
+#define portMPU_RBAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda4 ) )\r
+#define portMPU_RLAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda8 ) )\r
\r
-#define portMPU_RBAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edac ) )\r
-#define portMPU_RLAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edb0 ) )\r
+#define portMPU_RBAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edac ) )\r
+#define portMPU_RLAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edb0 ) )\r
\r
-#define portMPU_RBAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb4 ) )\r
-#define portMPU_RLAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb8 ) )\r
+#define portMPU_RBAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb4 ) )\r
+#define portMPU_RLAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb8 ) )\r
\r
-#define portMPU_MAIR0_REG ( * ( ( volatile uint32_t * ) 0xe000edc0 ) )\r
-#define portMPU_MAIR1_REG ( * ( ( volatile uint32_t * ) 0xe000edc4 ) )\r
+#define portMPU_MAIR0_REG ( * ( ( volatile uint32_t * ) 0xe000edc0 ) )\r
+#define portMPU_MAIR1_REG ( * ( ( volatile uint32_t * ) 0xe000edc4 ) )\r
\r
-#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
-#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
+#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
+#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
\r
-#define portMPU_MAIR_ATTR0_POS ( 0UL )\r
-#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )\r
+#define portMPU_MAIR_ATTR0_POS ( 0UL )\r
+#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )\r
\r
-#define portMPU_MAIR_ATTR1_POS ( 8UL )\r
-#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )\r
+#define portMPU_MAIR_ATTR1_POS ( 8UL )\r
+#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )\r
\r
-#define portMPU_MAIR_ATTR2_POS ( 16UL )\r
-#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )\r
+#define portMPU_MAIR_ATTR2_POS ( 16UL )\r
+#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )\r
\r
-#define portMPU_MAIR_ATTR3_POS ( 24UL )\r
-#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )\r
+#define portMPU_MAIR_ATTR3_POS ( 24UL )\r
+#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )\r
\r
-#define portMPU_MAIR_ATTR4_POS ( 0UL )\r
-#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )\r
+#define portMPU_MAIR_ATTR4_POS ( 0UL )\r
+#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )\r
\r
-#define portMPU_MAIR_ATTR5_POS ( 8UL )\r
-#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )\r
+#define portMPU_MAIR_ATTR5_POS ( 8UL )\r
+#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )\r
\r
-#define portMPU_MAIR_ATTR6_POS ( 16UL )\r
-#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )\r
+#define portMPU_MAIR_ATTR6_POS ( 16UL )\r
+#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )\r
\r
-#define portMPU_MAIR_ATTR7_POS ( 24UL )\r
-#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )\r
+#define portMPU_MAIR_ATTR7_POS ( 24UL )\r
+#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )\r
\r
-#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )\r
-#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )\r
-#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )\r
-#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )\r
-#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )\r
-#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )\r
-#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )\r
-#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )\r
+#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )\r
\r
-#define portMPU_RLAR_REGION_ENABLE ( 1UL )\r
+#define portMPU_RLAR_REGION_ENABLE ( 1UL )\r
\r
/* Enable privileged access to unmapped region. */\r
-#define portMPU_PRIV_BACKGROUND_ENABLE ( 1UL << 2UL )\r
+#define portMPU_PRIV_BACKGROUND_ENABLE ( 1UL << 2UL )\r
\r
/* Enable MPU. */\r
-#define portMPU_ENABLE ( 1UL << 0UL )\r
+#define portMPU_ENABLE ( 1UL << 0UL )\r
\r
/* Expected value of the portMPU_TYPE register. */\r
-#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */\r
+#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Constants required to set up the initial stack.\r
*/\r
-#define portINITIAL_XPSR ( 0x01000000 )\r
-\r
-/**\r
- * @brief Initial EXC_RETURN value.\r
- *\r
- * FF FF FF BC\r
- * 1111 1111 1111 1111 1111 1111 1011 1100\r
- *\r
- * Bit[6] - 0 --> The exception was taken from the Non-Secure state.\r
- * Bit[5] - 1 --> Do not skip stacking of additional state context.\r
- * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\r
- * Bit[3] - 1 --> Return to the Thread mode.\r
- * Bit[2] - 1 --> Restore registers from the process stack.\r
- * Bit[1] - 0 --> Reserved, 0.\r
- * Bit[0] - 0 --> The exception was taken to the Non-Secure state.\r
- */\r
-#define portINITIAL_EXC_RETURN ( 0xffffffbc )\r
+#define portINITIAL_XPSR ( 0x01000000 )\r
+\r
+#if( configRUN_FREERTOS_SECURE_ONLY == 1 )\r
+ /**\r
+ * @brief Initial EXC_RETURN value.\r
+ *\r
+ * FF FF FF FD\r
+ * 1111 1111 1111 1111 1111 1111 1111 1101\r
+ *\r
+ * Bit[6] - 1 --> The exception was taken from the Secure state.\r
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.\r
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\r
+ * Bit[3] - 1 --> Return to the Thread mode.\r
+ * Bit[2] - 1 --> Restore registers from the process stack.\r
+ * Bit[1] - 0 --> Reserved, 0.\r
+ * Bit[0] - 1 --> The exception was taken to the Secure state.\r
+ */\r
+ #define portINITIAL_EXC_RETURN ( 0xfffffffd )\r
+#else\r
+ /**\r
+ * @brief Initial EXC_RETURN value.\r
+ *\r
+ * FF FF FF BC\r
+ * 1111 1111 1111 1111 1111 1111 1011 1100\r
+ *\r
+ * Bit[6] - 0 --> The exception was taken from the Non-Secure state.\r
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.\r
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\r
+ * Bit[3] - 1 --> Return to the Thread mode.\r
+ * Bit[2] - 1 --> Restore registers from the process stack.\r
+ * Bit[1] - 0 --> Reserved, 0.\r
+ * Bit[0] - 0 --> The exception was taken to the Non-Secure state.\r
+ */\r
+ #define portINITIAL_EXC_RETURN ( 0xffffffbc )\r
+#endif /* configRUN_FREERTOS_SECURE_ONLY */\r
\r
/**\r
* @brief CONTROL register privileged bit mask.\r
* Bit[0] = 0 ==> The task is privileged.\r
* Bit[0] = 1 ==> The task is not privileged.\r
*/\r
-#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL )\r
+#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL )\r
\r
/**\r
* @brief Initial CONTROL register values.\r
*/\r
-#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 )\r
-#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 )\r
+#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 )\r
+#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 )\r
\r
/**\r
* @brief Let the user override the pre-loading of the initial LR with the\r
* in the debugger.\r
*/\r
#ifdef configTASK_RETURN_ADDRESS\r
- #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS\r
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS\r
#else\r
- #define portTASK_RETURN_ADDRESS prvTaskExitError\r
+ #define portTASK_RETURN_ADDRESS prvTaskExitError\r
#endif\r
\r
/**\r
* @brief If portPRELOAD_REGISTERS then registers will be given an initial value\r
* when a task is created. This helps in debugging at the cost of code size.\r
*/\r
-#define portPRELOAD_REGISTERS 1\r
+#define portPRELOAD_REGISTERS 1\r
\r
/**\r
* @brief A task is created without a secure context, and must call\r
* portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes\r
* any secure calls.\r
*/\r
-#define portNO_SECURE_CONTEXT 0\r
+#define portNO_SECURE_CONTEXT 0\r
/*-----------------------------------------------------------*/\r
\r
/**\r
static void prvTaskExitError( void );\r
\r
#if( configENABLE_MPU == 1 )\r
- /**\r
- * @brief Setup the Memory Protection Unit (MPU).\r
- */\r
- static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\r
+ /**\r
+ * @brief Setup the Memory Protection Unit (MPU).\r
+ */\r
+ static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\r
#endif /* configENABLE_MPU */\r
\r
#if( configENABLE_FPU == 1 )\r
- /**\r
- * @brief Setup the Floating Point Unit (FPU).\r
- */\r
- static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\r
+ /**\r
+ * @brief Setup the Floating Point Unit (FPU).\r
+ */\r
+ static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\r
#endif /* configENABLE_FPU */\r
\r
/**\r
static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
- /**\r
- * @brief Saved as part of the task context to indicate which context the\r
- * task is using on the secure side.\r
- */\r
- volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\r
+ /**\r
+ * @brief Saved as part of the task context to indicate which context the\r
+ * task is using on the secure side.\r
+ */\r
+ volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\r
#endif /* configENABLE_TRUSTZONE */\r
/*-----------------------------------------------------------*/\r
\r
static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\r
{\r
- /* Stop and reset the SysTick. */\r
- *( portNVIC_SYSTICK_CTRL ) = 0UL;\r
- *( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;\r
+ /* Stop and reset the SysTick. */\r
+ *( portNVIC_SYSTICK_CTRL ) = 0UL;\r
+ *( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;\r
\r
- /* Configure SysTick to interrupt at the requested rate. */\r
- *( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
- *( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
+ /* Configure SysTick to interrupt at the requested rate. */\r
+ *( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
+ *( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
}\r
/*-----------------------------------------------------------*/\r
\r
{\r
volatile uint32_t ulDummy = 0UL;\r
\r
- /* A function that implements a task must not exit or attempt to return to\r
- * its caller as there is nothing to return to. If a task wants to exit it\r
- * should instead call vTaskDelete( NULL ). Artificially force an assert()\r
- * to be triggered if configASSERT() is defined, then stop here so\r
- * application writers can catch the error. */\r
- configASSERT( ulCriticalNesting == ~0UL );\r
- portDISABLE_INTERRUPTS();\r
-\r
- while( ulDummy == 0 )\r
- {\r
- /* This file calls prvTaskExitError() after the scheduler has been\r
- * started to remove a compiler warning about the function being\r
- * defined but never called. ulDummy is used purely to quieten other\r
- * warnings about code appearing after this function is called - making\r
- * ulDummy volatile makes the compiler think the function could return\r
- * and therefore not output an 'unreachable code' warning for code that\r
- * appears after it. */\r
- }\r
+ /* A function that implements a task must not exit or attempt to return to\r
+ * its caller as there is nothing to return to. If a task wants to exit it\r
+ * should instead call vTaskDelete( NULL ). Artificially force an assert()\r
+ * to be triggered if configASSERT() is defined, then stop here so\r
+ * application writers can catch the error. */\r
+ configASSERT( ulCriticalNesting == ~0UL );\r
+ portDISABLE_INTERRUPTS();\r
+\r
+ while( ulDummy == 0 )\r
+ {\r
+ /* This file calls prvTaskExitError() after the scheduler has been\r
+ * started to remove a compiler warning about the function being\r
+ * defined but never called. ulDummy is used purely to quieten other\r
+ * warnings about code appearing after this function is called - making\r
+ * ulDummy volatile makes the compiler think the function could return\r
+ * and therefore not output an 'unreachable code' warning for code that\r
+ * appears after it. */\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
\r
#if( configENABLE_MPU == 1 )\r
- static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */\r
- {\r
- #if defined( __ARMCC_VERSION )\r
- /* Declaration when these variable are defined in code instead of being\r
- * exported from linker scripts. */\r
- extern uint32_t * __privileged_functions_start__;\r
- extern uint32_t * __privileged_functions_end__;\r
- extern uint32_t * __syscalls_flash_start__;\r
- extern uint32_t * __unprivileged_flash_end__;\r
- extern uint32_t * __privileged_sram_start__;\r
- extern uint32_t * __privileged_sram_end__;\r
- #else\r
- /* Declaration when these variable are exported from linker scripts. */\r
- extern uint32_t __privileged_functions_start__[];\r
- extern uint32_t __privileged_functions_end__[];\r
- extern uint32_t __syscalls_flash_start__[];\r
- extern uint32_t __unprivileged_flash_end__[];\r
- extern uint32_t __privileged_sram_start__[];\r
- extern uint32_t __privileged_sram_end__[];\r
- #endif /* defined( __ARMCC_VERSION ) */\r
-\r
- /* Check that the MPU is present. */\r
- if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\r
- {\r
- /* MAIR0 - Index 0. */\r
- portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
- /* MAIR0 - Index 1. */\r
- portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
-\r
- /* Setup privileged flash as Read Only so that privileged tasks can\r
- * read it but not modify. */\r
- portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;\r
- portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
- ( portMPU_REGION_NON_SHAREABLE ) |\r
- ( portMPU_REGION_PRIVILEGED_READ_ONLY );\r
- portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
- ( portMPU_RLAR_ATTR_INDEX0 ) |\r
- ( portMPU_RLAR_REGION_ENABLE );\r
-\r
- /* Setup unprivileged flash and system calls flash as Read Only by\r
- * both privileged and unprivileged tasks. All tasks can read it but\r
- * no-one can modify. */\r
- portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;\r
- portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
- ( portMPU_REGION_NON_SHAREABLE ) |\r
- ( portMPU_REGION_READ_ONLY );\r
- portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
- ( portMPU_RLAR_ATTR_INDEX0 ) |\r
- ( portMPU_RLAR_REGION_ENABLE );\r
-\r
- /* Setup RAM containing kernel data for privileged access only. */\r
- portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;\r
- portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
- ( portMPU_REGION_NON_SHAREABLE ) |\r
- ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
- ( portMPU_REGION_EXECUTE_NEVER );\r
- portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
- ( portMPU_RLAR_ATTR_INDEX0 ) |\r
- ( portMPU_RLAR_REGION_ENABLE );\r
-\r
- /* By default allow everything to access the general peripherals.\r
- * The system peripherals and registers are protected. */\r
- portMPU_RNR_REG = portUNPRIVILEGED_DEVICE_REGION;\r
- portMPU_RBAR_REG = ( ( ( uint32_t ) portDEVICE_REGION_START_ADDRESS ) & portMPU_RBAR_ADDRESS_MASK ) |\r
- ( portMPU_REGION_NON_SHAREABLE ) |\r
- ( portMPU_REGION_READ_WRITE ) |\r
- ( portMPU_REGION_EXECUTE_NEVER );\r
- portMPU_RLAR_REG = ( ( ( uint32_t ) portDEVICE_REGION_END_ADDRESS ) & portMPU_RLAR_ADDRESS_MASK ) |\r
- ( portMPU_RLAR_ATTR_INDEX1 ) |\r
- ( portMPU_RLAR_REGION_ENABLE );\r
-\r
- /* Enable mem fault. */\r
- portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;\r
-\r
- /* Enable MPU with privileged background access i.e. unmapped\r
- * regions have privileged access. */\r
- portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );\r
- }\r
- }\r
+ static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */\r
+ {\r
+ #if defined( __ARMCC_VERSION )\r
+ /* Declaration when these variable are defined in code instead of being\r
+ * exported from linker scripts. */\r
+ extern uint32_t * __privileged_functions_start__;\r
+ extern uint32_t * __privileged_functions_end__;\r
+ extern uint32_t * __syscalls_flash_start__;\r
+ extern uint32_t * __unprivileged_flash_end__;\r
+ extern uint32_t * __privileged_sram_start__;\r
+ extern uint32_t * __privileged_sram_end__;\r
+ #else\r
+ /* Declaration when these variable are exported from linker scripts. */\r
+ extern uint32_t __privileged_functions_start__[];\r
+ extern uint32_t __privileged_functions_end__[];\r
+ extern uint32_t __syscalls_flash_start__[];\r
+ extern uint32_t __unprivileged_flash_end__[];\r
+ extern uint32_t __privileged_sram_start__[];\r
+ extern uint32_t __privileged_sram_end__[];\r
+ #endif /* defined( __ARMCC_VERSION ) */\r
+\r
+ /* Check that the MPU is present. */\r
+ if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\r
+ {\r
+ /* MAIR0 - Index 0. */\r
+ portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
+ /* MAIR0 - Index 1. */\r
+ portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
+\r
+ /* Setup privileged flash as Read Only so that privileged tasks can\r
+ * read it but not modify. */\r
+ portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_PRIVILEGED_READ_ONLY );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Setup unprivileged flash and system calls flash as Read Only by\r
+ * both privileged and unprivileged tasks. All tasks can read it but\r
+ * no-one can modify. */\r
+ portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_ONLY );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Setup RAM containing kernel data for privileged access only. */\r
+ portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
+ ( portMPU_REGION_EXECUTE_NEVER );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* By default allow everything to access the general peripherals.\r
+ * The system peripherals and registers are protected. */\r
+ portMPU_RNR_REG = portUNPRIVILEGED_DEVICE_REGION;\r
+ portMPU_RBAR_REG = ( ( ( uint32_t ) portDEVICE_REGION_START_ADDRESS ) & portMPU_RBAR_ADDRESS_MASK ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_WRITE ) |\r
+ ( portMPU_REGION_EXECUTE_NEVER );\r
+ portMPU_RLAR_REG = ( ( ( uint32_t ) portDEVICE_REGION_END_ADDRESS ) & portMPU_RLAR_ADDRESS_MASK ) |\r
+ ( portMPU_RLAR_ATTR_INDEX1 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Enable mem fault. */\r
+ portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;\r
+\r
+ /* Enable MPU with privileged background access i.e. unmapped\r
+ * regions have privileged access. */\r
+ portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );\r
+ }\r
+ }\r
#endif /* configENABLE_MPU */\r
/*-----------------------------------------------------------*/\r
\r
#if( configENABLE_FPU == 1 )\r
- static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */\r
- {\r
- #if( configENABLE_TRUSTZONE == 1 )\r
- {\r
- /* Enable non-secure access to the FPU. */\r
- SecureInit_EnableNSFPUAccess();\r
- }\r
- #endif /* configENABLE_TRUSTZONE */\r
-\r
- /* CP10 = 11 ==> Full access to FPU i.e. both privileged and\r
- * unprivileged code should be able to access FPU. CP11 should be\r
- * programmed to the same value as CP10. */\r
- *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |\r
- ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )\r
- );\r
-\r
- /* ASPEN = 1 ==> Hardware should automatically preserve floating point\r
- * context on exception entry and restore on exception return.\r
- * LSPEN = 1 ==> Enable lazy context save of FP state. */\r
- *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );\r
- }\r
+ static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */\r
+ {\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ /* Enable non-secure access to the FPU. */\r
+ SecureInit_EnableNSFPUAccess();\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+\r
+ /* CP10 = 11 ==> Full access to FPU i.e. both privileged and\r
+ * unprivileged code should be able to access FPU. CP11 should be\r
+ * programmed to the same value as CP10. */\r
+ *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |\r
+ ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )\r
+ );\r
+\r
+ /* ASPEN = 1 ==> Hardware should automatically preserve floating point\r
+ * context on exception entry and restore on exception return.\r
+ * LSPEN = 1 ==> Enable lazy context save of FP state. */\r
+ *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );\r
+ }\r
#endif /* configENABLE_FPU */\r
/*-----------------------------------------------------------*/\r
\r
void vPortYield( void ) /* PRIVILEGED_FUNCTION */\r
{\r
- /* Set a PendSV to request a context switch. */\r
- *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
+ /* Set a PendSV to request a context switch. */\r
+ *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
\r
- /* Barriers are normally not required but do ensure the code is\r
- * completely within the specified behaviour for the architecture. */\r
- __asm volatile( "dsb" ::: "memory" );\r
- __asm volatile( "isb" );\r
+ /* Barriers are normally not required but do ensure the code is\r
+ * completely within the specified behaviour for the architecture. */\r
+ __asm volatile( "dsb" ::: "memory" );\r
+ __asm volatile( "isb" );\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */\r
{\r
- portDISABLE_INTERRUPTS();\r
- ulCriticalNesting++;\r
+ portDISABLE_INTERRUPTS();\r
+ ulCriticalNesting++;\r
\r
- /* Barriers are normally not required but do ensure the code is\r
- * completely within the specified behaviour for the architecture. */\r
- __asm volatile( "dsb" ::: "memory" );\r
- __asm volatile( "isb" );\r
+ /* Barriers are normally not required but do ensure the code is\r
+ * completely within the specified behaviour for the architecture. */\r
+ __asm volatile( "dsb" ::: "memory" );\r
+ __asm volatile( "isb" );\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */\r
{\r
- configASSERT( ulCriticalNesting );\r
- ulCriticalNesting--;\r
+ configASSERT( ulCriticalNesting );\r
+ ulCriticalNesting--;\r
\r
- if( ulCriticalNesting == 0 )\r
- {\r
- portENABLE_INTERRUPTS();\r
- }\r
+ if( ulCriticalNesting == 0 )\r
+ {\r
+ portENABLE_INTERRUPTS();\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
\r
{\r
uint32_t ulPreviousMask;\r
\r
- ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();\r
- {\r
- /* Increment the RTOS tick. */\r
- if( xTaskIncrementTick() != pdFALSE )\r
- {\r
- /* Pend a context switch. */\r
- *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
- }\r
- }\r
- portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );\r
+ ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();\r
+ {\r
+ /* Increment the RTOS tick. */\r
+ if( xTaskIncrementTick() != pdFALSE )\r
+ {\r
+ /* Pend a context switch. */\r
+ *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
+ }\r
+ }\r
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION */\r
{\r
#if( configENABLE_MPU == 1 )\r
- #if defined( __ARMCC_VERSION )\r
- /* Declaration when these variable are defined in code instead of being\r
- * exported from linker scripts. */\r
- extern uint32_t * __syscalls_flash_start__;\r
- extern uint32_t * __syscalls_flash_end__;\r
- #else\r
- /* Declaration when these variable are exported from linker scripts. */\r
- extern uint32_t __syscalls_flash_start__[];\r
- extern uint32_t __syscalls_flash_end__[];\r
- #endif /* defined( __ARMCC_VERSION ) */\r
+ #if defined( __ARMCC_VERSION )\r
+ /* Declaration when these variable are defined in code instead of being\r
+ * exported from linker scripts. */\r
+ extern uint32_t * __syscalls_flash_start__;\r
+ extern uint32_t * __syscalls_flash_end__;\r
+ #else\r
+ /* Declaration when these variable are exported from linker scripts. */\r
+ extern uint32_t __syscalls_flash_start__[];\r
+ extern uint32_t __syscalls_flash_end__[];\r
+ #endif /* defined( __ARMCC_VERSION ) */\r
#endif /* configENABLE_MPU */\r
\r
uint32_t ulPC;\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
- uint32_t ulR0;\r
- #if( configENABLE_MPU == 1 )\r
- uint32_t ulControl, ulIsTaskPrivileged;\r
- #endif /* configENABLE_MPU */\r
+ uint32_t ulR0;\r
+ #if( configENABLE_MPU == 1 )\r
+ uint32_t ulControl, ulIsTaskPrivileged;\r
+ #endif /* configENABLE_MPU */\r
#endif /* configENABLE_TRUSTZONE */\r
uint8_t ucSVCNumber;\r
\r
- /* Register are stored on the stack in the following order - R0, R1, R2, R3,\r
- * R12, LR, PC, xPSR. */\r
- ulPC = pulCallerStackAddress[ 6 ];\r
- ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];\r
-\r
- switch( ucSVCNumber )\r
- {\r
- #if( configENABLE_TRUSTZONE == 1 )\r
- case portSVC_ALLOCATE_SECURE_CONTEXT:\r
- {\r
- /* R0 contains the stack size passed as parameter to the\r
- * vPortAllocateSecureContext function. */\r
- ulR0 = pulCallerStackAddress[ 0 ];\r
-\r
- #if( configENABLE_MPU == 1 )\r
- {\r
- /* Read the CONTROL register value. */\r
- __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );\r
-\r
- /* The task that raised the SVC is privileged if Bit[0]\r
- * in the CONTROL register is 0. */\r
- ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );\r
-\r
- /* Allocate and load a context for the secure task. */\r
- xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );\r
- }\r
- #else\r
- {\r
- /* Allocate and load a context for the secure task. */\r
- xSecureContext = SecureContext_AllocateContext( ulR0 );\r
- }\r
- #endif /* configENABLE_MPU */\r
-\r
- configASSERT( xSecureContext != NULL );\r
- SecureContext_LoadContext( xSecureContext );\r
- }\r
- break;\r
-\r
- case portSVC_FREE_SECURE_CONTEXT:\r
- {\r
- /* R0 contains the secure context handle to be freed. */\r
- ulR0 = pulCallerStackAddress[ 0 ];\r
-\r
- /* Free the secure context. */\r
- SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );\r
- }\r
- break;\r
- #endif /* configENABLE_TRUSTZONE */\r
-\r
- case portSVC_START_SCHEDULER:\r
- {\r
- #if( configENABLE_TRUSTZONE == 1 )\r
- {\r
- /* De-prioritize the non-secure exceptions so that the\r
- * non-secure pendSV runs at the lowest priority. */\r
- SecureInit_DePrioritizeNSExceptions();\r
-\r
- /* Initialize the secure context management system. */\r
- SecureContext_Init();\r
- }\r
- #endif /* configENABLE_TRUSTZONE */\r
-\r
- #if( configENABLE_FPU == 1 )\r
- {\r
- /* Setup the Floating Point Unit (FPU). */\r
- prvSetupFPU();\r
- }\r
- #endif /* configENABLE_FPU */\r
-\r
- /* Setup the context of the first task so that the first task starts\r
- * executing. */\r
- vRestoreContextOfFirstTask();\r
- }\r
- break;\r
-\r
- #if( configENABLE_MPU == 1 )\r
- case portSVC_RAISE_PRIVILEGE:\r
- {\r
- /* Only raise the privilege, if the svc was raised from any of\r
- * the system calls. */\r
- if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&\r
- ulPC <= ( uint32_t ) __syscalls_flash_end__ )\r
- {\r
- vRaisePrivilege();\r
- }\r
- }\r
- break;\r
- #endif /* configENABLE_MPU */\r
-\r
- default:\r
- {\r
- /* Incorrect SVC call. */\r
- configASSERT( pdFALSE );\r
- }\r
- }\r
+ /* Register are stored on the stack in the following order - R0, R1, R2, R3,\r
+ * R12, LR, PC, xPSR. */\r
+ ulPC = pulCallerStackAddress[ 6 ];\r
+ ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];\r
+\r
+ switch( ucSVCNumber )\r
+ {\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ case portSVC_ALLOCATE_SECURE_CONTEXT:\r
+ {\r
+ /* R0 contains the stack size passed as parameter to the\r
+ * vPortAllocateSecureContext function. */\r
+ ulR0 = pulCallerStackAddress[ 0 ];\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ /* Read the CONTROL register value. */\r
+ __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );\r
+\r
+ /* The task that raised the SVC is privileged if Bit[0]\r
+ * in the CONTROL register is 0. */\r
+ ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );\r
+\r
+ /* Allocate and load a context for the secure task. */\r
+ xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );\r
+ }\r
+ #else\r
+ {\r
+ /* Allocate and load a context for the secure task. */\r
+ xSecureContext = SecureContext_AllocateContext( ulR0 );\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ configASSERT( xSecureContext != NULL );\r
+ SecureContext_LoadContext( xSecureContext );\r
+ }\r
+ break;\r
+\r
+ case portSVC_FREE_SECURE_CONTEXT:\r
+ {\r
+ /* R0 contains the secure context handle to be freed. */\r
+ ulR0 = pulCallerStackAddress[ 0 ];\r
+\r
+ /* Free the secure context. */\r
+ SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );\r
+ }\r
+ break;\r
+ #endif /* configENABLE_TRUSTZONE */\r
+\r
+ case portSVC_START_SCHEDULER:\r
+ {\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ /* De-prioritize the non-secure exceptions so that the\r
+ * non-secure pendSV runs at the lowest priority. */\r
+ SecureInit_DePrioritizeNSExceptions();\r
+\r
+ /* Initialize the secure context management system. */\r
+ SecureContext_Init();\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+\r
+ #if( configENABLE_FPU == 1 )\r
+ {\r
+ /* Setup the Floating Point Unit (FPU). */\r
+ prvSetupFPU();\r
+ }\r
+ #endif /* configENABLE_FPU */\r
+\r
+ /* Setup the context of the first task so that the first task starts\r
+ * executing. */\r
+ vRestoreContextOfFirstTask();\r
+ }\r
+ break;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ case portSVC_RAISE_PRIVILEGE:\r
+ {\r
+ /* Only raise the privilege, if the svc was raised from any of\r
+ * the system calls. */\r
+ if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&\r
+ ulPC <= ( uint32_t ) __syscalls_flash_end__ )\r
+ {\r
+ vRaisePrivilege();\r
+ }\r
+ }\r
+ break;\r
+ #endif /* configENABLE_MPU */\r
+\r
+ default:\r
+ {\r
+ /* Incorrect SVC call. */\r
+ configASSERT( pdFALSE );\r
+ }\r
+ }\r
}\r
/*-----------------------------------------------------------*/\r
\r
#if( configENABLE_MPU == 1 )\r
- StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */\r
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */\r
#else\r
- StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */\r
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */\r
#endif /* configENABLE_MPU */\r
{\r
- /* Simulate the stack frame as it would be created by a context switch\r
- * interrupt. */\r
- #if( portPRELOAD_REGISTERS == 0 )\r
- {\r
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
- *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\r
- pxTopOfStack -= 5; /* R12, R3, R2 and R1. */\r
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
- pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */\r
- *pxTopOfStack = portINITIAL_EXC_RETURN;\r
-\r
- #if( configENABLE_MPU == 1 )\r
- {\r
- pxTopOfStack--;\r
- if( xRunPrivileged == pdTRUE )\r
- {\r
- *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
- }\r
- else\r
- {\r
- *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
- }\r
- }\r
- #endif /* configENABLE_MPU */\r
-\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\r
-\r
- #if( configENABLE_TRUSTZONE == 1 )\r
- {\r
- pxTopOfStack--;\r
- *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\r
- }\r
- #endif /* configENABLE_TRUSTZONE */\r
- }\r
- #else /* portPRELOAD_REGISTERS */\r
- {\r
- pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
- *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */\r
- pxTopOfStack--;\r
- *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */\r
-\r
- #if( configENABLE_MPU == 1 )\r
- {\r
- pxTopOfStack--;\r
- if( xRunPrivileged == pdTRUE )\r
- {\r
- *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
- }\r
- else\r
- {\r
- *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
- }\r
- }\r
- #endif /* configENABLE_MPU */\r
-\r
- pxTopOfStack--;\r
- *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\r
-\r
- #if( configENABLE_TRUSTZONE == 1 )\r
- {\r
- pxTopOfStack--;\r
- *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\r
- }\r
- #endif /* configENABLE_TRUSTZONE */\r
- }\r
- #endif /* portPRELOAD_REGISTERS */\r
-\r
- return pxTopOfStack;\r
+ /* Simulate the stack frame as it would be created by a context switch\r
+ * interrupt. */\r
+ #if( portPRELOAD_REGISTERS == 0 )\r
+ {\r
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\r
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */\r
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
+ pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */\r
+ *pxTopOfStack = portINITIAL_EXC_RETURN;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ if( xRunPrivileged == pdTRUE )\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ else\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\r
+\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+ }\r
+ #else /* portPRELOAD_REGISTERS */\r
+ {\r
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ if( xRunPrivileged == pdTRUE )\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ else\r
+ {\r
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */\r
+ }\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */\r
+\r
+ #if( configENABLE_TRUSTZONE == 1 )\r
+ {\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */\r
+ }\r
+ #endif /* configENABLE_TRUSTZONE */\r
+ }\r
+ #endif /* portPRELOAD_REGISTERS */\r
+\r
+ return pxTopOfStack;\r
}\r
/*-----------------------------------------------------------*/\r
\r
BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */\r
{\r
- /* Make PendSV, CallSV and SysTick the same priority as the kernel. */\r
- *( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;\r
- *( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;\r
-\r
- #if( configENABLE_MPU == 1 )\r
- {\r
- /* Setup the Memory Protection Unit (MPU). */\r
- prvSetupMPU();\r
- }\r
- #endif /* configENABLE_MPU */\r
-\r
- /* Start the timer that generates the tick ISR. Interrupts are disabled\r
- * here already. */\r
- prvSetupTimerInterrupt();\r
-\r
- /* Initialize the critical nesting count ready for the first task. */\r
- ulCriticalNesting = 0;\r
-\r
- /* Start the first task. */\r
- vStartFirstTask();\r
-\r
- /* Should never get here as the tasks will now be executing. Call the task\r
- * exit error function to prevent compiler warnings about a static function\r
- * not being called in the case that the application writer overrides this\r
- * functionality by defining configTASK_RETURN_ADDRESS. Call\r
- * vTaskSwitchContext() so link time optimization does not remove the\r
- * symbol. */\r
- vTaskSwitchContext();\r
- prvTaskExitError();\r
-\r
- /* Should not get here. */\r
- return 0;\r
+ /* Make PendSV, CallSV and SysTick the same priority as the kernel. */\r
+ *( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;\r
+ *( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;\r
+\r
+ #if( configENABLE_MPU == 1 )\r
+ {\r
+ /* Setup the Memory Protection Unit (MPU). */\r
+ prvSetupMPU();\r
+ }\r
+ #endif /* configENABLE_MPU */\r
+\r
+ /* Start the timer that generates the tick ISR. Interrupts are disabled\r
+ * here already. */\r
+ prvSetupTimerInterrupt();\r
+\r
+ /* Initialize the critical nesting count ready for the first task. */\r
+ ulCriticalNesting = 0;\r
+\r
+ /* Start the first task. */\r
+ vStartFirstTask();\r
+\r
+ /* Should never get here as the tasks will now be executing. Call the task\r
+ * exit error function to prevent compiler warnings about a static function\r
+ * not being called in the case that the application writer overrides this\r
+ * functionality by defining configTASK_RETURN_ADDRESS. Call\r
+ * vTaskSwitchContext() so link time optimization does not remove the\r
+ * symbol. */\r
+ vTaskSwitchContext();\r
+ prvTaskExitError();\r
+\r
+ /* Should not get here. */\r
+ return 0;\r
}\r
/*-----------------------------------------------------------*/\r
\r
void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */\r
{\r
- /* Not implemented in ports where there is nothing to return to.\r
- * Artificially force an assert. */\r
- configASSERT( ulCriticalNesting == 1000UL );\r
+ /* Not implemented in ports where there is nothing to return to.\r
+ * Artificially force an assert. */\r
+ configASSERT( ulCriticalNesting == 1000UL );\r
}\r
/*-----------------------------------------------------------*/\r
\r
#if( configENABLE_MPU == 1 )\r
- void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )\r
- {\r
- uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;\r
- int32_t lIndex = 0;\r
-\r
- /* Setup MAIR0. */\r
- xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
- xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
-\r
- /* This function is called automatically when the task is created - in\r
- * which case the stack region parameters will be valid. At all other\r
- * times the stack parameters will not be valid and it is assumed that\r
- * the stack region has already been configured. */\r
- if( ulStackDepth > 0 )\r
- {\r
- /* Define the region that allows access to the stack. */\r
- ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;\r
- ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;\r
- ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\r
-\r
- xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |\r
- ( portMPU_REGION_NON_SHAREABLE ) |\r
- ( portMPU_REGION_READ_WRITE ) |\r
- ( portMPU_REGION_EXECUTE_NEVER );\r
-\r
- xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |\r
- ( portMPU_RLAR_ATTR_INDEX0 ) |\r
- ( portMPU_RLAR_REGION_ENABLE );\r
- }\r
-\r
- /* User supplied configurable regions. */\r
- for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )\r
- {\r
- /* If xRegions is NULL i.e. the task has not specified any MPU\r
- * region, the else part ensures that all the configurable MPU\r
- * regions are invalidated. */\r
- if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )\r
- {\r
- /* Translate the generic region definition contained in xRegions\r
- * into the ARMv8 specific MPU settings that are then stored in\r
- * xMPUSettings. */\r
- ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;\r
- ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;\r
- ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\r
-\r
- /* Start address. */\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |\r
- ( portMPU_REGION_NON_SHAREABLE );\r
-\r
- /* RO/RW. */\r
- if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )\r
- {\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );\r
- }\r
- else\r
- {\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );\r
- }\r
-\r
- /* XN. */\r
- if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )\r
- {\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );\r
- }\r
-\r
- /* End Address. */\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |\r
- ( portMPU_RLAR_REGION_ENABLE );\r
-\r
- /* Normal memory/ Device memory. */\r
- if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )\r
- {\r
- /* Attr1 in MAIR0 is configured as device memory. */\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;\r
- }\r
- else\r
- {\r
- /* Attr1 in MAIR0 is configured as normal memory. */\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;\r
- }\r
- }\r
- else\r
- {\r
- /* Invalidate the region. */\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;\r
- xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;\r
- }\r
-\r
- lIndex++;\r
- }\r
- }\r
+ void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )\r
+ {\r
+ uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;\r
+ int32_t lIndex = 0;\r
+\r
+ /* Setup MAIR0. */\r
+ xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
+ xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
+\r
+ /* This function is called automatically when the task is created - in\r
+ * which case the stack region parameters will be valid. At all other\r
+ * times the stack parameters will not be valid and it is assumed that\r
+ * the stack region has already been configured. */\r
+ if( ulStackDepth > 0 )\r
+ {\r
+ /* Define the region that allows access to the stack. */\r
+ ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;\r
+ ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;\r
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\r
+\r
+ xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |\r
+ ( portMPU_REGION_NON_SHAREABLE ) |\r
+ ( portMPU_REGION_READ_WRITE ) |\r
+ ( portMPU_REGION_EXECUTE_NEVER );\r
+\r
+ xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |\r
+ ( portMPU_RLAR_ATTR_INDEX0 ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+ }\r
+\r
+ /* User supplied configurable regions. */\r
+ for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )\r
+ {\r
+ /* If xRegions is NULL i.e. the task has not specified any MPU\r
+ * region, the else part ensures that all the configurable MPU\r
+ * regions are invalidated. */\r
+ if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )\r
+ {\r
+ /* Translate the generic region definition contained in xRegions\r
+ * into the ARMv8 specific MPU settings that are then stored in\r
+ * xMPUSettings. */\r
+ ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;\r
+ ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;\r
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;\r
+\r
+ /* Start address. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |\r
+ ( portMPU_REGION_NON_SHAREABLE );\r
+\r
+ /* RO/RW. */\r
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )\r
+ {\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );\r
+ }\r
+ else\r
+ {\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );\r
+ }\r
+\r
+ /* XN. */\r
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )\r
+ {\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );\r
+ }\r
+\r
+ /* End Address. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |\r
+ ( portMPU_RLAR_REGION_ENABLE );\r
+\r
+ /* Normal memory/ Device memory. */\r
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )\r
+ {\r
+ /* Attr1 in MAIR0 is configured as device memory. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;\r
+ }\r
+ else\r
+ {\r
+ /* Attr1 in MAIR0 is configured as normal memory. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Invalidate the region. */\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;\r
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;\r
+ }\r
+\r
+ lIndex++;\r
+ }\r
+ }\r
#endif /* configENABLE_MPU */\r
/*-----------------------------------------------------------*/\r
* 1 tab == 4 spaces!\r
*/\r
\r
- EXTERN pxCurrentTCB\r
- EXTERN vTaskSwitchContext\r
- EXTERN vPortSVCHandler_C\r
-\r
- PUBLIC xIsPrivileged\r
- PUBLIC vResetPrivilege\r
- PUBLIC vRestoreContextOfFirstTask\r
- PUBLIC vRaisePrivilege\r
- PUBLIC vStartFirstTask\r
- PUBLIC ulSetInterruptMaskFromISR\r
- PUBLIC vClearInterruptMaskFromISR\r
- PUBLIC PendSV_Handler\r
- PUBLIC SVC_Handler\r
+ EXTERN pxCurrentTCB\r
+ EXTERN vTaskSwitchContext\r
+ EXTERN vPortSVCHandler_C\r
+\r
+ PUBLIC xIsPrivileged\r
+ PUBLIC vResetPrivilege\r
+ PUBLIC vRestoreContextOfFirstTask\r
+ PUBLIC vRaisePrivilege\r
+ PUBLIC vStartFirstTask\r
+ PUBLIC ulSetInterruptMaskFromISR\r
+ PUBLIC vClearInterruptMaskFromISR\r
+ PUBLIC PendSV_Handler\r
+ PUBLIC SVC_Handler\r
/*-----------------------------------------------------------*/\r
\r
/*---------------- Unprivileged Functions -------------------*/\r
\r
/*-----------------------------------------------------------*/\r
\r
- SECTION .text:CODE:NOROOT(2)\r
- THUMB\r
+ SECTION .text:CODE:NOROOT(2)\r
+ THUMB\r
/*-----------------------------------------------------------*/\r
\r
xIsPrivileged:\r
- mrs r0, control /* r0 = CONTROL. */\r
- tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\r
- ite ne\r
- movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
- moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */\r
- bx lr /* Return. */\r
+ mrs r0, control /* r0 = CONTROL. */\r
+ tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\r
+ ite ne\r
+ movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
+ moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */\r
+ bx lr /* Return. */\r
/*-----------------------------------------------------------*/\r
\r
vResetPrivilege:\r
- mrs r0, control /* r0 = CONTROL. */\r
- orr r0, r0, #1 /* r0 = r0 | 1. */\r
- msr control, r0 /* CONTROL = r0. */\r
- bx lr /* Return to the caller. */\r
+ mrs r0, control /* r0 = CONTROL. */\r
+ orr r0, r0, #1 /* r0 = r0 | 1. */\r
+ msr control, r0 /* CONTROL = r0. */\r
+ bx lr /* Return to the caller. */\r
/*-----------------------------------------------------------*/\r
\r
/*----------------- Privileged Functions --------------------*/\r
\r
/*-----------------------------------------------------------*/\r
\r
- SECTION privileged_functions:CODE:NOROOT(2)\r
- THUMB\r
+ SECTION privileged_functions:CODE:NOROOT(2)\r
+ THUMB\r
/*-----------------------------------------------------------*/\r
\r
vRestoreContextOfFirstTask:\r
- ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
- ldr r1, [r2] /* Read pxCurrentTCB. */\r
- ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ ldr r1, [r2] /* Read pxCurrentTCB. */\r
+ ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
\r
#if ( configENABLE_MPU == 1 )\r
- adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
- ldr r3, [r1] /* r3 = *r1 i.e. r3 = MAIR0. */\r
- ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
- str r3, [r2] /* Program MAIR0. */\r
- ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */\r
- movs r3, #4 /* r3 = 4. */\r
- str r3, [r2] /* Program RNR = 4. */\r
- adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
- ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */\r
- ldmia r1!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
- stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+ adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
+ ldr r3, [r1] /* r3 = *r1 i.e. r3 = MAIR0. */\r
+ ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ str r3, [r2] /* Program MAIR0. */\r
+ ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ movs r3, #4 /* r3 = 4. */\r
+ str r3, [r2] /* Program RNR = 4. */\r
+ adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
+ ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */\r
+ ldmia r1!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
+ stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
#endif /* configENABLE_MPU */\r
\r
#if ( configENABLE_MPU == 1 )\r
- ldm r0!, {r1-r3} /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */\r
- msr psplim, r1 /* Set this task's PSPLIM value. */\r
- msr control, r2 /* Set this task's CONTROL value. */\r
- adds r0, #32 /* Discard everything up to r0. */\r
- msr psp, r0 /* This is now the new top of stack to use in the task. */\r
- isb\r
- bx r3 /* Finally, branch to EXC_RETURN. */\r
+ ldm r0!, {r1-r3} /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */\r
+ msr psplim, r1 /* Set this task's PSPLIM value. */\r
+ msr control, r2 /* Set this task's CONTROL value. */\r
+ adds r0, #32 /* Discard everything up to r0. */\r
+ msr psp, r0 /* This is now the new top of stack to use in the task. */\r
+ isb\r
+ bx r3 /* Finally, branch to EXC_RETURN. */\r
#else /* configENABLE_MPU */\r
- ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */\r
- msr psplim, r1 /* Set this task's PSPLIM value. */\r
- movs r1, #2 /* r1 = 2. */\r
- msr CONTROL, r1 /* Switch to use PSP in the thread mode. */\r
- adds r0, #32 /* Discard everything up to r0. */\r
- msr psp, r0 /* This is now the new top of stack to use in the task. */\r
- isb\r
- bx r2 /* Finally, branch to EXC_RETURN. */\r
+ ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */\r
+ msr psplim, r1 /* Set this task's PSPLIM value. */\r
+ movs r1, #2 /* r1 = 2. */\r
+ msr CONTROL, r1 /* Switch to use PSP in the thread mode. */\r
+ adds r0, #32 /* Discard everything up to r0. */\r
+ msr psp, r0 /* This is now the new top of stack to use in the task. */\r
+ isb\r
+ bx r2 /* Finally, branch to EXC_RETURN. */\r
#endif /* configENABLE_MPU */\r
/*-----------------------------------------------------------*/\r
\r
vRaisePrivilege:\r
- mrs r0, control /* Read the CONTROL register. */\r
- bic r0, r0, #1 /* Clear the bit 0. */\r
- msr control, r0 /* Write back the new CONTROL value. */\r
- bx lr /* Return to the caller. */\r
+ mrs r0, control /* Read the CONTROL register. */\r
+ bic r0, r0, #1 /* Clear the bit 0. */\r
+ msr control, r0 /* Write back the new CONTROL value. */\r
+ bx lr /* Return to the caller. */\r
/*-----------------------------------------------------------*/\r
\r
vStartFirstTask:\r
- ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */\r
- ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */\r
- ldr r0, [r0] /* The first entry in vector table is stack pointer. */\r
- msr msp, r0 /* Set the MSP back to the start of the stack. */\r
- cpsie i /* Globally enable interrupts. */\r
- cpsie f\r
- dsb\r
- isb\r
- svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */\r
+ ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */\r
+ ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */\r
+ ldr r0, [r0] /* The first entry in vector table is stack pointer. */\r
+ msr msp, r0 /* Set the MSP back to the start of the stack. */\r
+ cpsie i /* Globally enable interrupts. */\r
+ cpsie f\r
+ dsb\r
+ isb\r
+ svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */\r
/*-----------------------------------------------------------*/\r
\r
ulSetInterruptMaskFromISR:\r
- mrs r0, PRIMASK\r
- cpsid i\r
- bx lr\r
+ mrs r0, PRIMASK\r
+ cpsid i\r
+ bx lr\r
/*-----------------------------------------------------------*/\r
\r
vClearInterruptMaskFromISR:\r
- msr PRIMASK, r0\r
- bx lr\r
+ msr PRIMASK, r0\r
+ bx lr\r
/*-----------------------------------------------------------*/\r
\r
PendSV_Handler:\r
- mrs r0, psp /* Read PSP in r0. */\r
+ mrs r0, psp /* Read PSP in r0. */\r
#if ( configENABLE_FPU == 1 )\r
- tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
- it eq\r
- vstmdbeq r0!, {s16-s31} /* Store the FPU registers which are not saved automatically. */\r
+ tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
+ it eq\r
+ vstmdbeq r0!, {s16-s31} /* Store the FPU registers which are not saved automatically. */\r
#endif /* configENABLE_FPU */\r
#if ( configENABLE_MPU == 1 )\r
- mrs r1, psplim /* r1 = PSPLIM. */\r
- mrs r2, control /* r2 = CONTROL. */\r
- mov r3, lr /* r3 = LR/EXC_RETURN. */\r
- stmdb r0!, {r1-r11} /* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */\r
+ mrs r1, psplim /* r1 = PSPLIM. */\r
+ mrs r2, control /* r2 = CONTROL. */\r
+ mov r3, lr /* r3 = LR/EXC_RETURN. */\r
+ stmdb r0!, {r1-r11} /* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */\r
#else /* configENABLE_MPU */\r
- mrs r2, psplim /* r2 = PSPLIM. */\r
- mov r3, lr /* r3 = LR/EXC_RETURN. */\r
- stmdb r0!, {r2-r11} /* Store on the stack - PSPLIM, LR and registers that are not automatically. */\r
+ mrs r2, psplim /* r2 = PSPLIM. */\r
+ mov r3, lr /* r3 = LR/EXC_RETURN. */\r
+ stmdb r0!, {r2-r11} /* Store on the stack - PSPLIM, LR and registers that are not automatically. */\r
#endif /* configENABLE_MPU */\r
\r
- ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
- ldr r1, [r2] /* Read pxCurrentTCB. */\r
- str r0, [r1] /* Save the new top of stack in TCB. */\r
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ ldr r1, [r2] /* Read pxCurrentTCB. */\r
+ str r0, [r1] /* Save the new top of stack in TCB. */\r
\r
- cpsid i\r
- bl vTaskSwitchContext\r
- cpsie i\r
+ cpsid i\r
+ bl vTaskSwitchContext\r
+ cpsie i\r
\r
- ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
- ldr r1, [r2] /* Read pxCurrentTCB. */\r
- ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */\r
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
+ ldr r1, [r2] /* Read pxCurrentTCB. */\r
+ ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */\r
\r
#if ( configENABLE_MPU == 1 )\r
- adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
- ldr r3, [r1] /* r3 = *r1 i.e. r3 = MAIR0. */\r
- ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
- str r3, [r2] /* Program MAIR0. */\r
- ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */\r
- movs r3, #4 /* r3 = 4. */\r
- str r3, [r2] /* Program RNR = 4. */\r
- adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
- ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */\r
- ldmia r1!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
- stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
+ adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
+ ldr r3, [r1] /* r3 = *r1 i.e. r3 = MAIR0. */\r
+ ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
+ str r3, [r2] /* Program MAIR0. */\r
+ ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */\r
+ movs r3, #4 /* r3 = 4. */\r
+ str r3, [r2] /* Program RNR = 4. */\r
+ adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
+ ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */\r
+ ldmia r1!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
+ stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
#endif /* configENABLE_MPU */\r
\r
#if ( configENABLE_MPU == 1 )\r
- ldmia r0!, {r1-r11} /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */\r
+ ldmia r0!, {r1-r11} /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */\r
#else /* configENABLE_MPU */\r
- ldmia r0!, {r2-r11} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */\r
+ ldmia r0!, {r2-r11} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */\r
#endif /* configENABLE_MPU */\r
\r
#if ( configENABLE_FPU == 1 )\r
- tst r3, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
- it eq\r
- vldmiaeq r0!, {s16-s31} /* Restore the FPU registers which are not restored automatically. */\r
+ tst r3, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
+ it eq\r
+ vldmiaeq r0!, {s16-s31} /* Restore the FPU registers which are not restored automatically. */\r
#endif /* configENABLE_FPU */\r
\r
#if ( configENABLE_MPU == 1 )\r
- msr psplim, r1 /* Restore the PSPLIM register value for the task. */\r
- msr control, r2 /* Restore the CONTROL register value for the task. */\r
+ msr psplim, r1 /* Restore the PSPLIM register value for the task. */\r
+ msr control, r2 /* Restore the CONTROL register value for the task. */\r
#else /* configENABLE_MPU */\r
- msr psplim, r2 /* Restore the PSPLIM register value for the task. */\r
+ msr psplim, r2 /* Restore the PSPLIM register value for the task. */\r
#endif /* configENABLE_MPU */\r
- msr psp, r0 /* Remember the new top of stack for the task. */\r
- bx r3\r
+ msr psp, r0 /* Remember the new top of stack for the task. */\r
+ bx r3\r
/*-----------------------------------------------------------*/\r
\r
SVC_Handler:\r
- tst lr, #4\r
- ite eq\r
- mrseq r0, msp\r
- mrsne r0, psp\r
- b vPortSVCHandler_C\r
+ tst lr, #4\r
+ ite eq\r
+ mrseq r0, msp\r
+ mrsne r0, psp\r
+ b vPortSVCHandler_C\r
/*-----------------------------------------------------------*/\r
\r
- END\r
+ END\r
*------------------------------------------------------------------------------\r
*/\r
\r
+#ifndef configENABLE_FPU\r
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h.\r
+#endif /* configENABLE_FPU */\r
+\r
+#ifndef configENABLE_MPU\r
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h.\r
+#endif /* configENABLE_MPU */\r
+\r
+#ifndef configENABLE_TRUSTZONE\r
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.\r
+#endif /* configENABLE_TRUSTZONE */\r
+/*-----------------------------------------------------------*/\r
+\r
/**\r
* @brief Type definitions.\r
*/\r
-#define portCHAR char\r
-#define portFLOAT float\r
-#define portDOUBLE double\r
-#define portLONG long\r
-#define portSHORT short\r
-#define portSTACK_TYPE uint32_t\r
-#define portBASE_TYPE long\r
-\r
-typedef portSTACK_TYPE StackType_t;\r
-typedef long BaseType_t;\r
-typedef unsigned long UBaseType_t;\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT short\r
+#define portSTACK_TYPE uint32_t\r
+#define portBASE_TYPE long\r
+\r
+typedef portSTACK_TYPE StackType_t;\r
+typedef long BaseType_t;\r
+typedef unsigned long UBaseType_t;\r
\r
#if( configUSE_16_BIT_TICKS == 1 )\r
- typedef uint16_t TickType_t;\r
- #define portMAX_DELAY ( TickType_t ) 0xffff\r
+ typedef uint16_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffff\r
#else\r
- typedef uint32_t TickType_t;\r
- #define portMAX_DELAY ( TickType_t ) 0xffffffffUL\r
+ typedef uint32_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL\r
\r
- /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\r
- * not need to be guarded with a critical section. */\r
- #define portTICK_TYPE_IS_ATOMIC 1\r
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\r
+ * not need to be guarded with a critical section. */\r
+ #define portTICK_TYPE_IS_ATOMIC 1\r
#endif\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* Architecture specifics.\r
*/\r
-#define portSTACK_GROWTH ( -1 )\r
-#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
-#define portBYTE_ALIGNMENT 8\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
+#define portBYTE_ALIGNMENT 8\r
#define portNOP()\r
-#define portINLINE __inline\r
+#define portINLINE __inline\r
#ifndef portFORCE_INLINE\r
- #define portFORCE_INLINE inline __attribute__(( always_inline ))\r
+ #define portFORCE_INLINE inline __attribute__(( always_inline ))\r
#endif\r
-#define portHAS_STACK_OVERFLOW_CHECKING 1\r
+#define portHAS_STACK_OVERFLOW_CHECKING 1\r
/*-----------------------------------------------------------*/\r
\r
/**\r
extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
- extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );\r
- extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* PRIVILEGED_FUNCTION */;\r
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );\r
+ extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* PRIVILEGED_FUNCTION */;\r
#endif /* configENABLE_TRUSTZONE */\r
\r
#if( configENABLE_MPU == 1 )\r
- extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;\r
- extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;\r
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;\r
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;\r
#endif /* configENABLE_MPU */\r
/*-----------------------------------------------------------*/\r
\r
* @brief MPU specific constants.\r
*/\r
#if( configENABLE_MPU == 1 )\r
- #define portUSING_MPU_WRAPPERS 1\r
- #define portPRIVILEGE_BIT ( 0x80000000UL )\r
+ #define portUSING_MPU_WRAPPERS 1\r
+ #define portPRIVILEGE_BIT ( 0x80000000UL )\r
#else\r
- #define portPRIVILEGE_BIT ( 0x0UL )\r
+ #define portPRIVILEGE_BIT ( 0x0UL )\r
#endif /* configENABLE_MPU */\r
\r
\r
/* MPU regions. */\r
-#define portPRIVILEGED_FLASH_REGION ( 0UL )\r
-#define portUNPRIVILEGED_FLASH_REGION ( 1UL )\r
-#define portPRIVILEGED_RAM_REGION ( 2UL )\r
-#define portUNPRIVILEGED_DEVICE_REGION ( 3UL )\r
-#define portSTACK_REGION ( 4UL )\r
-#define portFIRST_CONFIGURABLE_REGION ( 5UL )\r
-#define portLAST_CONFIGURABLE_REGION ( 7UL )\r
-#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\r
-#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */\r
+#define portPRIVILEGED_FLASH_REGION ( 0UL )\r
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )\r
+#define portPRIVILEGED_RAM_REGION ( 2UL )\r
+#define portUNPRIVILEGED_DEVICE_REGION ( 3UL )\r
+#define portSTACK_REGION ( 4UL )\r
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )\r
+#define portLAST_CONFIGURABLE_REGION ( 7UL )\r
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\r
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */\r
\r
/* Devices Region. */\r
-#define portDEVICE_REGION_START_ADDRESS ( 0x50000000 )\r
-#define portDEVICE_REGION_END_ADDRESS ( 0x5FFFFFFF )\r
+#define portDEVICE_REGION_START_ADDRESS ( 0x50000000 )\r
+#define portDEVICE_REGION_END_ADDRESS ( 0x5FFFFFFF )\r
\r
/* Device memory attributes used in MPU_MAIR registers.\r
*\r
* 8-bit values encoded as follows:\r
* Bit[7:4] - 0000 - Device Memory\r
* Bit[3:2] - 00 --> Device-nGnRnE\r
- * 01 --> Device-nGnRE\r
- * 10 --> Device-nGRE\r
- * 11 --> Device-GRE\r
+ * 01 --> Device-nGnRE\r
+ * 10 --> Device-nGRE\r
+ * 11 --> Device-GRE\r
* Bit[1:0] - 00, Reserved.\r
*/\r
-#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */\r
-#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */\r
-#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */\r
-#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */\r
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */\r
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */\r
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */\r
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */\r
\r
/* Normal memory attributes used in MPU_MAIR registers. */\r
-#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */\r
-#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */\r
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */\r
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */\r
\r
/* Attributes used in MPU_RBAR registers. */\r
-#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )\r
-#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )\r
-#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )\r
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )\r
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )\r
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )\r
\r
-#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )\r
-#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )\r
-#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )\r
-#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )\r
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )\r
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )\r
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )\r
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )\r
\r
-#define portMPU_REGION_EXECUTE_NEVER ( 1UL )\r
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )\r
/*-----------------------------------------------------------*/\r
\r
/**\r
*/\r
typedef struct MPURegionSettings\r
{\r
- uint32_t ulRBAR; /**< RBAR for the region. */\r
- uint32_t ulRLAR; /**< RLAR for the region. */\r
+ uint32_t ulRBAR; /**< RBAR for the region. */\r
+ uint32_t ulRLAR; /**< RLAR for the region. */\r
} MPURegionSettings_t;\r
\r
/**\r
*/\r
typedef struct MPU_SETTINGS\r
{\r
- uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */\r
- MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */\r
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */\r
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */\r
} xMPU_SETTINGS;\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief SVC numbers.\r
*/\r
-#define portSVC_ALLOCATE_SECURE_CONTEXT 0\r
-#define portSVC_FREE_SECURE_CONTEXT 1\r
-#define portSVC_START_SCHEDULER 2\r
-#define portSVC_RAISE_PRIVILEGE 3\r
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0\r
+#define portSVC_FREE_SECURE_CONTEXT 1\r
+#define portSVC_START_SCHEDULER 2\r
+#define portSVC_RAISE_PRIVILEGE 3\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Scheduler utilities.\r
*/\r
-#define portYIELD() vPortYield()\r
-#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )\r
-#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )\r
-#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT\r
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
+#define portYIELD() vPortYield()\r
+#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )\r
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )\r
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT\r
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Critical section management.\r
*/\r
-#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()\r
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )\r
-#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )\r
-#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )\r
-#define portENTER_CRITICAL() vPortEnterCritical()\r
-#define portEXIT_CRITICAL() vPortExitCritical()\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )\r
+#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )\r
+#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )\r
+#define portENTER_CRITICAL() vPortEnterCritical()\r
+#define portEXIT_CRITICAL() vPortExitCritical()\r
/*-----------------------------------------------------------*/\r
\r
/**\r
* @brief Task function macros as described on the FreeRTOS.org WEB site.\r
*/\r
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
/*-----------------------------------------------------------*/\r
\r
#if( configENABLE_TRUSTZONE == 1 )\r
- /**\r
- * @brief Allocate a secure context for the task.\r
- *\r
- * Tasks are not created with a secure context. Any task that is going to call\r
- * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a\r
- * secure context before it calls any secure function.\r
- *\r
- * @param[in] ulSecureStackSize The size of the secure stack to be allocated.\r
- */\r
- #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )\r
-\r
- /**\r
- * @brief Called when a task is deleted to delete the task's secure context,\r
- * if it has one.\r
- *\r
- * @param[in] pxTCB The TCB of the task being deleted.\r
- */\r
- #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )\r
+ /**\r
+ * @brief Allocate a secure context for the task.\r
+ *\r
+ * Tasks are not created with a secure context. Any task that is going to call\r
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a\r
+ * secure context before it calls any secure function.\r
+ *\r
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.\r
+ */\r
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )\r
+\r
+ /**\r
+ * @brief Called when a task is deleted to delete the task's secure context,\r
+ * if it has one.\r
+ *\r
+ * @param[in] pxTCB The TCB of the task being deleted.\r
+ */\r
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )\r
#else\r
- #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )\r
- #define portCLEAN_UP_TCB( pxTCB )\r
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )\r
+ #define portCLEAN_UP_TCB( pxTCB )\r
#endif /* configENABLE_TRUSTZONE */\r
/*-----------------------------------------------------------*/\r
\r
#if( configENABLE_MPU == 1 )\r
- /**\r
- * @brief Checks whether or not the processor is privileged.\r
- *\r
- * @return 1 if the processor is already privileged, 0 otherwise.\r
- */\r
- #define portIS_PRIVILEGED() xIsPrivileged()\r
-\r
- /**\r
- * @brief Raise an SVC request to raise privilege.\r
- *\r
- * The SVC handler checks that the SVC was raised from a system call and only\r
- * then it raises the privilege. If this is called from any other place,\r
- * the privilege is not raised.\r
- */\r
- #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );\r
-\r
- /**\r
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\r
- * register.\r
- */\r
- #define portRESET_PRIVILEGE() vResetPrivilege()\r
+ /**\r
+ * @brief Checks whether or not the processor is privileged.\r
+ *\r
+ * @return 1 if the processor is already privileged, 0 otherwise.\r
+ */\r
+ #define portIS_PRIVILEGED() xIsPrivileged()\r
+\r
+ /**\r
+ * @brief Raise an SVC request to raise privilege.\r
+ *\r
+ * The SVC handler checks that the SVC was raised from a system call and only\r
+ * then it raises the privilege. If this is called from any other place,\r
+ * the privilege is not raised.\r
+ */\r
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );\r
+\r
+ /**\r
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\r
+ * register.\r
+ */\r
+ #define portRESET_PRIVILEGE() vResetPrivilege()\r
#else\r
- #define portIS_PRIVILEGED()\r
- #define portRAISE_PRIVILEGE()\r
- #define portRESET_PRIVILEGE()\r
+ #define portIS_PRIVILEGED()\r
+ #define portRAISE_PRIVILEGE()\r
+ #define portRESET_PRIVILEGE()\r
#endif /* configENABLE_MPU */\r
/*-----------------------------------------------------------*/\r
\r
projects / freertos / commitdiff