-/*
- * Enable ECC by setting L2CTLR[21].
- * Set L2CTLR[7] to make tag ram latency 3 cycles and
- * set L2CTLR[1] to make data ram latency 3 cycles.
- * We need to make RAM latency of 3 cycles here because cores
- * power ON and OFF while switching. And everytime a core powers
- * ON, iROM provides it a default L2CTLR value 0x400 which stands
- * for TAG RAM setup of 1 cycle. Hence, we face a need of
- * restoring data and tag latency values.
- */
-static void configure_l2_ctlr(void)
-{
- uint32_t val;
-
- mrc_l2_ctlr(val);
- val |= (1 << 21);
- val |= (1 << 7);
- val |= (1 << 1);
- mcr_l2_ctlr(val);
-}
-
-/*
- * Set L2ACTLR[27] to prevent the clock generator from stopping
- * the L2 logic clock.
- * Set L2ACTLR[3] to disable clean/evict push to external.
- */
-static void configure_l2_actlr(void)
-{
- uint32_t val;
-
- mrc_l2_aux_ctlr(val);
- val |= (1 << 27);
- val |= (1 << 3);
- mcr_l2_aux_ctlr(val);
-}
-