spl: fix assignment of board info to global data

[u-boot] / arch / arm / cpu / armv8 / fsl-layerscape / Kconfig

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index a99b1c6a99b2ce036c9c4b5c430d06c5392d5907..85b7c70937e84f6694eb1e46c354e3007cc9ec37 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -16,8 +16,12 @@ config ARCH_LS1043A
        select SYS_FSL_DDR_BE
        select SYS_FSL_DDR_VER_50
        select SYS_FSL_ERRATUM_A008850
        select SYS_FSL_DDR_BE
        select SYS_FSL_DDR_VER_50
        select SYS_FSL_ERRATUM_A008850

+       select SYS_FSL_ERRATUM_A008997
+       select SYS_FSL_ERRATUM_A009007
+       select SYS_FSL_ERRATUM_A009008

        select SYS_FSL_ERRATUM_A009660
        select SYS_FSL_ERRATUM_A009663
        select SYS_FSL_ERRATUM_A009660
        select SYS_FSL_ERRATUM_A009663

+       select SYS_FSL_ERRATUM_A009798

        select SYS_FSL_ERRATUM_A009929
        select SYS_FSL_ERRATUM_A009942
        select SYS_FSL_ERRATUM_A010315
        select SYS_FSL_ERRATUM_A009929
        select SYS_FSL_ERRATUM_A009942
        select SYS_FSL_ERRATUM_A010315


@@ -26,6 +30,8 @@ config ARCH_LS1043A
        select SYS_FSL_HAS_DDR4
        select ARCH_EARLY_INIT_R
        select BOARD_EARLY_INIT_F
        select SYS_FSL_HAS_DDR4
        select ARCH_EARLY_INIT_R
        select BOARD_EARLY_INIT_F

+       imply SCSI
+       imply CMD_PCI

 
 config ARCH_LS1046A
        bool
 
 config ARCH_LS1046A
        bool


@@ -36,6 +42,11 @@ config ARCH_LS1046A
        select SYS_FSL_DDR_VER_50
        select SYS_FSL_ERRATUM_A008336
        select SYS_FSL_ERRATUM_A008511
        select SYS_FSL_DDR_VER_50
        select SYS_FSL_ERRATUM_A008336
        select SYS_FSL_ERRATUM_A008511

+       select SYS_FSL_ERRATUM_A008850
+       select SYS_FSL_ERRATUM_A008997
+       select SYS_FSL_ERRATUM_A009007
+       select SYS_FSL_ERRATUM_A009008
+       select SYS_FSL_ERRATUM_A009798

        select SYS_FSL_ERRATUM_A009801
        select SYS_FSL_ERRATUM_A009803
        select SYS_FSL_ERRATUM_A009942
        select SYS_FSL_ERRATUM_A009801
        select SYS_FSL_ERRATUM_A009803
        select SYS_FSL_ERRATUM_A009942


@@ -45,6 +56,34 @@ config ARCH_LS1046A
        select SYS_FSL_SRDS_2
        select ARCH_EARLY_INIT_R
        select BOARD_EARLY_INIT_F
        select SYS_FSL_SRDS_2
        select ARCH_EARLY_INIT_R
        select BOARD_EARLY_INIT_F

+       imply SCSI
+
+config ARCH_LS1088A
+       bool
+       select ARMV8_SET_SMPEN
+       select FSL_LSCH3
+       select SYS_FSL_DDR
+       select SYS_FSL_DDR_LE
+       select SYS_FSL_DDR_VER_50
+       select SYS_FSL_EC1
+       select SYS_FSL_EC2
+       select SYS_FSL_ERRATUM_A009803
+       select SYS_FSL_ERRATUM_A009942
+       select SYS_FSL_ERRATUM_A010165
+       select SYS_FSL_ERRATUM_A008511
+       select SYS_FSL_ERRATUM_A008850
+       select SYS_FSL_ERRATUM_A009007
+       select SYS_FSL_HAS_CCI400
+       select SYS_FSL_HAS_DDR4
+       select SYS_FSL_HAS_RGMII
+       select SYS_FSL_HAS_SEC
+       select SYS_FSL_SEC_COMPAT_5
+       select SYS_FSL_SEC_LE
+       select SYS_FSL_SRDS_1
+       select SYS_FSL_SRDS_2
+       select FSL_TZASC_1
+       select ARCH_EARLY_INIT_R
+       select BOARD_EARLY_INIT_F

 
 config ARCH_LS2080A
        bool
 
 config ARCH_LS2080A
        bool


@@ -57,27 +96,36 @@ config ARCH_LS2080A
        select SYS_FSL_DDR
        select SYS_FSL_DDR_LE
        select SYS_FSL_DDR_VER_50
        select SYS_FSL_DDR
        select SYS_FSL_DDR_LE
        select SYS_FSL_DDR_VER_50

+       select SYS_FSL_HAS_CCN504

        select SYS_FSL_HAS_DP_DDR
        select SYS_FSL_HAS_SEC
        select SYS_FSL_HAS_DDR4
        select SYS_FSL_SEC_COMPAT_5
        select SYS_FSL_SEC_LE
        select SYS_FSL_SRDS_2
        select SYS_FSL_HAS_DP_DDR
        select SYS_FSL_HAS_SEC
        select SYS_FSL_HAS_DDR4
        select SYS_FSL_SEC_COMPAT_5
        select SYS_FSL_SEC_LE
        select SYS_FSL_SRDS_2

+       select FSL_TZASC_1
+       select FSL_TZASC_2

        select SYS_FSL_ERRATUM_A008336
        select SYS_FSL_ERRATUM_A008511
        select SYS_FSL_ERRATUM_A008514
        select SYS_FSL_ERRATUM_A008585
        select SYS_FSL_ERRATUM_A008336
        select SYS_FSL_ERRATUM_A008511
        select SYS_FSL_ERRATUM_A008514
        select SYS_FSL_ERRATUM_A008585

+       select SYS_FSL_ERRATUM_A008997
+       select SYS_FSL_ERRATUM_A009007
+       select SYS_FSL_ERRATUM_A009008

        select SYS_FSL_ERRATUM_A009635
        select SYS_FSL_ERRATUM_A009663
        select SYS_FSL_ERRATUM_A009635
        select SYS_FSL_ERRATUM_A009663

+       select SYS_FSL_ERRATUM_A009798

        select SYS_FSL_ERRATUM_A009801
        select SYS_FSL_ERRATUM_A009803
        select SYS_FSL_ERRATUM_A009942
        select SYS_FSL_ERRATUM_A010165
        select SYS_FSL_ERRATUM_A009801
        select SYS_FSL_ERRATUM_A009803
        select SYS_FSL_ERRATUM_A009942
        select SYS_FSL_ERRATUM_A010165

+       select SYS_FSL_ERRATUM_A009203

        select ARCH_EARLY_INIT_R
        select BOARD_EARLY_INIT_F
 
 config FSL_LSCH2
        bool
        select ARCH_EARLY_INIT_R
        select BOARD_EARLY_INIT_F
 
 config FSL_LSCH2
        bool

+       select SYS_FSL_HAS_CCI400

        select SYS_FSL_HAS_SEC
        select SYS_FSL_SEC_COMPAT_5
        select SYS_FSL_SEC_BE
        select SYS_FSL_HAS_SEC
        select SYS_FSL_SEC_COMPAT_5
        select SYS_FSL_SEC_BE


@@ -91,7 +139,7 @@ config FSL_LSCH3
 
 config FSL_MC_ENET
        bool "Management Complex network"
 
 config FSL_MC_ENET
        bool "Management Complex network"

-       depends on ARCH_LS2080A
+       depends on ARCH_LS2080A || ARCH_LS1088A

        default y
        select RESV_RAM
        help
        default y
        select RESV_RAM
        help


@@ -107,6 +155,7 @@ config FSL_PCIE_COMPAT
        default "fsl,ls1043a-pcie" if ARCH_LS1043A
        default "fsl,ls1046a-pcie" if ARCH_LS1046A
        default "fsl,ls2080a-pcie" if ARCH_LS2080A
        default "fsl,ls1043a-pcie" if ARCH_LS1043A
        default "fsl,ls1046a-pcie" if ARCH_LS1046A
        default "fsl,ls2080a-pcie" if ARCH_LS2080A

+       default "fsl,ls1088a-pcie" if ARCH_LS1088A

        help
          This compatible is used to find pci controller node in Kernel DT
          to complete fixup.
        help
          This compatible is used to find pci controller node in Kernel DT
          to complete fixup.


@@ -131,9 +180,24 @@ config FSL_LS_PPA
          which is loaded during boot stage, and then remains resident in RAM
          and runs in the TrustZone after boot.
          Say y to enable it.
          which is loaded during boot stage, and then remains resident in RAM
          and runs in the TrustZone after boot.
          Say y to enable it.

+
+config SPL_FSL_LS_PPA
+       bool "FSL Layerscape PPA firmware support for SPL build"
+       depends on !ARMV8_PSCI
+       select SPL_ARMV8_SEC_FIRMWARE_SUPPORT
+       select SEC_FIRMWARE_ARMV8_PSCI
+       select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
+       help
+         The FSL Primary Protected Application (PPA) is a software component
+         which is loaded during boot stage, and then remains resident in RAM
+         and runs in the TrustZone after boot. This is to load PPA during SPL
+         stage instead of the RAM version of U-Boot. Once PPA is initialized,
+         the rest of U-Boot (including RAM version) runs at EL2.

 choice
        prompt "FSL Layerscape PPA firmware loading-media select"
        depends on FSL_LS_PPA
 choice
        prompt "FSL Layerscape PPA firmware loading-media select"
        depends on FSL_LS_PPA

+       default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
+       default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT

        default SYS_LS_PPA_FW_IN_XIP
 
 config SYS_LS_PPA_FW_IN_XIP
        default SYS_LS_PPA_FW_IN_XIP
 
 config SYS_LS_PPA_FW_IN_XIP


@@ -142,20 +206,75 @@ config SYS_LS_PPA_FW_IN_XIP
          Say Y here if the PPA firmware locate at XIP flash, such
          as NOR or QSPI flash.
 
          Say Y here if the PPA firmware locate at XIP flash, such
          as NOR or QSPI flash.
 

+config SYS_LS_PPA_FW_IN_MMC
+       bool "eMMC or SD Card"
+       help
+         Say Y here if the PPA firmware locate at eMMC/SD card.
+
+config SYS_LS_PPA_FW_IN_NAND
+       bool "NAND"
+       help
+         Say Y here if the PPA firmware locate at NAND flash.
+

 endchoice
 
 config SYS_LS_PPA_FW_ADDR
        hex "Address of PPA firmware loading from"
        depends on FSL_LS_PPA
 endchoice
 
 config SYS_LS_PPA_FW_ADDR
        hex "Address of PPA firmware loading from"
        depends on FSL_LS_PPA

-       default 0x40500000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
-       default 0x60500000 if SYS_LS_PPA_FW_IN_XIP
+       default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
+       default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
+       default 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
+       default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1088A
+       default 0x60400000 if SYS_LS_PPA_FW_IN_XIP
+       default 0x400000 if SYS_LS_PPA_FW_IN_MMC
+       default 0x400000 if SYS_LS_PPA_FW_IN_NAND
+

        help
          If the PPA firmware locate at XIP flash, such as NOR or
          QSPI flash, this address is a directly memory-mapped.
          If it is in a serial accessed flash, such as NAND and SD
          card, it is a byte offset.
        help
          If the PPA firmware locate at XIP flash, such as NOR or
          QSPI flash, this address is a directly memory-mapped.
          If it is in a serial accessed flash, such as NAND and SD
          card, it is a byte offset.

+
+config SYS_LS_PPA_ESBC_ADDR
+       hex "hdr address of PPA firmware loading from"
+       depends on FSL_LS_PPA && CHAIN_OF_TRUST
+       default 0x60680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A
+       default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A
+       default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A
+       default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
+       default 0x580680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
+       default 0x680000 if SYS_LS_PPA_FW_IN_MMC
+       default 0x680000 if SYS_LS_PPA_FW_IN_NAND
+       help
+         If the PPA header firmware locate at XIP flash, such as NOR or
+         QSPI flash, this address is a directly memory-mapped.
+         If it is in a serial accessed flash, such as NAND and SD
+         card, it is a byte offset.
+
+config LS_PPA_ESBC_HDR_SIZE
+       hex "Length of PPA ESBC header"
+       depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
+       default 0x2000
+       help
+         Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
+         NAND to memory to validate PPA image.
+

 endmenu
 
 endmenu
 

+config SYS_FSL_ERRATUM_A008997
+       bool "Workaround for USB PHY erratum A008997"
+
+config SYS_FSL_ERRATUM_A009007
+       bool
+       help
+         Workaround for USB PHY erratum A009007
+
+config SYS_FSL_ERRATUM_A009008
+       bool "Workaround for USB PHY erratum A009008"
+
+config SYS_FSL_ERRATUM_A009798
+       bool "Workaround for USB PHY erratum A009798"
+

 config SYS_FSL_ERRATUM_A010315
        bool "Workaround for PCIe erratum A010315"
 
 config SYS_FSL_ERRATUM_A010315
        bool "Workaround for PCIe erratum A010315"
 


@@ -167,6 +286,7 @@ config MAX_CPUS
        default 4 if ARCH_LS1043A
        default 4 if ARCH_LS1046A
        default 16 if ARCH_LS2080A
        default 4 if ARCH_LS1043A
        default 4 if ARCH_LS1046A
        default 16 if ARCH_LS2080A

+       default 8 if ARCH_LS1088A

        default 1
        help
          Set this number to the maximum number of possible CPUs in the SoC.
        default 1
        help
          Set this number to the maximum number of possible CPUs in the SoC.


@@ -187,12 +307,27 @@ config QSPI_AHB_INIT
          But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
          bus for those flashes to support the full QSPI flash size.
 
          But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
          bus for those flashes to support the full QSPI flash size.
 

+config SYS_CCI400_OFFSET
+       hex "Offset for CCI400 base"
+       depends on SYS_FSL_HAS_CCI400
+       default 0x3090000 if ARCH_LS1088A
+       default 0x180000 if FSL_LSCH2
+       help
+         Offset for CCI400 base
+         CCI400 base addr = CCSRBAR + CCI400_OFFSET
+

 config SYS_FSL_IFC_BANK_COUNT
        int "Maximum banks of Integrated flash controller"
 config SYS_FSL_IFC_BANK_COUNT
        int "Maximum banks of Integrated flash controller"

-       depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
+       depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A

        default 4 if ARCH_LS1043A
        default 4 if ARCH_LS1046A
        default 4 if ARCH_LS1043A
        default 4 if ARCH_LS1046A

-       default 8 if ARCH_LS2080A
+       default 8 if ARCH_LS2080A || ARCH_LS1088A
+
+config SYS_FSL_HAS_CCI400
+       bool
+
+config SYS_FSL_HAS_CCN504
+       bool

 
 config SYS_FSL_HAS_DP_DDR
        bool
 
 config SYS_FSL_HAS_DP_DDR
        bool


@@ -206,6 +341,12 @@ config SYS_FSL_SRDS_2
 config SYS_HAS_SERDES
        bool
 
 config SYS_HAS_SERDES
        bool
 

+config FSL_TZASC_1
+       bool
+
+config FSL_TZASC_2
+       bool
+

 endmenu
 
 menu "Layerscape clock tree configuration"
 endmenu
 
 menu "Layerscape clock tree configuration"


@@ -229,6 +370,7 @@ config SYS_FSL_PCLK_DIV
        int "Platform clock divider"
        default 1 if ARCH_LS1043A
        default 1 if ARCH_LS1046A
        int "Platform clock divider"
        default 1 if ARCH_LS1043A
        default 1 if ARCH_LS1046A

+       default 1 if ARCH_LS1088A

        default 2
        help
          This is the divider that is used to derive Platform clock from
        default 2
        help
          This is the divider that is used to derive Platform clock from


@@ -241,7 +383,7 @@ config SYS_FSL_DSPI_CLK_DIV
        default 2
        help
          This is the divider that is used to derive DSPI clock from Platform
        default 2
        help
          This is the divider that is used to derive DSPI clock from Platform

-         PLL, in another word DSPI_clk = Platform_PLL_freq / this_divider.
+         clock, in another word DSPI_clk = Platform_clk / this_divider.

 
 config SYS_FSL_DUART_CLK_DIV
        int "DUART clock divider"
 
 config SYS_FSL_DUART_CLK_DIV
        int "DUART clock divider"


@@ -295,6 +437,18 @@ config RESV_RAM
          be at the high end of physical memory. The reserve RAM may be
          excluded from memory bank(s) passed to OS, or marked as reserved.
 
          be at the high end of physical memory. The reserve RAM may be
          excluded from memory bank(s) passed to OS, or marked as reserved.
 

+config SYS_FSL_EC1
+       bool
+       help
+         Ethernet controller 1, this is connected to MAC3.
+         Provides DPAA2 capabilities
+
+config SYS_FSL_EC2
+       bool
+       help
+         Ethernet controller 2, this is connected to MAC4.
+         Provides DPAA2 capabilities
+

 config SYS_FSL_ERRATUM_A008336
        bool
 
 config SYS_FSL_ERRATUM_A008336
        bool
 


@@ -307,6 +461,9 @@ config SYS_FSL_ERRATUM_A008585
 config SYS_FSL_ERRATUM_A008850
        bool
 
 config SYS_FSL_ERRATUM_A008850
        bool
 

+config SYS_FSL_ERRATUM_A009203
+       bool
+

 config SYS_FSL_ERRATUM_A009635
        bool
 
 config SYS_FSL_ERRATUM_A009635
        bool
 


@@ -316,10 +473,20 @@ config SYS_FSL_ERRATUM_A009660
 config SYS_FSL_ERRATUM_A009929
        bool
 
 config SYS_FSL_ERRATUM_A009929
        bool
 

+
+config SYS_FSL_HAS_RGMII
+       bool
+       depends on SYS_FSL_EC1 || SYS_FSL_EC2
+
+

 config SYS_MC_RSV_MEM_ALIGN
        hex "Management Complex reserved memory alignment"
        depends on RESV_RAM
 config SYS_MC_RSV_MEM_ALIGN
        hex "Management Complex reserved memory alignment"
        depends on RESV_RAM

-       default 0x20000000
+       default 0x20000000 if ARCH_LS2080A
+       default 0x70000000 if ARCH_LS1088A

        help
          Reserved memory needs to be aligned for MC to use. Default value
          is 512MB.
        help
          Reserved memory needs to be aligned for MC to use. Default value
          is 512MB.

+
+config SPL_LDSCRIPT
+       default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A