- apb2: apb2_clk@1c20058 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-apb1-clk";
- reg = <0x01c20058 0x4>;
- clocks = <&osc32k>, <&osc24M>, <&pll6 1>, <&pll6 1>;
- clock-output-names = "apb2";
- };
-
- bus_gates: bus_gates_clk@1c20060 {
- #clock-cells = <1>;
- compatible = "allwinner,sun50i-a64-bus-gates-clk",
- "allwinner,sunxi-multi-bus-gates-clk";
- reg = <0x01c20060 0x14>;
- ahb1_parent {
- clocks = <&ahb1>;
- clock-indices = <1>, <5>,
- <6>, <8>,
- <9>, <10>,
- <13>, <14>,
- <18>, <19>,
- <20>, <21>,
- <23>, <24>,
- <25>, <28>,
- <32>, <35>,
- <36>, <37>,
- <40>, <43>,
- <44>, <52>,
- <53>, <54>,
- <135>;
- clock-output-names = "bus_mipidsi", "bus_ce",
- "bus_dma", "bus_mmc0",
- "bus_mmc1", "bus_mmc2",
- "bus_nand", "bus_sdram",
- "bus_ts", "bus_hstimer",
- "bus_spi0", "bus_spi1",
- "bus_otg", "bus_otg_ehci0",
- "bus_ehci0", "bus_otg_ohci0",
- "bus_ve", "bus_lcd0",
- "bus_lcd1", "bus_deint",
- "bus_csi", "bus_hdmi",
- "bus_de", "bus_gpu",
- "bus_msgbox", "bus_spinlock",
- "bus_dbg";
- };
- ahb2_parent {
- clocks = <&ahb2>;
- clock-indices = <17>, <29>;
- clock-output-names = "bus_gmac", "bus_ohci0";
- };
- apb1_parent {
- clocks = <&apb1>;
- clock-indices = <64>, <65>,
- <69>, <72>,
- <76>, <77>,
- <78>;
- clock-output-names = "bus_codec", "bus_spdif",
- "bus_pio", "bus_ths",
- "bus_i2s0", "bus_i2s1",
- "bus_i2s2";
- };
- abp2_parent {
- clocks = <&apb2>;
- clock-indices = <96>, <97>,
- <98>, <101>,
- <112>, <113>,
- <114>, <115>,
- <116>;
- clock-output-names = "bus_i2c0", "bus_i2c1",
- "bus_i2c2", "bus_scr",
- "bus_uart0", "bus_uart1",
- "bus_uart2", "bus_uart3",
- "bus_uart4";
- };
- };
-
- mmc0_clk: mmc0_clk@1c20088 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c20088 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll7 1>;
- clock-output-names = "mmc0";
- };
-
- mmc1_clk: mmc1_clk@1c2008c {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c2008c 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll7 1>;
- clock-output-names = "mmc1";
- };
-
- mmc2_clk: mmc2_clk@1c20090 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01c20090 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&pll7 1>;
- clock-output-names = "mmc2";
- };
- };
-
- soc {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-